`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY
`Patent Owner
`
`_________________
`
`Patent No. 7,116,710
`_________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,116,710
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`
`TABLE OF CONTENTS
`I.
`INTRODUCTION ........................................................................................... 1
`II. MANDATORY NOTICES ............................................................................. 1
`III.
`PAYMENT OF FEES ..................................................................................... 3
`IV. GROUNDS FOR STANDING ........................................................................ 3
`V.
`PRECISE RELIEF REQUESTED AND GROUNDS .................................... 3
`VI. LEVEL OF ORDINARY SKILL .................................................................... 5
`VII. OVERVIEW OF THE ’710 PATENT ............................................................ 6
`VIII. CLAIM CONSTRUCTION ............................................................................ 7
`A.
`“repeat” .................................................................................................. 8
`IX. DETAILED EXPLANATION OF GROUNDS .............................................. 9
`A. Ground 1: Claims 11-12, 14-17, 19, 21-22, 24-27, 29, and 32-33
`Are Anticipated By Kobayashi ............................................................. 9
`1.
`Claim 11 ...................................................................................... 9
`2.
`Claim 12 .................................................................................... 19
`3.
`Claim 14 .................................................................................... 21
`4.
`Claim 15 .................................................................................... 21
`5.
`Claim 16 .................................................................................... 23
`6.
`Claim 17 .................................................................................... 25
`7.
`Claim 19 .................................................................................... 26
`8.
`Claim 21 .................................................................................... 27
`9.
`Claim 22 .................................................................................... 27
`10. Claim 24 .................................................................................... 28
`
`i
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`

`B.
`
`C.
`
`Petition for Inter Partes Review
`Patent No. 7,116,710
`11. Claim 25 .................................................................................... 28
`12. Claim 26 .................................................................................... 32
`13. Claim 27 .................................................................................... 33
`14. Claim 29 .................................................................................... 34
`15. Claim 32 .................................................................................... 34
`16. Claim 33 .................................................................................... 36
`Ground 2: Claims 13, 16, 17, 20, 23 and 28 Are Obvious Over
`Kobayashi ............................................................................................ 36
`1.
`Claim 13 .................................................................................... 36
`2.
`Claim 16 .................................................................................... 39
`3.
`Claim 17 .................................................................................... 42
`4.
`Claim 20 .................................................................................... 43
`5.
`Claim 23 .................................................................................... 43
`6.
`Claim 28 .................................................................................... 45
`Ground 3: Claims 13, 20, and 25-33 Are Obvious Over
`Kobayashi and McEliece ..................................................................... 45
`1.
`Claim 13 .................................................................................... 45
`2.
`Claim 20 .................................................................................... 54
`3.
`Claim 25 .................................................................................... 55
`4.
`Claim 26 .................................................................................... 56
`5.
`Claim 27 .................................................................................... 57
`6.
`Claim 28 .................................................................................... 57
`7.
`Claim 29 .................................................................................... 57
`8.
`Claim 30 .................................................................................... 58
`ii
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`9.
`Claim 31 .................................................................................... 59
`10. Claim 32 .................................................................................... 61
`11. Claim 33 .................................................................................... 63
`X. DISCRETIONARY DENIAL IS NOT APPROPRIATE HERE .................. 63
`A.
`The Board Should Not Use Its Discretion to Deny Institution
`Under Fintiv ........................................................................................ 63
`The Board Should Not Exercise Its Discretion Under General
`Plastic .................................................................................................. 69
`The Board Should Not Exercise Its Discretion Under Section
`325(d) .................................................................................................. 71
`XI. CONCLUSION .............................................................................................. 72
`
`
`
`B.
`
`C.
`
`
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`iii
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`
`LIST OF EXHIBITS
`
`Ex. 1001
`
`U.S. Patent No. 7,116,710
`
`Ex. 1002
`
`Declaration of Matthew C. Valenti, Ph.D., P.E.
`
`Ex. 1003
`
`Curriculum Vitae of Matthew C. Valenti, Ph.D., P.E.
`
`Ex. 1004
`
`Prosecution History of U.S. Patent No. 7,116,710
`
`Ex. 1005
`
`U.S. Patent No. 6,029,264 to Kobayashi et al. (“Kobayashi”)
`
`Ex. 1006 McEliece et al., “Turbo Decoding as an Instance of Pearl’s ‘Belief
`Propagation’ Algorithm,” IEEE Journal On Selected Areas in
`Communication, Vol. 16, No. 2 (February 1998). (“McEliece”)
`
`Ex. 1007 MacKay, “A Free Energy Minimization Framework for Inference
`Problems in Modulo 2 Arithmetic,” Fast Software Encryption, B.
`Preneel, Ed. Berlin, Germany: Springer-Verlag Lecture Notes in
`Computer Science, Vol. 1008 (1995). (“MacKay”)
`
`Ex. 1008
`
`U.S. Patent No. 5,381,408 to Brent et al.
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
`Ex. 1013
`
`Ex. 1014
`
`Rorabaugh, Error Coding Cookbook: Practical C/C++ Routines and
`Recipes for Error Detection and Correction (1996). (“Rorabaugh”)
`
`Lin & Costello, Error Control Coding: Fundamentals and
`Applications (1983). (“Lin/Costello”)
`
`the Construction of Efficient Multilevel Coded
`Cheng, “On
`Modulations,” Proceedings 1997 IEEE International Symposium on
`Information Theory (July 1997). (“Cheng I”)
`
`Cheng, “Iterative Decoding,” Ph.D. dissertation, California Institute of
`Technology, Pasadena, CA (March 1997). (“Cheng II”)
`
`Gallager, “Low-Density Parity-Check Codes,” IRE Transactions on
`Information Theory, Vol. 8, No. 1 (January 1962).
`
`Forney, Jr., “The Viterbi Algorithm,” Proceedings of the IEEE, Vol.
`61, No. 3 (March 1973).
`
`iv
`
`

`

`Ex. 1015
`
`Petition for Inter Partes Review
`Patent No. 7,116,710
`Docket Control Order (Dkt. No. 27), from California Institute of
`Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Ex. 1016
`
`National Judicial Caseload Profile (June 30, 2022)
`
`First Amended Complaint (Dkt. No. 42), from California Institute of
`Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Plaintiff Caltech’s Infringement Disclosures, Exhibit 1 (Preliminary
`Claim Chart for U.S. Patent No. 7,116,710), from California Institute
`of Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Ex. 1017
`
`Ex. 1018
`
`
`
`v
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`
`I.
`
`INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner” or “Samsung”) requests inter
`
`partes review of claims 11-17 and 19-33 (“challenged claims”) of U.S. Patent No.
`
`7,116,710 (“the ’710 patent”) (Ex. 1001) assigned to California Institute of
`
`Technology (“PO”). For the reasons below, the challenged claims should be found
`
`unpatentable and canceled.
`
`II. MANDATORY NOTICES
`Real Parties-in-Interest: Petitioner identifies the following as the real
`
`parties-in-interest: Samsung Electronics Co., Ltd., Samsung Electronics America,
`
`Inc.
`
`Related Matters: The ’710 patent is at issue in the following matters:
`
`• California Institute of Technology v. Samsung Electronics Co., Ltd., No.
`
`2-21-cv-00446 (E.D. Tex.) (alleging infringement of the ’710 patent and
`
`also U.S. Patent Nos. 7,421,032; 7,916,781; and 8,284,833) (“E.D. Texas
`
`Litigation”).
`
`• California Institute of Technology v. Microsoft Corp., No. 6-21-cv-00276
`
`(W.D. Tex.).
`
`• California Institute of Technology v. HP Inc. f/k/a/ Hewlett-Packard Co.,
`
`No. 6-20-cv-01041 (W.D. Tex.).
`
`1
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`• California Institute of Technology v. Dell Technologies Inc., No. 6-20-cv-
`
`01042 (W.D. Tex.).
`
`• California Institute of Technology v. Broadcom Ltd., No. 2-16-cv-03714
`
`(C.D. Cal.).
`
`The ’710 patent has previously been at issue in the following matters:
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00210 (“Apple
`
`-210 IPR”).
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00211 (“Apple
`
`-211 IPR”).
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00219 (Apple -
`
`219 IPR).
`
`• California Institute of Technology v. Hughes Communications, Inc., No.
`
`2-15-cv-01108 (C.D. Cal.).
`
`• Hughes Communications, Inc. v. California Institute of Technology,
`
`IPR2015-00067 (“Hughes -067 IPR”).
`
`• Hughes Communications, Inc. v. California Institute of Technology,
`
`IPR2015-00068 (“Hughes -068 IPR”).
`
`• California Institute of Technology v. Hughes Communications, Inc., No.
`
`2-13-cv-07245 (C.D. Cal.).
`
`2
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`Counsel and Service Information: Lead counsel: Robert A. Appleby (Reg.
`
`No. 40,897), and Backup counsel is Greg S. Arovas, P.C. (Reg. No. 38,818). Service
`
`information is Kirkland & Ellis, LLP, 601 Lexington Avenue, New York, NY
`
`10022,
`
`Telephone:
`
`212.446.4800,
`
`Facsimile:
`
`212.446.4900,
`
`Email:
`
`Samsung_Caltech_IPR@kirkland.com. Petitioner consents to electronic service.
`
`III. PAYMENT OF FEES
`The PTO is authorized to charge any fees due during this proceeding to
`
`Deposit Account No. 506092.
`
`IV. GROUNDS FOR STANDING
`Petitioner certifies that the ’710 patent is available for review and Petitioner
`
`is not barred/estopped from requesting review on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED AND GROUNDS
`Claims 11-17 and 19-33 should be canceled as unpatentable based on the
`
`following grounds:
`
`Ground 1: Claims 11-12, 14-17, 19, 21-22, 24-27, 29, and 32-33 are
`
`unpatentable under pre-AIA 35 U.S.C. § 102(e) as anticipated by Kobayashi (Ex.
`
`1005);
`
`Ground 2: Claims 13, 16, 17, 20, 23, and 28 are unpatentable under § 103(a)
`
`as obvious over Kobayashi; and
`
`3
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`Ground 3: Claims 13, 20, and 25-33 are unpatentable under § 103(a) as
`
`obvious over Kobayashi and McEliece (Ex. 1006).1
`
`The ’710 patent issued October 3, 2006 from Application No. 09/861,102
`
`filed May 18, 2001, and claims priority to, inter alia, Provisional Application No.
`
`60/205,095 filed May 18, 2000. Petitioner does not concede that the priority claim
`
`to the provisional application is proper, but for purposes of this proceeding, assumes
`
`the critical date is May 18, 2000.
`
`Kobayashi was filed April 28, 1997 and issued on February 22, 2000, and thus
`
`qualifies as prior art at least under pre-AIA 35 U.S.C. §§ 102(a) and 102(e).
`
`McEliece is an article published in February 1998 in the IEEE Journal on
`
`Selected Areas in Communications. (Ex. 1006, Cover; see also id. (Library date
`
`stamp), 2 (“Copyright © 1998”).) The Board has routinely held IEEE publications
`
`like McEliece as printed publications. For example, “[t]he Board has previously
`
`observed that ‘IEEE is a well-known, reputable compiler and publisher of scientific
`
`and technical publications, and we take Official Notice that members in the scientific
`
`and technical communities who both publish and engage in research rely on the
`
`
`1 For the Grounds presented, Petitioner does not rely on any prior art reference other
`
`than those listed here. Any other references discussed herein are provided to show
`
`the state of the art.
`
`4
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`information published on the copyright line of IEEE publications.’” Power
`
`Integrations, Inc., v. Semiconductor Components Industries, LLC, IPR2018-00377,
`
`Paper No. 10 at 10 (July 17, 2018). Thus, McEliece qualifies as prior art at least
`
`under pre-AIA 35 U.S.C. § 102(b).
`
`These references were not considered during prosecution or prior IPRs. (See
`
`generally Ex. 1004.) Nor are these references cumulative of references previously
`
`before the Office.
`
`VI. LEVEL OF ORDINARY SKILL
`A person of ordinary skill in the art at the time of the alleged invention
`
`(“POSITA”) would have had a Ph.D. in mathematics, electrical or computer
`
`engineering, or computer science with an emphasis in signal processing,
`
`communications, or coding, or a master’s degree in the above areas with at least
`
`three years of work experience in the field at the time of the alleged invention. (Ex.
`
`1002, ¶¶21-22.)2 Additional education would compensate for less experience, and
`
`vice versa. (Id.)
`
`
`2 Petitioner submits the declaration of Matthew C. Valenti, Ph.D., P.E. (Ex. 1002),
`
`an expert in the field of the ’710 patent. (Ex. 1002, ¶¶3-20; Ex. 1003.)
`
`5
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`
`VII. OVERVIEW OF THE ’710 PATENT
`The ’710 patent relates to “serial concatenation of interleaved convolutional
`
`codes forming turbo-like codes.” (Ex. 1001, Title; Ex. 1002, ¶¶36-39.) The ’710
`
`patent describes a “serial concatenated coder” that “includes an outer coder and an
`
`inner coder,” where the “outer coder irregularly repeats bits in a data block according
`
`to a degree profile and scrambles the repeated bits,” which are then “input to an inner
`
`coder, which has a rate substantially close to one.” (Ex. 1001, Abstract.)
`
`An exemplary embodiment of the alleged invention is disclosed by way of
`
`Figure 2. (Id., 2:33-34.)
`
`
`
`(Id., FIG. 2.) The ’710 patent explains that “coder 200 may include an outer coder
`
`202, an interleaver 204, and inner coder 206.” (Id., 2:34-35.) The outer coder
`
`irregularly “repeats the k bits in a block” such that “different bits in the block may
`
`be repeated a different number of times.” (Id., 2:48-58.) “The bits output from the
`
`outer coder 202 are scrambled” by interleaver 204 “before they are input to the inner
`
`6
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`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`coder 206.” (Id., 3:18-22.) “The inner coder 206” may be “an accumulator, which
`
`produces outputs that are the modulo two (mod-2) partial sums of its inputs.” (Id.,
`
`2:59-67.) Together, “[t]he serial concatenation of the interleaved irregular repeat
`
`code and the accumulate code produces an irregular repeat and accumulate (IRA)
`
`code.” (Id., 3:23-25; Ex. 1002, ¶37.)
`
`The challenged claims recite limitations relating to some of the features
`
`discussed above. However, all these claim limitations were known in the prior art.
`
`(See Section IX; Ex. 1002, ¶39; see also id. ¶¶23-35 (discussing technology
`
`background and citing Ex. 1009 and Ex. 1010).)
`
`VIII. CLAIM CONSTRUCTION
`For IPR proceedings, the Board applies the claim construction standard set
`
`forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). See 83
`
`Fed. Reg. 51,340-51,359 (Oct. 11, 2018). For purposes of this proceeding, Petitioner
`
`believes that other than the term(s) discussed below in Section VIII.A, no other
`
`special constructions are necessary to assess whether the challenged claims are
`
`7
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`unpatentable over the asserted prior art, and thus any remaining terms should be
`
`given their plain and ordinary meaning.3 (Ex. 1002, ¶40.)
`
`A.
`“repeat”
`The term “repeat,” as recited in claims 11(c), 15(b), 16, 25(b), and 26, should
`
`be construed to mean “generation of additional bits, where generation can include,
`
`for example, duplication or reuse of bits.” (See, e.g., Sections IX.A.1(c), IX.A.4(b),
`
`IX.A.5, IX.A.11(b), IX.A.12; Ex. 1002, ¶41.)
`
`The Federal Circuit affirmed this construction of “repeat” in California Inst.
`
`of Tech. v. Broadcom Ltd., 25 F.4th 976, 986 (Fed. Cir. 2022) (“Broadcom
`
`litigation”). In doing so, the Federal Circuit agreed with the district court and PO
`
`that the claims simply require bits to be repeated and do not limit how the duplicate
`
`bits are created or stored in memory. Id. The Federal Circuit further clarified that
`
`“[t]he specifications confirm [the district court’s] construction and describe two
`
`embodiments, neither of which require duplication of bits.” Id. Applying this
`
`construction, the Federal Circuit found that simply passing an input bit through an
`
`
`3 Petitioner reserves all rights to raise claim construction and other arguments,
`
`including challenges under 35 U.S.C. §§ 101 or 112, in district court as relevant to
`
`those proceedings.
`
`8
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`AND gate (when the other input was “1”) was “repeating” within the context of the
`
`asserted claims. Id. at 986-88.
`
`IX. DETAILED EXPLANATION OF GROUNDS
`A. Ground 1: Claims 11-12, 14-17, 19, 21-22, 24-27, 29, and 32-33 Are
`Anticipated By Kobayashi
`1.
`Claim 11
`a)
`A method of encoding a signal, comprising:
`To the extent the preamble is limiting, Kobayashi discloses the limitations
`
`therein. (Ex. 1002, ¶¶56-57; see also id., ¶¶42-48.) For example, Kobayashi
`
`discloses a concatenated system with a transmitter that receives a signal from a
`
`source and uses several encoders that perform the “method of encoding a signal” as
`
`claimed. (Ex. 1005, FIG. 8, 5:25-27, 7:5-8:34 (describing the method in the context
`
`of Figure 8); Ex. 1002, ¶56; see also Sections IX.A.1(b)-(d).) In particular,
`
`Kobayashi discloses that the method comprises receiving a signal from a source via
`
`a “packet transmission system;” encoding the signal using the Hamming encoder,
`
`interleaver, and precoder components; and transmitting the encoded signal to the
`
`receiver via duobinary signaling. (Ex. 1005, 7:5-8:34; see also id., 7:46-48
`
`(disclosing a “simple packet transmission system in which there are 28 information
`
`bits in a packet” as the information source); Ex. 1008, Abstract (describing a “packet
`
`transmission system” as a system that “produce[s] packets” by “packetizing an input
`
`9
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`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`signal” (emphasis added))4; Section IX.A.1(d) (discussing Kobayashi’s duobinary
`
`signaling as a transmission technique while being included in Figure 8’s inner
`
`encoder); Ex. 1002, ¶57.)
`
`(Ex. 1005, FIG. 8 (annotated); see also id., 5:17-24; Ex. 1002, ¶57.)
`
`
`
`
`4 See n.1.
`
`10
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`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`(Ex. 1005, FIGS. 7A, 7B (showing generalized versions of transmitter and receiver
`
`sides of Figure 8); Ex. 1002, ¶57.)
`
`b)
`
`receiving a block of data in the signal to be encoded,
`the data block including a plurality of bits;
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶58-60.) For example,
`
`Kobayashi discloses receiving a block of data I1 in a signal to be encoded, the data
`
`block including 28 bits. (Ex. 1005, 7:46-53; see also id., 7:6-15, 11:18-19; Ex. 1002,
`
`¶58.)
`
`In particular, Kobayashi discloses that the concatenated system’s transmitter
`
`receives data via “a simple packet transmission system in which there are 28
`
`information bits in a packet, an example of which is given by the stream:
`
`I1=(0001001000110100010101100000).” (Ex. 1005, 7:46-49.) Thus, Kobayashi’s
`
`method comprises “receiving a block of data in the signal” because the transmitter
`
`receives a stream of bits from a signal, where the stream of bits is comprised of 28-
`
`bit packets, each forming a binary data block from a signal. (Ex. 1002, ¶59; Ex.
`
`1008, Abstract (describing a “packet transmission system” as a system that
`
`“produce[s] packets” by “packetizing an input signal” (emphasis added)).) The 28-
`
`bit binary data sequence I1 is encoded by the outer code (Hamming code), but
`
`“[r]ather than encoding the entire packet at once, it is first segmented into [sub-
`
`11
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`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`]blocks5 of k=4 bits, and each block is then encoded to a codeword of length n=7,
`
`by using a (7, 4) Hamming code.” (Ex. 1005, 7:50-53; see also id., 7:6-15
`
`(describing Hamming codes), 11:18-19 (“the information source is binary data”).)
`
`Kobayashi thus discloses “receiving a block of data in the signal to be encoded”
`
`because after the concatenated system receives block of data I1 from an input signal,
`
`the block is subsequently encoded by the Hamming code. (Ex. 1002, ¶60; see also
`
`Section IX.A.1(c)-(d) (describing further encoding steps).) Moreover, “the data
`
`block includ[es] a plurality of bits” because block I1 is a binary sequence having 28
`
`bits. (Ex. 1002, ¶60.)
`
`c)
`
`first encoding the data block such that each bit in the
`data block is repeated and two or more of said
`plurality of bits are repeated a different number of
`times in order to form a first encoded data block; and
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶61-68.) Kobayashi
`
`discloses that 28-bit data block I1 is “first segmented into [sub-]blocks of k=4 bits,
`
`and each [sub-]block is then encoded to a codeword of length n=7, by using a (7, 4)
`
`Hamming code.” (Ex. 1005, 7:50-53.) Kobayashi discloses that the Hamming
`
`code’s parity-check and generator matrices are represented in systematic form as
`
`follows:
`
`
`5 Kobayashi’s “block” is a sub-block of “the entire packet” (e.g., a “claimed data
`
`block”). (Ex. 1005, 7:50-53).
`
`12
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`
`
`
`(Id., 7:53-65.) After the Hamming encoder is applied to all seven sub-blocks of
`
`block I1, “the Hamming encoder output is the following 49 bits (commas are placed
`
`between code words for clarity): I2=(0001101, 0010111, 0011010, 0100011,
`
`0101110, 0110100, 0000000).” (Id., 7:66-8:2; Ex. 1002, ¶61.) A “7x7 block
`
`interleaver” is then used to “perform a permutation action . . . which will store the
`
`above 49 bits [of I2] row-wise in the following array structure.”
`
`
`
`(Ex. 1005, 8:3-15.) Kobayashi discloses that the “permutation output is obtained by
`
`“reading out the above array column by column as follows: I3=(0000000, 0001110,
`
`0110010, 1010100, 1100110, 0111100, 1101000).” (Id., 8:16-20; Ex. 1002, ¶62.)
`
`
`
`Kobayashi discloses “first encoding the data block” I1 via a Hamming encoder
`
`and interleaver “to form a first encoded data block” I3 because, as described above
`
`and shown below, the Hamming encoder and interleaver components comprise the
`
`13
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`

`

`Petition for Inter Partes Review
`Patent No. 7,116,710
`first encoding step of the Kobayashi method. (Ex. 1002, ¶63.) As discussed further
`
`infra Section IX.A.1(d), the “first encoded data block” I3 is the input to the second
`
`encoding step of the Kobayashi method. (See Section IX.A.1(d); Ex. 1002, ¶63.)
`
`
`
`(Ex. 1005, FIG. 8 (annotated).)
`
`Moreover, under the Federal Circuit’s affirmance of “repeat” from the
`
`Broadcom litigation (see Section VIII.A), “each bit in the data block [I1] is repeated
`
`and two or more of said plurality of bits are repeated a different number of times” in
`
`order to form encoded data block I3. (Ex. 1002, ¶64.) As discussed, the Federal
`
`Circuit found that passing an input information bit through an AND gate when the
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`other input is a “1” bit comprises “repeating” the information bit. (See Section
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`VIII.A.) Multiplying a binary information bit by a “1” bit is equivalent to passing
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`Patent No. 7,116,710
`the information bit through an AND gate with a “1” bit, and thus under this
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`construction of “repeat,” multiplying an information bit by a “1” bit comprises
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`“repeating” the information bit. (Ex. 1002, ¶64; see also Ex. 1009, 7-8 (disclosing
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`that binary/modulo-2 multiplication is equivalent to a bitwise AND operation)6.)
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`Accordingly, under this construction, any type of linear code using a non-zero
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`generator matrix will “repeat” input bits because the process of multiplying a vector
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`of information bits by the generator matrix will necessarily involve multiplying input
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`bits by “1” bits. (Ex. 1002, ¶64.)
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`For example, as described above, Kobayashi’s Hamming encoder multiplies
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`each 4-bit sub-block of I1 by the 4x7 generator matrix G, resulting in seven 7-bit
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`codewords. (Id., ¶65.) The interleaving operation permutes the order of these bits
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`in order to form a 49-bit “first encoded data block” I3. (Id.) This “first encoding”
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`step performs repetition of each and every information bit because the process of
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`multiplying each 4-bit sub-block by generator matrix G involves multiplying each
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`input bit by at least one “1” bit (i.e., repeating the input bits) and then summing the
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`repeated bits to generate the codeword. (Id.) Moreover, the information bits are
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`repeated irregularly such that information bits are repeated a different number of
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`times. (Id., ¶66.) The example below shows the first 4-bit sub-block of data block
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`6 See n.1.
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`I1 (in green) being multiplied by 4x7 generator matrix G. (Id.) As shown, the first,
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`second, and fourth bits of the sub-block are “repeated” (multiplied by a “1” bit) three
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`times because the first, second, and fourth rows of generator matrix G each have
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`three “1”s (in blue). (Id.) However, the third bit of the sub-block is repeated four
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`times because the third row of generator matrix G has four “1”s (in yellow). (Id.)
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`The repeated bits are summed to generate the 7-bit codeword. (Id.)
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`
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`(Id.) When the full 28-bit data block I1 is encoded via the Hamming encoder, the
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`3rd, 7th, 11th, 15th, 19th, 23rd, and 27th bits are repeated four times, while the other 21
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`bits are repeated three times. (Id., ¶67.) The interleaver merely permutes the
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`sequence I2 to result in “first encoded data block” I3, and does not otherwise alter the
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`bits of the Hamming encoder output. (Id.) Thus, every bit in data block I1 is
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`repeated, and two or more of the bits of I1 are repeated a different number of times—
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`some three times and some four times—to form encoded data block I3. (Id.)
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`Accordingly, Kobayashi discloses “first encoding the data block [I1] such that
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`each bit in the data block is repeated and two or more of said plurality of bits are
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`repeated a different number of times in order to form a first encoded data block [I3].”
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`(Id., ¶68.)
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`d)
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`second encoding the first encoded data block in such a
`way that bits in the first encoded data block are
`accumulated.
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶69-72.) Kobayashi
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`discloses that the precoder in Figure 8 performs a “second encoding” step as claimed.
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`(Ex. 1005, 8:18-27.)
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`
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`(Id., FIG. 8 (annotated); Ex. 1002, ¶69.)7
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`7 While duobinary signaling is depicted in Figure 8 as part of the “inner encoder,”
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`Kobayashi discloses that duobinary signaling is simply a transmission technique,
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`Kobayashi discloses that the precoder takes as an input the “first encoded data
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`
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`block” I3, for example, the sequence “I3=(0000000, 0001110, 0110010, 1010100,
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`1100110, 0111100, 1101000).” (Ex. 1005, 8:18-27.) “The precoder output is
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`obtained by taking the modulo-2 sum of the current input and the previous output
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`(where ‘modulo-2 summation’ can be implemented by Exclusive OR: 0+0=0,
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`0+1=1, 1+0=1, 1+1=0).” (Id., 8:21-24.) In other words, “[t]he precoder maps the
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`input binary sequence into another binary sequence, based on the following rule:
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`when the current input is 0, the output should remain in the previous value; and when
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`the input is 1, the output changes its value from the previous one, i.e. either 0 to 1 or
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`from 1 to 0.” (Id., 7:33-37.) The resulting encoded sequence is “I4=(0000000,
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`and thus the precoder is the inner encoder component that performs the “second
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`encoding” step as claimed. (Ex. 1005, 7:30-31 (“The precoder introduces a simple
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`transformation prior to the transmission by duobinary signaling.”), 7:43-45
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`(“Duobinary signaling illustrated in this example is a simplest case of partial-
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`response channel coding referred to in the Background of the Art.”); see also id.,
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`2:21-25 (“Partial-response channel coding is well recognized as a bandwidth-
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`efficient transmission technique . . .”); Ex. 1002, ¶69 n.3.)
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`0001011, 1011100, 1100111, 0111011, 1010111, 011000[0]).” (Id., 8:25-27; Ex.
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`1002, ¶70.)8
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`
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`The precoder is an accumulator that accumulates the bits in first encoded data
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`block I3 because the precoder’s operations involve taking the modulo-2 partial sum
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`of the current input of I3 and the immediately previous output of I4 (i.e., the modulo-
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`2 partial sum of all previous inputs up to the current input). (Ex. 1002, ¶71.) This
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`understanding is consistent with the accumulation operations disclosed by the ’710
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`patent. (Id.; Ex. 1001, 2:65-3:17 (describing accumulation of bits using mod-2
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`operations).)
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`Accordingly, Kobayashi discloses “second encoding the first encoded data
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`block” I3 via the precoder “in such a way that bits in the first encoded data block are
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`accumulated” to result in encoded sequence I4. (Ex. 1002, ¶72.)
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`2.
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`Claim 12
`a)
`The method of claim 11, wherein the said second
`encoding is via a rate 1 linear transformation.
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶73-74.) As explained,
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`the precoder performs the “second encoding” by accumulating bits of the first
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`8 A POSITA would have understood based on the context that the I4 sequence
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`contains a typographical error (missing the 49th bit), which a POSITA would have
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`understood to be a “0.” (Ex. 1002, ¶70 n.4.)
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`encoded data block I3 and outputting 49-bit sequence I4. (See Section IX.A.1(d).)
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`The second encoding is a “rate 1 [] transformation” because the precoder’s
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`accumulation operation takes an input of 49 bits (k=49) and outputs 49 bits (n=49)
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`and thus the rate is k/n = 49/49 = 1. (Ex. 1002, ¶73; see also Ex. 1009, 114-16
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`(disclosing that the code rate is R = k/n where k is the number of input bits and n is
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`the number of output bits)9.)
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`The second encoding is also a “linear transformation” because the precoder’s
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`accumulation operation can be represented as a (49, 49) linear block code. (Ex.
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`1002, ¶74.) In particular, the accumulation operation is equivalent to multiplying
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`the 1x49 vector I3 by a 49x49 generator matrix GA with “1”s both alon