Trials@uspto.gov
`571-272-7822
`
`Paper 7
`Date: May 24, 2023
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`GOOGLE LLC,
`Petitioner,
`v.
`LS CLOUD STORAGE TECHNOLOGIES LLC,
`Patent Owner.
`
`IPR2023-00120
`Patent 10,154,092 B2
`
`
`
`
`
`
`
`
`
`Before LARRY J. HUME, MINN CHUNG, and AMBER L. HAGY,
`Administrative Patent Judges.
`HUME, Administrative Patent Judge.
`
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`

`

`IPR2023-00120
`Patent 10,154,092 B2
`
`INTRODUCTION
`I.
`Google LLC (“Petitioner”)1 filed a Petition (Paper 2, “Pet.”)
`requesting inter partes review (“IPR”) of all claims 1–24 (“the challenged
`claims”) of U.S. Patent No. 10,154,092 B2 (Ex. 1001, “the ’092 patent”).
`LS Cloud Storage Technologies LLC (“Patent Owner”) timely filed a
`Preliminary Response. Paper 6 (“Prelim. Resp.”).
`An inter partes review may not be instituted unless “the information
`presented in the petition . . . and any response . . . shows that there is a
`reasonable likelihood that the petitioner would prevail with respect to at least
`one of the claims challenged in the petition.” 35 U.S.C. § 314(a);
`see 37 C.F.R. § 42.4.
`Having reviewed the parties’ papers and the evidence of record, we
`determine that Petitioner has shown a reasonable likelihood it will prevail in
`establishing the unpatentability of at least one challenged claim.
`Accordingly, we institute an inter partes review of all challenged claims 1
`through 24 of the ’092 patent, based on the grounds raised in the Petition.
`
`II. BACKGROUND
`A. Related Matters
`The parties indicate that the ’092 patent has been asserted in various
`district court lawsuits, including: LS Cloud Storage Technologies, LLC v.
`
`
`1 Petitioner identifies its parent entity as XXVI Holdings Inc., which is a
`subsidiary of Alphabet Inc. Petitioner states that neither XXVI Holdings Inc.
`nor Alphabet Inc. are real parties-in-interest to this proceeding. Pet. 2, n.1.
`
`2
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`

`

`IPR2023-00120
`Patent 10,154,092 B2
`Google LLC, No. 6:22-cv-00318 (W.D. Tex. 2022). Pet. 2; Paper 4 (Patent
`Owner Mandatory Notices), 2. 2
`After filing of the Petition and Patent Owner’s Response, the ’092
`patent has become the subject of one other petition for inter partes review
`and Motion for Joinder, i.e., IPR2023-00733 (filed by Cisco Systems, Inc.,
`Microsoft Corporation, Amazon.Com, Inc., Amazon Web Services, Inc., and
`Amazon.Com Services LLC). The Decision whether to institute inter partes
`review in IPR2023-00733 and effect joinder with this proceeding will be
`made in due course.
`
`B. The ’092 Patent
`The ’092 patent is titled “Data Sharing Using Distributed Cache in a
`Network of Heterogeneous Computers.” Ex. 1001, code (54). The
`’092 patent issued December 11, 2018, from U.S. Patent Application
`No. 14/997,327, filed January 15, 2016, claiming benefit as a continuation
`application under 35 U.S.C. § 120 to a series of applications, and ultimately
`claiming benefit as a divisional application under 35 U.S.C. § 121 of U.S.
`Patent Application No. 09/236,409 filed on January 22, 1999, and issued on
`April 15, 2003. Id. at codes (21), (22), (45), (60). We note the ’092 patent
`term appears to have expired on September 16, 2019.
`
`
`2 In addition, Patent Owner has asserted the ’092 patent against other
`parties, i.e., LS Cloud Storage Technologies, LLC v. Amazon.com, Inc. et al.,
`6:22-cv-00316 (W.D. Tex. 2022); LS Cloud Storage Technologies, LLC v.
`Cisco Systems, Inc., 6:22-cv-00319 (W.D. Tex. 2022) (dismissed); LS Cloud
`Storage Technologies, LLC v. Microsoft Corporation, 6:22-cv-00321 (W.D.
`Tex. 2022); and LS Cloud Storage Technologies, LLC v. Cisco Systems, Inc.,
`6:22-cv-00845 (W.D. Tex. 2022). See Paper 4, 2; see also Pet. 2.
`
`3
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`IPR2023-00120
`Patent 10,154,092 B2
`The ’092 patent describes a network of PCs that includes an
`input/output (I/O) channel adapter and network adapter, configured for
`management of a distributed cache memory stored in the plurality of PCs
`interconnected by the network. See Ex. 1001, code (57) (Abstr.). According
`to the ’092 patent, the use of standard PCs serves to reduce the cost of the
`data storage system, and using networked PCs permits building large, high-
`performance data storage systems. Id. The ’092 patent further describes:
`This invention relates generally to the field of cached
`data storage systems and more particularly to a data storage
`system that permits independent access from local hosts
`connected via I/O channels and independent access from remote
`hosts and remote storage systems connected via network links.
`A network of PCs permits building a high-performance,
`scalable, data storage system using off-the-shelf components at
`reduced cost. A configuration manager ensures consistency of
`data stored in the distributed cache.
`Id. at 1:18–26.
`As background, the ’092 patent describes the prior art as follows:
`A typical data processing system generally involves a
`cached data storage system that connects to local host
`computers via I/O channels or remote host computers via
`network links. The purpose of the data storage system is to
`improve the performance of applications running on the host
`computer by offloading I/O processing from the host to the data
`storage system. The purpose of the cache memory in a data
`storage system is to further improve the performance of the
`applications by temporarily storing data buffers in the cache so
`that the references to those buffers can be resolved efficiently as
`“cache hits”. Reading data from a cache is an order of
`magnitude faster than reading data from a back end storage
`device such as a disk. Writing data to a cache is also an order of
`magnitude faster than writing to a disk. All writes are cache hits
`because data is simply copied into cache buffers that are later
`flushed to disks.
`
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`IPR2023-00120
`Patent 10,154,092 B2
`Id. at 1:30–45. The ’092 patent also describes the need for improvements in
`distributed data storage systems at the time of the invention:
`There is a growing demand for distributed data storage
`systems. In response to this demand some prior art systems
`have evolved into complex assemblies of two systems, one
`proprietary a data storage system and the other an open
`networking server. One such system is described in a white
`paper on a company web site on Internet. The industry white
`paper, EMC Data Manager: A high-performance, centralized
`open system backup/restore solution for LAN-based and
`Symmetrix resident data, describes two different systems, one
`for network attached hosts and second for channel attached
`hosts. The two systems are needed because of the lack of
`generic networking support. In related products such as Celerra
`File Server, product data sheets suggest using data movers for
`copying data between LAN-based open system storage and
`channel attached storage system.
`However, the above systems are built from two systems,
`one for handling I/O channels, and another for handling open
`networks. Two systems are very expensive even in minimal
`configuration that must include two systems.
`Id. at 2:42–60.
`The background of the ʼ092 patent concludes by stating that there is a
`need “to provide a high-performance data storage system that is assembled
`out of standard modules, using off-the-shelf hardware components and a
`standard general-purpose operating system that supports standard network
`software and protocols.” Id. at 3:30–34. Further, the background of the
`ʼ092 patent identifies a need “to provide a cached data storage system that
`permits independent data accesses from I/O channel attached local hosts,
`network attached remote hosts, and network-attached remote data storage
`systems.” Id. at 3:35–38.
`
`5
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`IPR2023-00120
`Patent 10,154,092 B2
`Against this backdrop, the ʼ092 patent describes embodiments of a
`cached storage system that includes a network of personal computers (PCs)
`with an I/O channel adaptor and a network adaptor configured for
`management of a distributed cache memory stored in the network-connected
`PCs. Id., Abstr. Figure 1 of the ʼ092 patent is reproduced below as an aid in
`understanding the claimed invention.
`
`Figure 1 of the ʼ092 patent “shows data storage systems
`configurations” (id. at 4:50) illustrating a network of data storage systems
`(131, 132, 133).
`
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`IPR2023-00120
`Patent 10,154,092 B2
`In the preferred embodiment shown in Figure 1 of the ʼ092 patent,
`“PC data storage system 131 services a plurality of channel attached host
`processors 111, 112 using channels 121, 122, and a plurality of network
`attached host processors 106, 107 using network link 151, and a plurality of
`network attached data storage systems 132, 133 using network links 152,
`153.” Ex. 1001, 5:10–15. In addition, “PC storage system 132 services
`channel attached hosts 157, 158.” Id. at 5:15–16. The ʼ092 patent further
`describes that
`Hosts 157 and 158 access a data storage system 131
`indirectly via network attached data storage system 132,
`thereby offloading communications protocol overhead from
`remote hosts 157, 158. Hosts 106 and 107 directly access
`storage system 131 via network link 151 thereby incurring
`communications protocol overhead on hosts 106, 107 and
`therefore decreasing performance of applications running on
`said hosts.
`Host 111 accesses remote disk 181 via local data storage
`system 131, network link 153, and remote data storage system
`133 without incurring protocol overhead on host 111. Host 157
`accesses disk 161 via data storage system 133, network link
`152, and data storage system 131 without incurring protocol
`overhead on host 157. Host 106 directly accesses local disk 161
`via network link 151 thereby incurring protocol overhead. The
`disks 191, 192 that are attached to hosts 106, 107 without a data
`storage system, cannot be accessed by outside hosts.
`Id. at 5:17–34; see also Ex. 2001 (PO Declaration of Dr. Hassan Zeino,
`Ph.D, hereinafter “Zeino Declaration”) ¶¶ 27–28 (in which Dr. Zeino
`discusses the disclosures relating to Figure 1 of the ʼ092 patent (citing
`Ex. 1001, 5:9–24, Fig. 1)).
`The ʼ092 patent describes that “[t]he presence of fast access cache
`memory permits front end channels and network links to operate completely
`independent of the back-end physical disk devices. Because of this front-
`
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`IPR2023-00120
`Patent 10,154,092 B2
`end/back-end separation, the data storage system 131 is liberated from the
`I/O channel and network timing dependencies.” Ex. 1001, 6:1–6. As a
`result, processing resources may be dedicated to increase performance
`through better scheduling and utilization of data transfer network protocol.
`Id. at 6:6–8.
`
`C. Illustrative Claims
`Of the challenged claims, claims 1, 13, 19, and 24 are independent,
`and for purposes of this Decision, claims 1, 4, 5, 10, and 13 are illustrative
`of the challenged claims, and are reproduced below:
`Claim 1 recites:
`[1.pre] An apparatus comprising:
`[1.a] a first interface configured to receive input/output
`(I/O) traffic from a first host device via a dedicated I/O channel,
`the I/O traffic comprising a read command;
`[1.b] a second interface configured to receive first data
`via a network;
`[1.c] a cache memory configured to store second data;
`[1.d] a storage device configured to store third data; and
`[1.e] a processor coupled to the cache memory, the
`processor coupled to the storage device via a communication
`path that is distinct from the dedicated I/O channel, the
`processor configured to access the cache memory during
`processing of the I/O traffic,
`[1.f] the processor further configured to perform an
`access operation at the storage device based on the I/O traffic.
`Ex. 1001, 9:20–34 (Petitioner-provided bracketed labeling added for ease of
`reference); see Pet. 21–30.
`
`8
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`IPR2023-00120
`Patent 10,154,092 B2
`Claim 4 recites:
`4.
`The apparatus of claim 1, wherein the dedicated
`I/O channel comprises a small computer system interface
`(SCSI) channel.
`Ex. 1001, 9:40–42.
`Claim 5 recites:
`5.
`The apparatus of claim 1, wherein the second
`interface comprises an Ethernet interface or an asynchronous
`transfer mode (ATM) interface.
`Ex. 1001, 9:43–45.
`Claim 10 recites:
`10. The apparatus of claim 1, wherein the processor is
`further configured to route the read command to the cache
`memory or to the storage device.
`Ex. 1001, 9:58–60.
`Claim 13 recites:
`13.
`[13.pre] A method comprising:
`[13.a] receiving input/output (I/O) traffic from a host
`device via a dedicated I/O channel at a first interface, the I/O
`traffic comprising a write command;
`[13.b] receiving first data via a network at a second
`interface;
`[13.c] storing second data at a cache memory;
`[13.d] storing third data at a storage device;
`[13.e] accessing the cache memory during processing of
`the I/O traffic; and
`[13.f] performing one or more access operations at the
`storage device based on the I/O traffic, the one or more access
`operations utilizing a communication path between a processor
`and the storage device, the communication path distinct from
`the dedicated I/O channel.
`
`9
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`

`IPR2023-00120
`Patent 10,154,092 B2
`Ex. 1001, 10:6–19 (Petitioner-provided bracketed labeling added for ease of
`reference); see Pet. 51–53.
`
`Reference(s)/Basis
`
`D. Asserted Grounds of Unpatentability
`Petitioner asserts the following grounds 1 through 5 of unpatentability
`(Pet. 4–5, 21–76):
`Ground Claim(s) Challenged 35 U.S.C.
`3 §
`102(e) Heil4
`102(b) Heil
`103(a) Heil, Nakayama5
`103(a) Heil, Nakayama, Gulick6
`103(a) Heil, Nakayama, Berman7
`
`1
`2
`3
`4
`5
`
`1–3, 7–12, 19–23
`10, 11
`1–3, 6–24
`4
`5
`
`
`3 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29,
`125 Stat. 284, 285–88 (2011), revised 35 U.S.C. §§ 102 and 103 effective
`March 16, 2013. The ’092 patent claims benefit under 35 U.S.C. § 120 to
`applications filed before that date, so we refer to the pre-AIA version of the
`statute, but our findings and analysis would be the same under the current
`version of the statute.
`4 US 6,173,374 B1, filed Feb. 11, 1998, issued Jan. 9, 2001 (Ex. 1006,
`“Heil”).
`5 US 5,920,893, filed June 2, 1997, issued July 6, 1999. (Ex. 1007,
`“Nakayama”).
`6 US 5,692,211, filed Sept. 11, 1995, issued Nov. 25, 1997 (Ex. 1008,
`“Gulick”).
`7 US 6,118,776, filed Aug. 7, 1997, issued Sept. 12, 2000 (Ex. 1009,
`“Berman”).
`
`10
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`

`IPR2023-00120
`Patent 10,154,092 B2
`Petitioner supports its challenge with a declaration from Dr. Paul
`Franzon, Ph.D. (Ex. 1004, “Franzon Declaration”).
`
`III. ANALYSIS
`A. Legal Standards
`“In an [inter partes review], the petitioner has the burden from the
`onset to show with particularity why the patent it challenges is
`unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
`Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`petitions to identify “with particularity . . . the evidence that supports the
`grounds for the challenge to each claim”)). This burden of persuasion never
`shifts to the patent owner. Dynamic Drinkware, LLC v. Nat’l Graphics, Inc.,
`800 F.3d 1375, 1378 (Fed. Cir. 2015).
`“A single prior art reference that discloses, either expressly or
`inherently, each limitation of a claim invalidates that claim by anticipation.”
`Perricone v. Medicis Pharm. Corp., 432 F.3d 1368, 1375–76 (Fed.
`Cir. 2005). To establish anticipation, each and every element in a claim,
`arranged as recited in the claim, must be found in a single prior art reference.
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008);
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed.
`Cir. 2001).
`Further, a “reference must describe the claimed invention with
`sufficient precision and detail to establish that the subject matter existed in
`the prior art.” Verve, LLC v. Crane Cams, Inc., 311 F.3d 1116, 1120 (Fed.
`Cir. 2002). The reference does not need to use the same terminology.
`Kennametal, Inc. v. Ingersoll Cutting Tool Co., 780 F.3d 1376, 1381 (Fed.
`Cir. 2015) (noting that a reference anticipates if a person of skill in the art
`
`11
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`IPR2023-00120
`Patent 10,154,092 B2
`“would at once envisage the claimed arrangement or combination” (internal
`quotation marks and citation omitted)). But, an ambiguous reference will
`not anticipate a claim. Wasica Fin. GmbH v. Cont’l Auto. Sys., Inc.,
`853 F.3d 1272, 1284 (Fed. Cir. 2017). The dispositive question for
`anticipation is whether one skilled in the art would reasonably understand or
`infer from the reference that every claim element is disclosed. Eli Lilly &
`Co. v. Los Angeles Biomedical Research Inst. at Harbor-UCLA Medical
`Ctr., 849 F.3d 1073, 1074–75 (Fed. Cir. 2017).
`The legal question of obviousness is resolved on the basis of
`underlying factual determinations including (1) the scope and content of the
`prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of ordinary skill in the art; and (4) when in evidence,
`objective evidence of nonobviousness. 8 Graham v. John Deere Co., 383
`U.S. 1, 17–18 (1966). One seeking to establish obviousness based on more
`than one reference also must articulate sufficient reasoning with rational
`underpinnings to combine teachings. See KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398, 418 (2007).
`
`B. Level of Ordinary Skill in the Art
`Supported by the testimony of Dr. Franzon, Petitioner asserts that the
`level of ordinary skill in the art corresponds to a person having “a bachelor’s
`degree in Computer Science, Computer Engineering, or Electrical
`Engineering, or an equivalent course of study, as well as 2 or more years of
`academic or industry experience in the field of computer networking,
`
`
`8 The current record does not include allegations or evidence of objective
`indicia of nonobviousness (secondary considerations).
`
`12
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`

`IPR2023-00120
`Patent 10,154,092 B2
`computer architecture and storage management. . . . More education can
`supplement practical experience, and vice versa.” Pet. 17–18 (citing
`Ex. 1004 ¶¶ 34–36).
`At this stage, “Patent Owner agrees to Petitioner’s proffered level of
`ordinary skill in the art because it comports with the technology and claims
`of the ’092 Patent as well as the asserted prior art.” See Prelim. Resp. 11.
`For purposes of this Decision, we adopt Petitioner’s unopposed
`position as to the level of ordinary skill in the art at the time of the claimed
`invention, as articulated above. We are satisfied that Petitioner’s proposed
`definition generally comports with the level of skill necessary to understand
`and implement the teachings of the ’092 patent and the asserted prior art.
`This definition is also supported by the testimony of Dr. Franzon (see
`Ex. 1004 ¶¶ 34–36), as well as a declaration from Patent Owner’s declarant,
`Dr. Hassan Zeino, Ph.D. See Ex. 2001 ¶ 24 (“Zeino Declaration”).
`
`C. Claim Construction
`In an inter partes review, we apply the same claim construction
`standard that would be used in a civil action under 35 U.S.C. § 282(b),
`following the standard articulated in Phillips v. AWH Corp., 415 F.3d 1303
`(Fed. Cir. 2005) (en banc). 37 C.F.R. § 42.100(b) (2019). In applying such
`standard, claim terms are generally given their ordinary and customary
`meaning, as would be understood by a person of ordinary skill in the art, at
`the time of the invention and in the context of the entire patent disclosure.
`Phillips, 415 F.3d at 1312–13. “In determining the meaning of the disputed
`claim limitation, we look principally to the intrinsic evidence of record,
`examining the claim language itself, the written description, and the
`prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
`
`13
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`

`IPR2023-00120
`Patent 10,154,092 B2
`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips,
`415 F.3d at 1312–17).
`“Petitioner interprets all terms of claims 1–23 in accordance with their
`ordinary and customary meaning.” Pet. 18. Petitioner further states that
`claim 24 recites various “means for” limitations that “are means-plus-
`function limitations governed by 35 U.S.C. § 112[, sixth paragraph].” Id.
`Patent Owner responds that “the terms of claims 1–4 (and all other
`challenged claims) of the ’092 Patent are clear on their face,” and “Patent
`Owner reserves the right to propose further constructions if necessary.”
`Prelim. Resp. 5.
`However, notwithstanding the parties’ stated positions, we note
`claim 1 of the ’092 patent recites, inter alia, “a first interface configured to
`receive input/output (I/O) traffic from a first host device via a dedicated I/O
`channel, the I/O traffic comprising a read command.” Ex. 1001, 9:21–23
`(emphasis added).
`We find no express definition of “dedicated I/O channel” in the
`disclosure of the ’092 patent or the related prosecution history (see generally
`Ex. 1002 (File History of U.S. Patent No. 10,154,092) and Ex. 1003 (File
`History of U.S. Patent No. 6,549,988)). Further, Patent Owner asserts:
`Heil does not disclose “a first interface configured to receive
`input/output (I/O) traffic from a first host device via a dedicated
`I/O channel.” The channel used by the PCI bus bridge 115 and
`PCI bus 116.5 is used for other communications besides I/O
`requests, for example arbitrary communications among peer
`CPUs (Heil, Col. 8, lines 8–18) and thus the PCI bus bridge 115
`and PCI bus 116.5 simply cannot be and cannot serve as a
`dedicated I/O channel.
`Prelim. Resp. 15 (italics added).
`
`14
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`IPR2023-00120
`Patent 10,154,092 B2
`Patent Owner’s assertion highlights a potential claim construction
`dispute. Although Patent Owner highlights this potential dispute and
`characterizes Petitioner’s position regarding the teachings of Heil as
`improper, Patent Owner does not explicitly propose any construction.
`Prelim. Resp. 12–16; Ex. 2001 (Zeino Declaration) ¶¶ 4–5. Likewise,
`Petitioner does not offer any proposed construction of the phrase “dedicated
`I/O channel.” See Pet. 18–21. Thus, we are left without guidance from the
`parties on this issue.
`Lacking guidance, we nevertheless consider whether independent
`claim 1 and, similarly, independent claims 13, 19, and 24, require that the
`recitation of “dedicated I/O channel” either be construed as (1) requiring a
`node-based approach using an exclusive communication channel dedicated
`between two components, e.g., a central processing unit (CPU) and a
`peripheral I/O device, over which dedicated input/output requests are
`transmitted, thus precluding sharing of the channel with other CPUs and
`peripheral I/O devices; or (2) as a channel that is dedicated exclusively for a
`certain type of data, i.e., I/O requests, thus encompassing load sharing
`configurations that share the I/O channel between multiple CPUs and I/O
`peripheral devices.
`The only allusion provided by Patent Owner as to how “dedicated I/O
`channel” should be construed is found in Dr. Zeino’s declaration: “The PC
`data storage system 131 services a plurality of channel attached host
`processors 111, 112 using dedicated I/O channels 121, 122, and a plurality
`of network attached host processors 106, 107. . . .” Ex. 2001 ¶ 27 (emphasis
`added); see also Prelim. Resp. 3–4 (relying upon the same description as
`Dr. Zeino). Elements 121 and 122 are illustrated in Figure 1 of the ʼ092
`patent. See Ex. 1001, Fig. 1 (reproduced, supra).
`
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`IPR2023-00120
`Patent 10,154,092 B2
`Based on the current record, given Patent Owner’s argument cited
`above that Heil’s configuration does not meet the limitation “dedicated I/O
`channel” because of other types of data purportedly being communicated
`over the channel, we infer from Patent Owner’s assertion and Dr. Zeino’s
`statement that the second claim construction issue articulated above is
`relevant, i.e., whether a “dedicated I/O channel” should be interpreted as a
`channel that is used exclusively for a certain type of data, i.e., I/O requests.
`We find that, in contrast to Patent Owner’s and Dr. Zeino’s assertions,
`the ʼ092 patent provides a somewhat broader description of elements 121
`and 122, to wit: “The PC data storage system 131 services a plurality of
`channel attached host processors 111, 112 using channels 121, 122, and a
`plurality of network attached host processors 106, 107. . . .” Ex. 1001,
`5:10–13 (omitting Dr. Zeino’s proffered words “dedicated I/O” (Ex. 2001
`¶ 27 (emphasis added)). The ʼ092 patent goes on to later describe channels
`121 and 122 as “I/O channels.” Ex. 1001, 5:51. We have reviewed the ʼ092
`patent and prosecution history, and find no further intrinsic evidence of
`record, i.e., original disclosure or arguments presented during prosecution,
`that would provide additional context for the “dedicated I/O channel”
`limitation.
`Nonetheless, for purposes of this Decision, we need not determine
`whether a “dedicated I/O channel” can transmit data other than I/O requests
`because, as discussed in Section III.E.1 below, Petitioner shows sufficiently
`that Heil discloses a “dedicated I/O channel” even under the claim
`construction inferred from Patent Owner’s argument. See Nidec Motor
`Corp. v. Zhongshan Broad Ocean Motor Co. Matal, 868 F.3d 1013, 1017
`(Fed. Cir. 2017) (noting that “we need only construe terms ‘that are in
`controversy, and only to the extent necessary to resolve the controversy’”
`
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`IPR2023-00120
`Patent 10,154,092 B2
`(quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`(Fed. Cir. 1999))). Thus, based on the current record and purposes of this
`Decision, we preliminarily construe a “dedicated I/O channel” as a channel
`that is used exclusively for a certain type of data, i.e., I/O requests, thus
`encompassing load sharing configurations that share the I/O channel
`between multiple CPUs and I/O peripheral devices for communication of
`I/O requests.
`At this stage of the proceeding, based on the parties’ stated positions,
`we do not find it necessary to address the construction of any other claim
`terms or phrases. See Nidec, 868 F.3d at 1017.
`We further note our claim construction analysis in this Decision is
`preliminary, and does not preclude the parties from arguing proposed
`constructions of the claims during trial. Indeed, the parties are hereby given
`notice that claim construction, in general, is an issue to be addressed at trial.
`Claim construction will be determined at the close of all the evidence and
`after any hearing. The parties are expected to assert all their claim
`construction arguments and evidence in the Petition, Patent Owner’s
`Response, Petitioner’s Reply, Patent Owner’s Sur-reply, or otherwise during
`trial, as permitted by our rules.
`
`D. Summary of Asserted Prior Art References
`1. Heil (Ex. 1006)
`Heil describes data storage systems and an apparatus and method in
`which host computers may store files in a cache or disk storage. Ex. 1006,
`Abstr., 1:9–14, 6:34–47. Figure 1 of Heil is reproduced below.
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`“FIG. 1 depicts a host system in which the present invention may be
`advantageously applied.” Id. at 6:33–34.
`In Figure 1, Node 1 (150) includes a host system with CPU 1 and
`CPU 2 (100) connected via Peripheral Component Interconnect (PCI)
`bus 116.5 to host bus adapter (“HBA”) 117. Id. at 6:34–47. Host bus
`adapter 117 includes cache memory 117.2 and local memory 116 and is
`connected to local drives 118 via Small Computer System Interface (SCSI)
`or fiber channel arbitrated loop (“FCAL”) interfaces 117.8 and 117.9. Id.
`at 7:9–15, 7:51–56. The host may process I/O requests locally by accessing
`HBA 117 via PCI bus 116.5. Id. at 4:51–57, 6:34–47. “Although PCI is the
`preferred I/O bus standard, one skilled in the art will recognize other I/O bus
`standards are operable within the present invention, such as EISA,
`MicroChannel, etc.” Id. at 6:61–64.
`Front-end interface 102 represents a PCI-to-PCI Bus bridge that
`connects various peripheral I/O devices via PCI bus 117.6, e.g., local drives
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`118 and Fibre Channel Chip 120, to centralized system PCI bus 116.5. Id. at
`7:1–4. “To improve I/O performance, CPU 117.1 temporarily caches disk
`data in cache memory 117.2 that is frequently accessed. Later, the CPU
`117.1 stores the data permanently in the slower disk drive devices 118.” Id.
`at 7:24–27. Figure 1 illustrates that one HBA services I/O requests from
`CPU 1 and CPU 2 100. “One skilled in the art, however, will recognize the
`load sharing benefits of allowing a plurality of HBAs to service the local and
`remote I/O requests of CPU 1 and CPU 2 100.” Id. at 7:35–39.
`
`2. Nakayama (Ex. 1007)
`Nakayama is directed to cached data storage systems and describes an
`apparatus and method in which host computers provide input to a cache
`memory or a storage drive. Ex. 1007, Abstr., 4:52–65.
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`Figure 3 of Nakayama is reproduced below.
`
`
`“FIG. 3 is a schematic block diagram showing the configuration of
`an[ ] embodiment of a disk subsystem of the present invention.” Ex. 1007,
`3:13–15. Figure 3 shows host disk control 302, containing cache memory
`309, connected via channel 301 to host computer 300 on the host side. Disk
`control 302 is also connected to host computer 303 via a SCSI interface, and
`disk control 302 is connected to magnetic storage medium drives 315 and
`316 to perform read/write operations for data on drives 315/316 in response
`to requests from host computers 300 and 303. Id. at 4:39–51.
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`3. Gulick (Ex. 1008)
`Gulick describes a system that includes a dedicated multimedia engine
`and dedicated multimedia memory coupled directly to a main memory. A
`data path to the main memory and multimedia memory is provided, as is a
`separate command path to the multimedia engine. Ex. 1008, Abstr.
`Figure 1 of Gulick is reproduced below.
`
`
`
`Figure 1 “is a block diagram of a computer system including a
`separate command path to a multimedia engine.” Id. at 3:45–47. Figure 1
`depicts central processing unit (CPU) 102 coupled through CPU local bus
`104 to a host/PCI/cache bridge or chipset 106. Id. at 4:61–65.
`Gulick describes that, in an embodiment, PCI local bus 120 is used,
`but that other local buses of known types may be used. Id. at 5:39–41. In
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`addition, Gulick discloses that a number of different types of devices may be
`connected to PCI bus 120. Id. at 5:41–43. In Figure 1, hard disk 122 and
`network interface controller 124 are coupled to PCI bus 120, and SCSI
`adapter 126 may also be coupled to PCI bus 120 to connect to various SCSI
`devices, such as a CD-ROM drive and a tape drive (not shown). Id. at
`5:44–51.
`
`4. Berman (Ex. 1009)
`Berman describes “Methods and apparatus for Fiber Channel
`interconnection . . . provided between a plurality of private loop devices
`through a Fiber Channel private loop device interconnect system.”
`Ex. 1009, Abstr. Figure 14 of Berman is reproduced below.
`
`
`Berman – Figure 14
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`Figure 14 of Berman “is a block diagram of a Fibre Channel Fabric.”
`Id. at 6:36. In the block diagram of Figure 14, fabric 30 is composed of
`fabric control module (FCM) 454, fabric router 452, multiple port control
`modules 451, 474, and 475, switch core module 453 and, optionally, one or
`more bridge router (brouter) modules 455. The Fabric Control module
`controls and configures the rest of the fabric but is said to not usually be
`involved in the normal routing of frames. Id. at 11:30–36. “The interface to
`the brouter module 455 allows the FCM to communicate through legacy
`networks such as ethernet and fast ethernet, depending on the brouter
`module.” Id. at 12:8–11.
`Berman further describes:
`Any type of private loop device, consistent with the
`apparatus and methods stated herein, may be utilized in
`conjunction with this system. Examples of private loop devices
`include storage devices, such as tape drives, JBODs and RAID
`subsystems, host systems, and other connections within a
`system, such as bridges, particularly SCSI to Fibre Channel
`bridges, routers,