`
`PAUL D. FRANZON
`
`Cirrus Logic Distinguished Professor
`Director of Graduate Programs
`Department of Electrical and Computer Engineering
`
`I.
`
`INTRODUCTION
`
`B. BRIEF RESUME
`
`1. Education
`
`• Doctor of Philosophy, Electrical and Electronic Engineering 1989, University of
`Adelaide, Australia . Advisor: Kamran Eshraghian.
`• Bachelor of Engineering with First Class Honours, Electrical and Electronic En-
`gineering: 1984, University of Adelaide, Australia
`• Bachelor of Science, Physics and Mathematics: 1983, University of Adelaide,
`Australia.
`
`2. Professional Experience
`
`•
`
`• Assistant Professor, Associate Professor, Professor, and Distinguished Professor
`North Carolina State University, Department of Electrical and
`Computer Engineering, Raleigh, North Carolina, January 1989 – present
`• Technical Director, Rambus (part time/consulting), 2009-11, Chapel Hill, NC.
`• Cofounder, LightSpin Technologies Inc., 2001-. Vice-President of Engineering,
`2001-2002, Raleigh NC.
`• PhD Candidate, University of Adelaide, Department of Electrical and Electronic
`Engineering, Adelaide, South Australia, Australia, April 1987 - December 1988.
`• Director and Co-Founder, Network Communications Pty. Ltd., Adelaide, South
`Australia, Australia, April 1987 - April 1989.
`• Consultant, AT&T Bell Laboratories, Holmdel NJ, January 1986 - April 1987.
`• PhD Candidate, University of Adelaide, Department of Electrical and Electronic
`Engineering, Adelaide, South Australia, Australia, August 1984-December 1985.
`• Engineer, Defence Science and Technology Organization, Salisbury, South Aus-
` tralia, Australia, January 1984--July 1984
`Intern, Defense Science and Technology Organization, Salisbury, South Austra-
`lia, Australia, December 1982--March 1983.
`Intern, Telecom Australia, Adelaide, South Australia, Australia, December 1981-
`March 1982.
`Infantry Soldier and Officer, (Ranks held: Private - Captain), Royal Australian
`Infantry Corps, Australian Army Reserve, December 1979 - December 1991.
`
`•
`
`•
`
`3. Scholarly and Creative activities
`
`1
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`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 1 of 72
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`
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`Paul D. Franzon
`
`
`Number
`
`
`
`Type
`-------------------------------------------------------
`Books
`
`
`
`4
`Solution Manuals
`
`
`1
`Edited Book Chapter
`
`19
`Refereed Journal article
`
`99
`Conference Paper (refereed)
`237
`Patents granted
`
`
`10
`
`4. Membership in professional organizations
`
`Fellow, Institute of Electrical and Electronic Engineers
`Member, IMAPS
`Member, SPIE
`Member, Association of Computing Machinery
`
`5. Scholarly and professional honors
`
`
`• Alumni Distinguished Graduate Professor Award, 2021
`• NCSU Innovator of the Year Award, 2015
`• College of Engineering Board of Governor’s Award, 2014
`• NRL Alan Berman Research Publication Award, 2008
`• Babbage Award, Synopsys, 2008
`• Fellow of the IEEE, 2006
`• Alcoa Research Award, 2005
`• ECE Graduate Teacher of the year award, 2007
`• ECE Most Helpful Teacher of the year award, 2007
`• ECE Teacher of the year award, 2006
`• ECE Graduate Advisor of the year award, 2006
`• Alumni Undergraduate Distinguished Professor, 2003-2005.
`• Graduate teacher of the year, ECE department, 2005
`• NSW Australia Expatriate Scientist Award, 2003
`• Selected to the NCSU Academy of Outstanding Teachers, 2001
`• First round prize winner, SRC copper challenge, 2000.
`• Teacher of the Year Award, presented by the IEEE Student Branch, 1997
`• National Science Foundation Young Investigator's Award, 1993.
`• 13 prizes while a student at the University of Adelaide
`• Australia Defense Medal, 2006
`
`
`6. Professional service on campus
`
`
`• Member, STRAG 2003-2005
`•
`Instructor, PE preparation course 1995-2000
`
`
`7. Professional service off campus
`
`
`
`2
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`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 2 of 72
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`
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`Paul D. Franzon
`
`• Consultant to Perkins Cole, 2022, patent issues
`• Consultant to Micross, 2022, 3DIC processes
`• Consultant to DLA Piper, 2022, patent issues
`• Consultant to Wolf Greenfield, 2022, patent issues
`• Consultant to Lee Hayes, 2020-, patent issues
`• Consultant to Fish and Richardson, 2020-22, patent issues
`• Consultant to Sofwerx, 2018, Machine learning for UAVs.
`• Consultant to Kirkland, 2019- patent issues
`• Consultant to Finnigan, 2016-, patent issues
`• Consultant to Wilmar, 2017-, patent issues
`• Consultant to Unified Patents, 2017- , patent issues
`• Consultant to DARPA, Thermal issues, 2012-2016
`• Consultant to Paul Hastings, OMM, KL Gates, Samsung, Micron and SK Hynix,
`2015-,2017 Patent issues
`• Consultant to LDKM and AVT, Patent issues, 2013-2015
`• Consultant to Skiermont Puckett and Spherix, Patent issues, 2014-2016
`• Consultant to Haliburton, 2014
`• Consultant to DARPA, Exascale Computing Study, 2007-9.
`• Consultant to Rambus, Semiconductors, 2009-12
`• Consultant to Techsearch, 2008.
`• Consultant, NTU, 2004-9. ASIC Design.
`• Consultant to Tessera, 2009. 3DIC advising.
`• Consultant, Irvine Sensors, 2006. Secure chip design.
`• Consultant, Cisco Systems, 2006, Signal Integrity.
`• Consultant, Talon Logic, 2005. Secure system Design.
`• Consultant to O'Malveny and Meyers, 2000-2002, Patent issues.
`• Consultant to Venture 2000, 2000, Due Diligance.
`• Consultant to CAPPS, 1999-2000, IP Development.
`• Consultant to Sofrent, 1999-2000, IP Development.
`• Consultant to Ericsson, 1997, Synthesis Methodology.
`• Consultant to Cadence, 1996. Evaluated possible company acquisition.
`• Consultant to Polychip, 1994 - 2000. Circuit Design.
`• Consultant to Square-D, 1996. Interconnect Design.
`• Consultant to Mentor Graphics, 1995, 1996. Technical advisory board.
`• Consultant to Cadence Design Systems, 1992, 1996. Technical advisory board.
`• Consultant to DCT, 1995-1996. ASIC Design.
`• Consultant to Techsearch International, 1989-1991. Report Preparation.
`• Consultant to BNR, HP, Sun. 1992-4. Interconnect Design.
`• Consultant to MCNC, 1989. CAD
`
`
`C. CANDIDATES STATEMENT
`
`As Director of Graduate Programs in ECE (starting in 2016), I have introduced the
`following innovations:
`
`
`
`3
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`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 3 of 72
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`
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`Paul D. Franzon
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`1. I led the faculty in agreeing to a reduced course load for our PhD students (from 42
`CH to 30 and simplified rules). This has been very popular with PhD students.
`(2016)
`2. I introduced a PhD Visit Day and held one every year. The ones held in 2017 and
`2018 each involved over 40 visitors and about the same number of alumni, faculty
`and current students. Over 90% of students surveyed stated they are more likely to
`come as a result of the visit day.
`3. I reorganized an office into 3 staff and 1 EPA position. The 3 staff consist of two
`GSSCs (one for admissions and one for current students), and one assistant for
`both. The EPA position is our new Director of Graduate Employment Services.
`Her role is to help students get jobs and internships.
`4. I introduced a series of panels aimed at PhD students. Panels held so far include
`the following
`a. Becoming faculty (2017);
`b. Becoming an industry researcher (2018);
`c. Writing proposals (2019).
`5. I held two classes on advanced study skills aimed at MS students (2018).
`6. I took over leadership of the Graduate Admissions Committee. We reorganized
`the PhD recruiting flow, starting from information disseminated by the Admissions
`GSSC through to TA allocations. I reorganized the MS admissions flow, starting
`from data prep by the Admissions GSSC to using statistical models to assist (not
`make) the decision making process.
`7. I changed the PhD application process to encourage students to answer questions
`specifical to what they can draw upon to make good PhD students.
`8. I redid our marketing materials and started marketing at other campuses in the
`UNC system.
`9. I conducted surveys of current students, and alumni to determine gaps in our
`program. As a result, I introduced additional courses in verification with UVM,
`operating systems and hardware security. In addition the Neural Networks course
`was refocused and a concentration on Machine Learning introduced.
`10. Introduced Graduate Certificates in 5G, ASIC Design and Verification, CPE and
`EE.
`
`
`As Site Director for the Center for Advanced Electronics through Machine Learning
`(CAEML) I lead this Center for NCSU. I am one of the founding directors for this Center,
`which is run jointly with UIUC and Ga Tech. I am responsible for member company
`recruiting, faculty recruiting and running the biannual meetings as held every 18 months
`on campus here. I have particularly focused on drawing in other NCSU faculty to the
`Center. Two new faculty have joined since the center started.
`
`
`
`
`
`4
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`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 4 of 72
`
`
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`Paul D. Franzon
`
`II. TEACHING AND MENTORING OF UNDERGRADUATE AND
`GRADUATE STUDENTS
`
`A. TEACHING EFFECTIVENESS
`
`1. Courses Taught
`
`
`Since becoming DGP, I am not required to teach, though I did teach ECE 464/564 in
`2016, 17 and 19. I continue to remain involved in ECE 464/564 and ECE 733 though by
`giving guest and substitute lectures, advising on course policies, content and suggesting
`suitable class projects.
`
`Course
`
`When
`
`Enrollment
`
`ECE 464 ASIC Design
`ECE 564 ASIC Design
`ECE 564-601
`ECE 564-640
`ECE 564-651
`ECE 464 ASIC Design
`ECE 564 ASIC Design
`ECE 564-601
`ECE 564-651
`ECE 464-001
`ECE 564-001
`ECE 564-601
`ECE 464-001
`ECE 564-001
`ECE 564-601
`ECE 464-001
`ECE 520-001
`ECE 520-601
`ECE 520-651
`ECE 464-001
`ECE 520-001
`ECE 520-601
`ECE 520-603
`ECE 520-651
`ECE 733-001
`ECE 464-002
`ECE 520-002
`ECE 520-601
`ECE 634-602 ASIC Design
`ECE 634-602 ASIC Design
`ECE 520-601
`
`41
`F 21
`157
`F 21
`7
`F 21
`11
`F 21
`9
`Sum 21
`39
`F 20
`54
`F 20
`10
`F 20
`Sum 20 16
`F 19
`F 19
`F 19
`F 17
`F 17
`F 17
`F 16
`F 16
`F 16
`Su 16
`S 15
`S 15
`S 15
`S 15
`SuI 15
`S 15
`F 15
`F 15
`F 15
`F 2014
`F 2014
`S1 2014
`
`39
`139
`6
`36
`148
`7
`29
`121
`9
`16
`19
`119
`11
`3
`16
`50
`21
`129
`7
`6
`2
`9
`
`
`
`5
`
`Instructor
`effectiveness
`na
`na
`5.0/4.3
`4.8
`4.3/3.8
`
`
`Course
`excellence
`na
`na
`4.7/4.1
`4.3
`4.2/3.8
`
`
`4.2
`4.3
`
`
`
`4.7
`4.7
`5.0
`4.4
`4.4
`
`4.8
`4.8
`4.4
`4.6
`4.3
`4.3
`4.8
`
`4.6
`4.5
`4.6
`4.6
`5.0
`
`
`
`
`4.6
`4.0
`
`
`
`4.5
`4.5
`5.0
`4.4
`4.4
`
`4.6
`4.8
`4.2
`4.6
`4.3
`4.3
`5.0
`
`4.6
`4.3
`4.5
`4.5
`5.0
`
`
`
`
`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 5 of 72
`
`
`
`ECE 464-001
`ECE 520-001
`ECE 520-601
`ECE 733-001
`ECE 520-601
`ECE 520-651 ASIC Design
`ECE 464-051 ASIC Design
`ASIC Design OOC
`ECE 733 Digital Electronics
`ECE 520-001 ASIC Design
`ECE 464 ASIC Design
`
`ECE 520-651 ASIC Design
`
`ECE 733 Digital Electronics
`ECE 520-601
`ECE 520-001 ASIC Design
`ECE 464 ASIC Design
`ECE 406 Des. Complex
`Systems
`ECE 520-651 ASIC Design
`
`ECE 733 Digital Electronics
`ECE 520-601
`ECE 520-001 ASIC Design
`ECE 464 ASIC Design
`ECE 406 Des Complex
`Systems
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 520 ASIC Design 620
`ECE 464 ASIC Design
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 733
`
`S 2014
`S 2014
`S 2014
`S 2014
`F 2013
`SII ‘13
`SII ‘13
`SII ‘13
`S 2013
`S 2013
`S 2013
`
`Sum
`‘12
`S 2012
`S 2012
`S 2012
`S 2012
`F 2011
`
`Sum
`‘11
`S 2011
`S 2011
`S 2011
`S 2011
`F 2010
`
`S 2010
`S 2010
`S 2010
`S 2010
`S 2010
`S 2009
`S 2009
`S 2009
`S 2009
`S 2009
`S 2009
`S 2008
`S 2008
`S 2008
`S 2008
`S 2008
`S 2007
`
`10
`111
`9
`49
`2
`7
`6
`635
`62
`136
`(with
`above)
`18
`
`52
`12
`116
`14
`58
`
`13
`
`18
`12
`75
`25
`75
`
`36
`3
`57
`17
`9
`57
`7
`128
`17
`1
`16
`67
`2
`101
`15
`27
`58
`
`
`
`6
`
`Paul D. Franzon
`
`4.5
`4.5
`4.5
`4.4
`
`4.3
`4.5
`
`4.3
`4.5
`4.3
`
`
`
`4.2
`4.2
`4.3
`4.3
`4.6
`
`4.2
`
`4.5
`4.2
`4.5
`4.5
`4.6
`
`4.2
`5.0
`4.4
`4.4
`4.4
`4.5
`4.2
`4.4
`4.20
`
`4.4
`4.64
`
`4.59
`4.20
`4.59
`4.46
`
`4.5
`4.5
`4.5
`4.7
`
`4.3
`4.5
`
`4.5
`4.6
`4.3
`
`
`
`4.2
`4.3
`4.3
`4.3
`4.6
`
`4.2
`
`4.5
`4.3
`4.5
`4.5
`4.6
`
`4.3
`5.0
`4.3
`4.2
`4.3
`4.6
`4.4
`4.6
`4.5
`
`4.6
`4.64
`
`4.76
`4.5
`4.76
`4.64
`
`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 6 of 72
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`
`
`129
`6
`17
`20
`43
`65
`8
`17
`30
`5
`44
`34
`2
`15
`13
`45
`76
`17
`69
`84
`81
`30
`63
`167
`239
`
`39
`
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 745 ASIC Verification
`ECE 733 Digital Circuits 001
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design 001
`ECE 733 Digital Circuits 001
`ECE 733 Digital Circuits 601
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 002
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design 001
`ECE 464 ASIC Design 002
`ECE 733 Digital circuits
`ECE 520 ASIC Design
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 733 Digital Circuits
`ECE 520 ASIC Design
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 406 Design Complex DS
`ECE 520 ASIC Design
`ECE 520 ASIC Design 601
`ECE 464 ASIC Design
`ECE 406 Des. Complex Dig
`Sys
`ECE 704 Design For Test
`ECE 520 ASIC Design 001
`ECE 520 ASIC Design 002
`ECE 520 ASIC Design 601
`ECE 492B ASIC Design
`ECE 342 Des. Complex Dig
`Sys
`ECE 520 ASIC Design 005
`ECE 520 ASIC Design 006
`ECE 342 Des. Complex Dig
`Sys
`ECE 520 ASIC Design
`ECE 492B ASIC Design
`ECE 342 Des. Complex Dig
`Sys
`ECE 520 ASIC Design
`
`S 2007
`S 2007
`S 2007
`F 2006
`S 2006
`S 2006
`S 2006
`S 2006
`S 2005
`S 2005
`S 2005
`S 2005
`S 2005
`S 2005
`S 2005
`S 2004
`S 2004
`S 2004
`S 2004
`S 2003
`S 2003
`S 2003
`S 2003
`F 2002
`S 2002
`S 2002
`S 2002
`F 2000
`
`F 2000
`S 2000
`S 2000
`S 2000
`S 2000
`F 1999
`
`S 1999
`S 1999
`F 1998
`
`S 1998
`S 1998
`F 1997
`
`S 1997
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`7
`
`Paul D. Franzon
`
`
`
`
`
`4.68
`
`4.68
`4.6
`4.6
`
`
`4.1
`4.6
`
`4.3
`4.5
`
`4.1
`4.1
`4.2 (3.9)
`4.3 (3.9)
`
`4.0 (3.9)
`4.2 (3.8)
`3.9 (3.8)
`
`3.5 (3.8)
`3.8 (3.9)
`4.2 (3.9)
`
`3.6 (3.9)
`4.5 (3.7)
`
`4 (3.8)
`4.4 (3.9)
`4.3 (3.9)
`
`4.3 (3.9)
`4 (3.9)
`
`4.5 (4.0)
`4.3 (4.0)
`4.1 (3.9)
`
`4.4 (3.9)
`4.8 (4.1)
`4.4 (4.0)
`
`
`
`
`
`4.75
`
`4.75
`
`4.5
`
`
`4.4
`4.5
`
`4.6
`4.6
`
`4.9
`4.9
`4.2 (4.1)
`4.4 (4.1)
`
`4.5 (4.1)
`4.3 (4.0)
`4.2 (4.0)
`
`3.9 (4.0)
`4.2 (4.1)
`4.4 (4.1)
`
`4.1 (4.1)
`4.7 (4.0)
`
`4.6 (4.0)
`4.5 (4.1)
`4.6 (4.1)
`
`4.5 (4.1)
`4.4 (4.1)
`
`4.6 (4.2)
`4.5 (4.2)
`4.3 (4.1)
`
`4.6 (4.1)
`4.7 (4.1)
`4.6 (4.0)
`
`4.7 (4.1)
`
`4.7 (3.9)
`
`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 7 of 72
`
`
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`Paul D. Franzon
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`ECE 492B ASIC Design
`AVERAGE
`
`S 1997
`
`
`
`
`
`4.7 (4.1)
`
`
`4.4 (3.9)
`
`
` •
`
` ECE 342 Design of Complex Digital Systems, Fall 1996, Overall Rating: 4.6/5.0.
`• ECE 592B ASIC Design, Spring 1996, Overall Rating: 4.75/5.0. (With Dr. Liu.)
`• ECE 492B ASIC Design, Spring 1996, Overall Rating: 4.00/5.0. (With Dr. Liu.)
`• ECE 544, Design of Electronic Packaging and Interconnects, Spring 1999, Overall
`Rating : 4.60/5.0.
`• ECE 520, Fundamentals of Logic Systems, Fall 1995, Overall Rating: 4.50/5.0.
`• ECE 218, Computer Organization and Microprocessors, Both Sections, Spring,
`1995: Section 001: 4.45/5.0; Section 002: 4.62/5.0.
`• ECE 592V, VLSI Microprocessor Project, Spring 1995. (13 students but not rated).
`• ECE 681/693A, Computer Engineering Seminar. Spring 1996 and Fall 1996.
`• ECE 521 Computer Design and Technology, Fall 1994, Overall Rating: 4.24/5.0.
`• ECE 691F, High Speed VLSI, Fall 1994, Overall Rating: 4.45/5.0.
`• ECE 691P, Superscalar Processor Design, Spring 1994, Overall Rating: 4.67/5.0.
`• ECE 591F, Design of Electronic Packaging and Interconnects, Spring 1994, Overall
`Rating: 4.60/5.0.
`
`
`B. INSTRUCTIONAL DEVELOPMENT
`
`
`
`1. NSF-funded CISE Infrastructure effort, “Experimental High Performance
`Computing and Communications Systems''. (Total: $1,338,283 including $503,046 in
`matching.) Approximately $283,000 of this funding went towards outfitting the ECE
`Design Center.
`
`2. CAD Tools. Modern design is done with sosphisticated Computer – Aided Design
`Tools, not with pencil and paper. I have spent considerable effort bringing such tools
`into the Unity environment, gaining the `corporate knowledge' about how to use these
`tools effectively and obtaining additional computers for use with these tools. Students tell
`me that knowledge of these tools is highly regarded by potential employers. In fact one
`student stated that `Dr. Franzon teaches courses that gets jobs'. In addition , in 1999, we
`won the Cadence University Alliance Best Web site Awards. Through my funded
`research efforts and Corporate Donations introduced the following Computer Aided
`Design Tools into the curricula:
`• Cadence Design Systems. A complete suite of over 4 GB of executables
`that facilitate chip, board and system design, with a retail value of over
`$100,000,000. Cadence donates these tools because of the widespread
`recognition of our contributions to CAD. (i.e. It waives the $5,000 fee.)
`• Synopsys. The industry leading chip (ASIC) synthesis tool,with a retail
`value of over $7,000,000.
`In 2008, NCSU won the “Babbage Award” from Sun and Synopsys, in
`recognition of our contributions towards lab infrastructure. The award comes
`in the form of $15,000 of computers.
`
`•
`
`
`
`8
`
`Google Exhibit 1005
`Google v. LS Cloud Storage Technologies
`IPR2023-00120, Page 8 of 72
`
`
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`Paul D. Franzon
`
`•
`
`• Mentor. We integrate some mentor graphics tools with the other tools above.
`The tools have a retail value of over $5,000,000. Mentor donates these tools
`because of the widespread recognition of our contributions to CAD.
` Mentor donates $30,000 annually to the University to assist in CAD
`infrastructure development.
`As well as obtaining these tools, my group has spent considerable effort making these tools
`useful to us by writing integration scripts and generating `know-how'. Much of this `know-
`how' has been published on the Web and in our own lockers. Most of this learning was
`conducted driven by research needs and serves as an excellent example of the integration
`of research and teaching. This work is ongoing. For example, over 2000 organizations
`world-wide, use our “Physical Design Kit”..
`
`3. ECE 745. ASIC Verification. I introduced this course in 2007, though it was taught by
`Meeta Yadav.
`
` 4. ECE 342, Design of Complex Digital System, Fall 1996:
`• Completely redesigned and updated course to reflect modern design practices,
`and use of modern Hardware Description Languages and Design Tools.
`• Completed a new laboratory course ECE 342L for use with this course.
`
` 5. ECE 520 ASIC Design (formerly `Fundamentals of Logic Systems'), Spring 1997:
`• Based on my teaching of ECE592B in Spring 1995, this course has been
`completely updated to reflect modern design practices, modern tools, and
`emphasize an understanding of algorithms used in modern tools. (`ASIC' stands
`for `Application Specific Integrated Circuit'. For example the chips in a satellite
`dish receiver are ASICs. ASIC engineering is the fastest growing area of ECE
`today.)
`• Once the course action forms are approved, this course will be taught concurr-
`ently with ECE 420 ASIC Design.
`
`
`
`
`
`
`
`6. ECE 544, Design of Electronic Packaging and Interconnects, Spring 1995. New c-
`ourse emphasizing `transmission line effects' in electronic packages and how to design
``deep sub-micron interconnect'. I receive tremendous demand from ind-
` ustry
`for graduates from this course.
`
`7. ECE 691/693A, Computer Engineering Graduate Seminar
`• Created new seminar course (with Dr. Tom Conte) for computer engineering
`students.
`• Recruited and scheduled weekly speakers.
`
`
`8. ECE CAD Lab. $75,000. Provost Office, 1995.
`
`C. MENTORING ACTIVITIES
`
`UNDERGRADUATE STUDENT SUPERVISIOR
`1. 2012. Spring advisor to two undergraduates.
`
`
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`2. 2010. Summer REU supervisor to three Undergraduates
`3. 2009. Summer REU supervisor to one Undergraduate.
`4. 2009. Supervised Senior Design Team
`5. 2008. Summer REU supervisor to two Undergraduates.
`6. 2005 Andrew Pita, SRC Undergraduate Research Fellowship
`7. 1999 Ecoh Oh, NSF Undergraduate Research Award
`8. 1999 Ben Hughes, NSF Undergraduate Research Award
`9. 1993- Numerous Senior Design projects
`
`
`GRADUATE STUDENT SUPERVISION
`
`GRADUATE COMMITTEES
`
`Currently member of several PhD and MS committees.
`
`GRADUATE COMMITTEES
`
`For a list of graduate committees I chair, see below. I am on numerous committees as a
`member, but I do not track the numbers.
`
`D. MASTER’S AND DOCTORAL THESES DIRECTED AND BEING
`DIRECTED
`
`
`Masters and Doctoral Theses under direction
`
`
`
`Student’s Name
`
`Ph.D.
`MS
`
`Chair/
`Co-
`chair
`x
`x
`X
`X
`X
`X
`X
`X
`
`PhD
`Han Pan
`PhD
`Ahmad Benaki
`PhD
`George Li
`PhD
`Wen Yuejing
`PhD
`Josh Stevens
`PhD
`Archit Gaijar
`PhD
`Priyank Kashyap
`PhD
`Batool Khader
`I do not track memberhips.
`
`
`Doctoral Theses Directed
`
`1. Luis Francisco, “Machine Learning for Design Rule Checking, Multilayer CMP
`Hotspot Detection, using Transfer Learning and Synthetic Training”, May 202, co-
`Chair..
`2. Billy Huggins, “An Evolutionary Approach to Producing Optimal Electronic Design
`Automation Tool Settings”, May 2021, co-chair.
`
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`3. Theodros Nigussie, “Design obfuscation throught smart partitioning and 3D
`integration,”, Mar. 2020, chair.
`4. Kirti Bhanashuli, “On implementing power-efficient and scalable short-range RF-
`power radios using RF-only architectures,” Jan., 2020, chair.
`5. Yi Wang, “Solving Inverse Problem through optimization and its application to
`Analog/RF Design,” March 2020, chair.
`6. Bowen Li, “High-speed receiver behavioral modeling using machine learning,”, Jan.
`2020, chair.
`7. Sumon Dey, “Design of a scalable, confirugate and cluster-based hierarchical
`hardware accelerator for a cortically inspired algorithm and recurrent neural
`networks,” August, 2019, chair.
`8. Weifu Li. Design of Hardware Accelerators for Hierarchical Temporal Memory and
`Convolutional Neural Networks”, August 2019, chair.
`9. Nazia Zannat, “Design of contactless connectors for simultaneous power and data
`transfer,” May, 2019, chair.
`10. Zhao Wang, “Efficient linear matrix solver and its hardware implementations
`dedicated to faster than real time dynamic simulation of large scale power systems,”
`September, 2018, chair.
`11. Lee Baker, “Design of a 3DIC system to aid in the acceleration of embedded system
`that employ multiple instances of disparate artificial neural networks,” March 2018,
`chair.
`12. Jong Beom Park, “A circuit level three-dimensional DRAM area timing and energy
`model,” March 2018, co-chair.
`13. Josh Schabel, “Design of an application specific instruction set processor for sparse
`neural networks,”, October 2017, chair.
`14. Weiyi Qi, “IC Design Analysis, Optimization and Reuse via Machine Learning,
`August, 2017, Chair.
`15. Wenxu Zhao, “RF-only Logic Enbabled RFID Transponder Size Reduction,”,
`December 2016. Chair.
`16. Marcus Tshibangu, “Study and analysis of Energy Efficient DRAM Cache with
`unconventional row buffer size,” August 2016. Chair.
`17. Randy Widialaksono, “Three Dimensional Integration of Hterogeneous Multi-Core
`Processors,” June, 2016. Co-chair.
`18. Zhenquian Zhang, “Design of On-chip bus of Heterogeneous 3DIC Micro-
`processors,” May 2016, Chair.
`19. Sarkar, Biplap, “Atomic Layer Deposition Techniques for Novel Memory
`Applications,” August 2015. Cochair
`20. Winick, David, “Electroactive Polymer Refreshable Braille Display, December
`2015 (Posthumous).
`21. Gary Charles, “Design, Model and Analysis of TSV-based On-Chip PDN Interconnects
`for 3-D Integrated Circuits. “, March 2015.
`22. Zhao Yan, “S-Parameter Based Binary Multimode
`Methodology and Implementation,” December, 2014 .
`23. W.S. Pitts, “High quality CMOS Integratable Varactors,” March 2014.
`24. Peter Gadfort, “Packaging and Integration of Three Dimensional Microsensors,”
`December, 2013.
`25. Evan Erickson, “Multi-Gbps Inductively Coupled Connectors,” December, 2013.
`
`Interconnect Design
`
`
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`26. Akalu Lentiro, “Low-Density, Ultra-Low Power and Smart Radio Frequency
`Telemetry Sensor,” October, 2013.
`27. Shivam Priyadarshi, “System and Gate Level Dynamic Electrothermal Simulation
`of Three Dimensional Integrated Circuits,” June, 2013.
`28. Eric Wyers, “Direct Search Calibration Algorithms for Digitally Reconfigurable
`Radio Frequency Integrated Circuits,” March 2013.
`29. Ojas Ashok BOpat, “A Generic Scalable Architecture For a Large Acoustic Model
`and Large Vocabularly Speech Recognition Accelerator,” October, 2012.
`30. Won Hao Choi, “System Level Power Prediction Methodology for Mobile 3-D
`Graphic Engines,” May 2012.
`31. Hsuan-Jung Su, “Continuous-Time Fractionally Spaced Equalization and Its
`Application in Capacitively Coupled Chip-To-Chip Interconnect,” May, 2012.
`32. Matthew Hamlett, “A Novel Approach to IP Protection Using Automated Hardware
`Techniques to Secure a Design,” March 2012.
`33. Mustafa Berke Yelten, “Variability and Reliability in Nanoscale Circuits:
`Simulation, Desgin, Monitoring and Characterization,” January, 2012.
`34. Hoon Seok Kim, “Advanced Multi Mode Interconnect,” December, 2011.
`35. Xiangzhong Xue, “Electronic System Optimization Via Convex Programming,”
`December, 2011.
`36. Tsing Zhu, A Surrogae Model-based Framework for Design and Macromodeling of
`Self-calibrated Analog Circuits,” October, 2011.
`37. Chanyoun Won, “Multimode Interconnect for High-Density Links: Implementation,
`Design Methodology and New Crosstalk Cencallation Scheme,” July 2011
`38. Thor Thorolfsson, “Three Dimensional Integration of Synthetic Aperture Radar
`Processors,” April 2011
`39. Daniel Schinke, “Computing with Novel Floating Gate Devices,” April 2011
`40. Yongjin Choi, “Design of Multimodel Signaling Transceiver for High-Density and
`High-Speed Links,” May 2010.
`41. Eun Chu Julie Oh, Ph.D. Dissertation, “Design and Applications of Three-
`Dimensional Circuits”, December, 2009.
`42. Karthik Chandrashekhar, Ph.D. Dissertation, “Inductively Coupled Connectors,”
`December, 2008
`43. Dhruba Chandra, Ph.D. Dissertation, Speech Recognition CoProccessor, December,
`2007.
`44. Meeta Yadav, “Hardware Architecture of behavior Modeling Coprocessor for
`Network Intrusion Detection,” Ph.D. Dissertation, March, 2007.
`45. Ullas Pazhayaveetil, “Hardware Implementation of a Low Power Speech
`Recognition System,” Ph.D. Dissertation, February, 2007.
`46. Jian Xu, “AC Coupled Interconnect for Inter-Chip Communications,” Ph.D.
`Dissertation, December, 2006.
`47. Ambrish Varma, “Improved behavioral modeling based on Input Output Buffer
`Information Specification,” Ph.D. Dissertation, NCSU, October, 2006.
`48. Sachin Sonkusale, “Planar edge defined alternate layer process (PEDAL) – an
`unconventional technique for the fabrication of wafer scale sub-25 nm nanowires
`and nanowire template,” PhD, October, 2006.
`
`
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`49. Liang Zhang, “Driver Pre-emphasis Signaling for on-chip global interconnects,”
`Ph.D. Dissertation, September, 2006.
`50. Monther Al Dwairi, “Hardware Efficient Pattern Matching Algorithms and
`Architectures for Fast Intrusion Detection,” Ph.D., November, 2006.
`51. John Damiano, “Active body bias for low-power silicon-on-insulator design,”
`Ph.D., March 2006.
`52. Neil DiSpigna, “Electronic Devices and Interface Strategies for Nanotechnology,”
`Ph.D., April 2006.
`53. Christian Amsinck, “Molecular Electronic Memories,” Ph.D., March 2006.
`54. Lei Luo, “Capacitively Coupled Chip to Chip Interconnect Design, Ph.D.,
`December, 2005.
`55. Leon Zhang, “Driver pre-emphasis signaling for on-chip global interconnects,”
`Ph.D., December, 2005.
`56. Steve Lipa, “Phase Noise Analysis of Rotary Oscillators,” Ph.D. May 24, 2005
`57. David Nackashi, Circuit and Integration Technologies for Molecular Electronics,
`Ph.D. 2004
`58. Stephen Mick, AC Coupled Interconnect, Ph.D. 200
`59. John Wilson, Linearly Tunable RF MEMS Capacitors Implemented Using an
`Integrated Removable Self-Masking Technique, Ph.D. 2004
`60. Andrew Stanaski, Sensor Circuits for Flip Chip Debug, Ph.D. 2004
`61. Pronita Mehrotra, High Performance Hardware Memory Algorithms, Ph.D. 2003
`62. Bruce Duewer, MEMS Switch Fabric, Ph.D.
`63. Toby Schaffer, Chip-package Codesign, Ph.D.
`64. Mouna Nakkar, Dynamically Programmable Cache, Ph.D.
`65. Mir Azam, Custom CMOS Design and Architecture for Low-Power High-
`Performance Circuits, PhD.
`66. Debu Ghosh (co-chair), Synthesis of Benchmarking Expiriments, Ph.D.
`67. Chris Harvatis, Performance Driven Partitioning for MCMs, PhD.
`68. Slobodan Simovich, Computer-Aided Analysis of Interconnect,PhD.
`69. Scott Washabaugh, Low energy FSM Design, PhD.
`70. Sharad Mehrotra, Automated Synthesis of High Speed Digital Circuits and Package-
`Level Interconnect, PhD.
`71. Todd Cook, Instruction Set Architecture Specification, PhD.
`72. Robert Evans, Energy Consumption for Modeling and Optimization of SRAMs,
`PhD.
`
`Masters Theses directed
`
`1. Abhishek Bhattacharya, “Design and Power Optimization of a16 nm Dual Floating
`Gate FET Memory Array and Peripheral Circuits,” October, 2013.
`2. Joshua Schabel, “An Analysis of Subthreshold SRAM Bitcells for Operation in Low
`Power RF only Technologies,” July 2013.
`3. Vinod Kotipllai, “Impact of Process Variations on 16-nm Dual Floating Gate FET
`using TCAD simulations,” December 2012.
`4. Wenxu Zhao, “Headphone Deiver Design with Inductive Coupled Interconnection,”
`November, 2012.
`
`
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`5. Shiney Gupta, “Multi-Storey Stacked Driver Topolo9gy for Reduced Swing and
`Low Power Bus Operation,”, May 2012.
`6. Pattabhiraman Ravindran, “Harvesting Thermal Energy to Power Agricultural
`Sensors,” October, 2011.
`7. Alex Leaonard, “Implementation of a System-on-Chip for self-healing of analog
`receiver components in a 65 nm CMOS process”, May 2011
`8. Seema Kumar, “Memory Diesgn for Sensor IC,” May 2010.
`9. Mihir Shiveshwarkar, “A Nanocrystal Floating Gate Flash Analog to Digital
`Converter,” December, 2009.
`10. Ojas Bapat. “Design of DDR2 Interface for Tezzaron TSC8200A Octupus Memory
`intended for Chip Stacking Applications,” April 2009.
`11. Peter Gadfort, “Low power driver for silicon carrier interconnects,” April 2009.
`12. Chintan Shah, “Inductively Coupled
`Interconnect
`for Chip
`to Chip
`Commmunication over Transmission Line,” Feb 2009.
`13. Kiran Gonsalves, “Memory Design for FFT Processor in 3DIC Technology,”
`March, 2009.
`14. Vinay Honnavara, “Cost optimization by method of allocating software component
`units to electronic control units for model-driven designs,” October, 2008.
`15. Wei Cao, “Design of temperature sensors for validation of aseptic food processing,”
`Sept. 2008.
`16. Akalu Lentiro, “Implemention of AC Coupled Interconnect Test Vehicle,” May,
`2008.
`17. Vinayak Devasthali, “Application of body biasing and supply voltage scaling
`techniques for leakage reduction and performance improvement of CMOS Circuits,”
`December 2007.
`18. Paul Fernando, “Adding scalability to IBIS using AMS Languages,” September
`2007.
`19. Vivek Jayadav, “Hardware-Software Codesign of a Large Vocabularly Speech
`Recognition System,” February, 2007.
`20. Srivatsan Parthasarathy, “Interfacing AC Coupled Interconnect Design with Rocket
`I/O compatible FPGA Systems,” December 2006.
`21. Janani Mukundan, “Instruction Cache Checkpoints Using Phase Tracking and
`Prediction,” June 2006.
`22. Yasaswini Sudarsanam, “Implementatin of Double Precision Floating Point
`Arithmetic for Matrix Multiplication,” October 2006
`23. Itisha Tyagi, “Design of array based row decoders and self-referencing sense
`amplifier for large scale resistance change style molecular memories,”