UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`__________________________
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`v.
`KATANA SILICON TECHNOLOGIES LLC,
`Patent Owner.
`__________________________
`
`PTAB Case No. IPR 2023-00073
`
`Patent No. 6,352,879
`__________________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,352,879
`__________________________
`
` 
`
` 
`
`
`
`
`
`

`

` 
`
`TABLE OF CONTENTS
` 
`
`Page
`
`
`INTRODUCTION ....................................................................................... 1 
`I. 
`II.  MANDATORY NOTICES ......................................................................... 2 
`A. 
`Real Party-in-Interest ........................................................................ 2 
`B. 
`Related Matters .................................................................................. 2 
`C. 
`Counsel and Service Information ...................................................... 2 
`III.  REQUIREMENTS FOR INTER PARTES REVIEW .................................. 3 
`A.  Grounds For Standing ....................................................................... 3 
`B. 
`Overview of Challenge and Requested Relief .................................. 3 
`1. 
`Identification of Prior Art ....................................................... 3 
`2. 
`Grounds for challenge ............................................................. 4 
`IV.  OVERVIEW OF THE ’879 PATENT ........................................................ 5 
`A. 
`The Alleged Invention ....................................................................... 5 
`B. 
`The Prosecution History .................................................................... 9 
`C. 
`Alleged Priority Date....................................................................... 11 
`D. 
`State of the Art and Applicant Admitted Prior Art ......................... 11 
`CLAIM CONSTRUCTION ...................................................................... 14 
`V. 
`VI.  LEVEL OF ORDINARY SKILL .............................................................. 17 
`VII.  DESCRIPTION OF THE PRIOR ART .................................................... 17 
`A. 
`Ball .................................................................................................. 17 
`B. 
`Fogal ................................................................................................ 19 
`C.  Mostafazadeh ................................................................................... 20 
`D. 
`Tsumura ........................................................................................... 22 
`E.  Ma .................................................................................................... 24 
`VIII.  FLIP-CHIP CLAIMS: GROUNDS FOR CHALLENGE ......................... 25 
`A.  Ground 1: Claim 7 is Obvious over Ball in view of
`Mostafazadeh ................................................................................... 25 
`
`- i -
`
`

`

` 
`
`TABLE OF CONTENTS
`(continued)
`
`B. 
`
`Page
`1.  Motivation to Combine Ball and Mostafazadeh ................... 25 
`2. 
`Independent Claim 7 ............................................................. 28 
`Ground 2: Claims 8 and 9 are Obvious over Ball and
`Mostafazadeh in view of Tsumura .................................................. 43 
`1.  Motivation to Combine Ball and Mostafazadeh and
`Tsumura ................................................................................ 43 
`Dependent Claim 8 ............................................................... 44 
`2. 
`Dependent Claim 9 ............................................................... 48 
`3. 
`IX.  WIRE BOND CLAIMS: GROUNDS FOR CHALLENGE ..................... 48 
`A.  Ground 3: Claims 1-2, 10-11, and 15 are Obvious over
`Ball, Fogal and in further view of Mostafazadeh and in
`view of the General Knowledge of a Skilled Artisan ..................... 49 
`1.  Motivation to Combine Ball, Fogal, and
`Mostafazadeh ........................................................................ 49 
`Independent Claim 1 ............................................................. 51 
`2. 
`Dependent Claim 2 ............................................................... 58 
`3. 
`Independent Claim 10 ........................................................... 60 
`4. 
`Dependent Claim 11 ............................................................. 62 
`5. 
`Independent Claim 15 ........................................................... 63 
`6. 
`Ground 4: Claims 3-4 and 12 Are Obvious Over Ball and
`Fogal in view of Mostafazadeh and Tsumura ................................. 64 
`1.  Motivation to Combine Ball, Fogal, Mostafazadeh,
`and Tsumura .......................................................................... 64 
`Dependent Claim 3 ............................................................... 65 
`2. 
`Dependent Claim 4 ............................................................... 65 
`3. 
`Dependent Claim 12 ............................................................. 66 
`4. 
`Ground 5: Claims 5-6 and 13-14 Are Obvious Over Ball
`and Fogal in view of Mostafazadeh and Ma ................................... 67 
`1.  Motivation to Combine Ball, Fogal, Mostafazadeh,
`
`B. 
`
`C. 
`
`- ii -
`
`

`

` 
`
`TABLE OF CONTENTS
`(continued)
`
`Page
`and Ma ................................................................................... 67 
`Dependent Claim 5 ............................................................... 68 
`2. 
`Dependent Claim 6 ............................................................... 71 
`3. 
`Dependent Claim 13 ............................................................. 73 
`4. 
`Dependent Claim 14 ............................................................. 73 
`5. 
`THE BOARD SHOULD NOT DECLINE REVIEW UNDER
`§314(A) ...................................................................................................... 74 
`XI.  CONCLUSION .......................................................................................... 75 
`
`
`
`X. 
`
`- iii -
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`
`EXHIBIT LIST
`
`
`
`Ex. 1001
`
`U.S. Patent No. 6,352,879 (“’879 patent”)
`
`Ex. 1002
`
`Declaration and Curriculum Vitae of Dr. Jeffrey Suhling (“Suhling”)
`
`Ex. 1003
`
`International Publication WO 1996/13066 (“Mostafazadeh”)
`
`Ex. 1004
`
`U.S. Patent No. 5,323,060 (“Fogal”)
`
`Ex. 1005
`
`U.S. Patent No. 7,166,495 (“Ball”)
`
`Ex. 1006
`
`U.S. Patent No. 5,790,384 (“Ahmad”)
`
`Ex. 1007
`
`U.S. Patent No. 4,821,944 (“Tsumura”)
`
`Ex. 1008
`
`U.S. Patent No. 6,014,586 (“Weinberg”)
`
`Ex. 1009
`
`U.S. Patent No. 6,682,954 (“Ma”)
`
`Ex. 1010
`
`European Patent No. EP0590598A1 (“Mita”)
`
`Ex. 1011
`
`Ex. 1012
`
`Ex. 1013
`
`Ex. 1014
`
`Ex. 1015
`
`Ex. 1016
`
`Ex. 1017
`
`File History - U.S. Reissue Patent No. RE38,806 (family member of
`’879 patent)
`File History - U.S. ’879 patent
`
`File History - U.S. Patent No. 6,229,217 (family member of ’806
`patent)
`File History - U.S. Patent No. 6,100,594 (family member of ’806
`patent)
`JP Unexamined Application Publication 1997/121002 & Certified
`Translation (“Aoki”)
`
`JP Unexamined Application Publication No. 90486/1993 & Certified
`Translation (“Tadasu”)
`
`Eugene J. Rymaszewski, Rao R. Tummala, & Toshihiko Watari, Ch.
`1, Microelectronics Packaging—An Overview, in
`MICROELECTRONICS PACKAGING HANDBOOK (Rao R. Tummala et al.
`eds., 2d ed. 1997).
`
`- iv -
`
`

`

`Ex. 1018
`
`Ex. 1019
`
`Ex. 1020
`
`Ex. 1021
`
`Ex. 1022
`
`1023
`
`Ex. 1024
`
`Ex. 1025
`
`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`
`Kenneth Rose, Tsuneyo Chiba, William R. Heller & Wadie F.
`Mikhal, Ch. 2, Package Wiring and Terminals, in
`MICROELECTRONICS PACKAGING HANDBOOK (Rao R. Tummala et al.
`eds., 2d ed. 1997).
`
`Lewis S. Goldmann, Robert T. Howard & Dexter A. Jeannotte, Ch.
`5, Package Reliability, in MICROELECTRONICS PACKAGING
`HANDBOOK (Rao R. Tummala et al. eds., 2d ed. 1997).
`
`Paul A. Totta, Subash Khadpe, Nicholas G. Koopman, Timothy C.
`Reiley & Michael J. Sheaffer, Ch. 8, Chip-to-Package
`Interconnections, in MICROELECTRONICS PACKAGING HANDBOOK
`(Rao R. Tummala et al. eds., 2d ed. 1997).
`
`Rao R. Tummala, Phil Garrou, Tapan Gupta, N. Kuramoto, Koichi
`Niwa, Yuzo Shimada & Masami Terasawa, Ch. 9, Ceramic
`Packaging, in MICROELECTRONICS PACKAGING HANDBOOK (Rao R.
`Tummala et al. eds., 2d ed. 1997).
`
`Michael G. Pecht & Luu T. Nguyen, Ch. 10, Plastic Packaging, in
`MICROELECTRONICS PACKAGING HANDBOOK (Rao R. Tummala et al.
`eds., 2d ed. 1997).
`
`J. Richard Behun, Thomas Caulfield, Marie Cole, Timothy C.
`Reiley, Pratap Singh & Puligandla Viswanadham, Ch. 16, Package-
`to-Board Interconnections, in MICROELECTRONICS PACKAGING
`HANDBOOK (Rao R. Tummala et al. eds., 2d ed. 1997).
`
`MICROELECTRONICS PACKAGING HANDBOOK, Glossary and Symbols,
`pp. 931-76 (Rao R. Tummala et al. eds., 2d ed. 1997).
`
`Massenat, M., High Density Package, Cofired, Multi Chip Module,
`3D, A Mass Memory Mixed Technology for Space Applications,
`Proceedings of the 9th European Hybrid Microelectronics
`Conference, pp. 216-23 (1994).
`
`Ex. 1026
`
`Al-Sarawi, S. F., Abbott, D., Franzon, P. D., A Review of 3-D
`Packaging Technology, IEEE TRANSACTIONS ON COMPONENTS,
`
`- v -
`
`

`

`PACKAGING, AND MANUFACTURING TECHNOLOGY, Part B, Vol.
`21(1), pp. 2-14, Feb 1998.
`
`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`
`Ex. 1027
`
`D. B. Tuckerman, L.-O. Bauer, N. E. Brathwaite, J. Demmin, K.
`Flatow, R. Hsu, P. Kim, C.-M. Lin, K. Lin, S. Nguyen, & V.
`Thipphavong, Laminated Memory: A New 3-Dimensional
`Packaging Technology for MCM’s, PROCEEDINGS OF THE 1994 IEEE
`MULTI-CHIP MODULE CONFERENCE, pp. 58-63 (Mar. 1994).
`
`Ex. 1028
`
`U.S. Patent No. 5,804,004 to David B. Tuckerman et al.
`
`Ex. 1029
`
`G. Rochat, COB and COC for Low Cost and High Density Package,
`PROCEEDINGS OF THE 17TH IEEE/CPMT INTERNATIONAL
`ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, pp. 109-
`111 (Oct. 1995) (“Rochat”).
`
`Ex. 1030
`
`U.S. Patent No. 4,688,075 to William S. Phy.
`
`Ex. 1031
`
`U.S. Patent No. 5,411,921 to Atsuhito Negoro.
`
`Ex. 1032
`
`U.S. Patent No. 5,762,744 to Kazutaka Shibata et al.
`
`Ex. 1033
`
`U.S. Patent No. 5,110,388 to Mikio Komiyama et al.
`
`Ex. 1034
`
`U.S. Patent No. 6,007,920 to Norito Umehara et al.
`
`
`
`
`- vi -
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Petitioner Micron Technology, Inc. (“Micron”) respectfully requests inter
`
`partes review (“IPR”) of claims 1-15 of U.S. Patent No. 6,352,879 (“’879 patent”)
`
`(Ex. 1001.)
`
`I.
`
`INTRODUCTION
`Cutting through the lengthy recitation of conventional semiconductor
`
`manufacturing steps, the ’879 patent’s alleged invention is simple. The patent’s
`
`purportedly novel idea is to apply an adhesive layer to the backside of a wafer that—
`
`when diced—creates individual chips with adhesive surfaces that make the chip
`
`easier to align and vertically stack in multichip modules.
`
`The concept of a pre-applied adhesive layer, however, is old. Not surprisingly,
`
`this technique was already used in the semiconductor industry and described in
`
`multiple patents, including several patents issued to Micron itself, long before the
`
`’879 patent’s 1998 priority date. The ’879 patent’s identification of conventional
`
`components, such as substrates with wiring layers, flip-chip and wire bonded chip-
`
`on-board interconnections, vertically-stacked chips, and resin encapsulation, cannot
`
`camouflage the fact that nothing was novel or patent-worthy about this common-
`
`sense idea.
`
`Because the claimed invention was both well-known and obvious to a person
`
`of ordinary skill in the art (“POSITA”), Petitioner asks the Board to institute this
`
`Petition and cancel all challenged claims.
`
`– 1 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`
`Micron Technology,
`
`Inc. and
`
`its
`
`subsidiaries,
`
`including Micron
`
`Semiconductor Products, Inc. and Micron Technology Texas, LLC, are the real
`
`parties in interest for this Petition.
`
`B. Related Matters
`
`Patent Owner asserted that Petitioner infringes the ’879 patent along with U.S.
`
`Reissue Patent No. RE38,806 (“’806 patent”) and 6,731,013 (“’013 patent”) in a
`
`district court lawsuit captioned Katana Silicon Techs., LLC. v. Micron Tech., Inc. et
`
`al., No. 1:22-cv-282-BLW (D. Idaho) (transferred from No. 1:22 cv-214 (W.D.
`
`Tex.) on July 11, 2022.).
`
`Petitioner is also filing two Petitions for inter partes review challenging the
`
`’806 patent in IPR 2023-00071 and IPR 2023-00072 and a single Petition
`
`challenging the ’013 patent in IPR 2023-00105.
`
`C. Counsel and Service Information
`
`Lead Counsel
`
`
`
`Amy E. Simpson
`PERKINS COIE LLP
`
`
`
`11452 El Camino Real, Suite 300
`San Diego, CA 92130
`
`
`
`Back-up Counsel
`Amanda Tessar
`PERKINS COIE LLP
`
`Phone: 858-720-5702
`Fax: 858-720-5799
`Simpson-ptab@perkinscoie.com
`USPTO Reg. No. 54,688
`
`Phone: 303-291-2367
`Fax: 303-291-2457
`
`– 2 –
`
`
`
`
`
`
`
`
`
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Tessar-ptab@perkinscoie.com
`USPTO Reg. No. 53,683
`
`1900 Sixteenth Street, Suite 1400
`Denver, CO 80202
`
`
`
`
`Phone: 212-261-6852
`
`
`
`Thomas Matthew
`PERKINS COIE LLP
`Fax: 212-399-8013
`
`
`
`1155 Avenue of the Americas, 22nd Fl. Matthew-ptab@perkinscoie.com
`New York, New York 10036
`
`Pro-Hac Vice pending
`Petitioner consents to electronic service. All services and communications to
`
`the attorneys listed above may be sent to PerkinsMicronIPRs@perkinscoie.com. A
`
`Power of Attorney is concurrently filed with this Petition.
`
`III. REQUIREMENTS FOR INTER PARTES REVIEW
`A. Grounds For Standing
`
`Petitioner certifies that the ’879 patent is available for IPR and that Petitioner
`
`is not barred or estopped from requesting IPR challenging the claims of the ’879
`
`patent on the grounds presented here. This Petition is filed less than one year after
`
`Micron was served with a complaint alleging infringement.
`
`B. Overview of Challenge and Requested Relief
`
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner requests
`
`cancellation of claims 1-15 of the ’879 patent under pre-AIA 35 U.S.C. §103.
`
`1.
`
`Identification of Prior Art
`
`In this Petition, Petitioner relies on the patents listed in the Table of the
`
`Exhibits, including:
`
`– 3 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Exhibit No.
`Ex. 1003: (Mostafazadeh)
`Int. Pub. WO1996/13066
`Ex. 1004: (Fogal)
`U.S. Patent No. 5,323,060
`
`Ex. 1005: (Ball)
`U.S. Patent No. 7,166,495
`
`Ex. 1007: (Tsumura)
`U.S. Patent No. 4,821,944
`
`Ex. 1009: (Ma)
`U.S. Patent No. 6,682,954
`
`Prior Art Reference
`Mostafazadeh published on May 2, 1996 and is
`prior art at least under pre-AIA 35 U.S.C. §102(b).
`Fogal issued on June 21, 1994 and is prior art at
`least under pre-AIA 35 U.S.C. §102(b).
`Ball published on April 18, 2002, from an
`application filed on February 20, 1996, and is prior
`art at least under pre-AIA 35 U.S.C. §102(e).
`Tsumura issued on August 18, 1989 and is prior art
`under pre-AIA 35 U.S.C. §102(b).
`Ma issued on January 27, 2004, from an application
`filed on May 29, 1996, and is prior art at least under
`pre-AIA 35 U.S.C. §102(e).
`
`The Examiner did not cite or discuss any of the prior art now used as grounds
`
`in this Petition during the prosecution of the ’879 patent.
`
`2. Grounds for Challenge
`
`The table below summarizes the grounds and challenges for claims 1-15. The
`
`grounds are organized into two groups: (1) claims 7-9 reciting flip-chip
`
`interconnection techniques; and (2) claims 1-6 and 10-15 reciting wire bond
`
`interconnection techniques.
`
`Ground 1
`
`Ind. claim 7
`
`Statutory Grounds Challenging: Flip-Chip Claims
`Obvious over Ball in view of
`Mostafazadeh
`Obvious over Ball, Mostafazadeh
`and in view of Tsumura
`
`Ground 2 Dep. claims 8 and 9
`
`– 4 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Ground 3
`
`Statutory Grounds Challenging: Wire Bond Claims
`Ind. claims 1, 10, and 15
`Obvious over Ball and Fogal in
`view of Mostafazadeh
`Dep. claims 2 and 11
`Obvious over Ball, Fogal, and
`Mostafazadeh and in view of
`Tsumura
`Obvious over Ball, Fogal, and
`Mostafazadeh and in view of Ma
`
`Ground 4 Dep. claims 3-4 and 12
`
`Ground 5 Dep claims 5-6 and 13-14
`
`This Petition is supported by the declaration of Dr. Jeffrey Suhling
`
`(“Suhling”), whose curriculum vitae is attached as an appendix to Ex. 1002 and
`
`whose declaration demonstrates that there is a reasonable likelihood that Petitioner
`
`will prevail with respect to cancellation of at least one challenged claim. See pre-
`
`AIA 35 U.S.C. § 314(a).
`
`IV. OVERVIEW OF THE ’879 PATENT
`A. The Alleged Invention
`
`The ’879 patent describes a multi-chip stacked semiconductor device and a
`
`method of manufacturing such a device. (’879 patent at 1:10-15, 2:57-59.) The
`
`patent’s Background of the Invention section describes conventional techniques for
`
`vertically stacking semiconductor chips to increase circuit density while producing
`
`a “chip-sized” semiconductor package. The patent explains, however, that when
`
`adhesive agents are used to bond the semiconductor chip to the substrate or other
`
`chips, problems arise resulting in larger and less stable semiconductor packages.
`
`– 5 –
`
`

`

`(’879 patent at 1:49-2:19.)
`
`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`’879 patent - Figure 14(a)
`
`
`
`On the one hand, if too much adhesive is applied, the “adhesive agent spreads
`
`beyond the outer edge of the semiconductor chip.” (’879 patent at 1:49-2:19.) Figure
`
`14(a) shows how the adhesive “overflow” 87a necessitates connecting wires 88 to
`
`the substrate farther from the sides of the semiconductor chips—thereby increasing
`
`the size of the semiconductor package. (’879 patent at 2:20-34.) On the other hand,
`
`if too little adhesive is applied, gaps form, weakening the bond between the chips
`
`and substrate. (’879 patent at 2:39-43.) Finally, the patent explains that conventional
`
`adhesive application processes required multiple steps, including aligning an
`
`adhesive sheet onto a first semiconductor, and then accurately positioning the second
`
`– 6 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`chip onto the adhesive layer of the first chip. These extra steps complicated the
`
`manufacturing process. (’879 patent at 2:44-50, 5:12-20.)
`
`The ’879 patent purports to fix these deficiencies using a common-sense
`
`solution: applying the adhesive agent to the semiconductor wafer before it is diced
`
`into individual chips. (’879 patent at 3:33-36, 4:14-17, 4:44-51, 5:12-18.)
`
`’879 patent - Figure 1 (wire bond interconnection)
`
`
`
`Figure 1 illustrates a cross-section of a semiconductor device with a wire
`
`bonded chip-on-board (or chip and wire) configuration. (’879 patent at 5:34-36,
`
`6:37-38.) Semiconductor chip 1 and semiconductor chip 2 are stacked on insulating
`
`substrate 3. (’879 patent at 6:37-41.) Wiring layer 4 is disposed on insulating
`
`substrate 3. (’879 patent at 6:35-51.) Semiconductor chip 1 is mounted on the
`
`– 7 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`substrate through a bottom adhesion layer (’879 patent at 6:47-48.) Semiconductor
`
`chip 2 is mounted on the circuit-formed surface of semiconductor chip 1 through
`
`adhesion layer 6. (’879 patent at 6:47-52.) Semiconductor chips 1 and 2 are each
`
`wire-bonded to electrode sections of the wiring layer 4 on the insulating substrate 3
`
`with wires 7 to electrically connect the chip’s circuitry to the substrate. (’879 patent
`
`at 7:1-4.) Semiconductor chip 1, semiconductor chip 2, and wires 7 are then covered
`
`by a sealing resin 8. (’879 patent at 7:5-7.)
`
`’879 patent - Figure 10 (flip-chip interconnection)
`
`
`
`Figure 10 shows a conventional flip-chip configuration. (’879 patent at 6:7-9,
`
`11:10-18.) Unlike the first embodiment where the bottom chip’s backside is mounted
`
`– 8 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`directly onto the substrate, the second embodiment uses a flip-chip interconnection
`
`where the chip is placed face-down and connected to the substrate using metal
`
`bumps. (’879 patent at 11:18-21.) As shown in Figure 10, first semiconductor chip
`
`21 is inverted and electrically connected to wiring layer 4 through metal bumps 23.
`
`(’879 patent at 11:34-36.) A second semiconductor chip 22 is mounted on the
`
`adhesive backside of the inverted first semiconductor chip 21. The stacked structure
`
`also includes resin sheet 24 (underfill encapsulant) between the first semiconductor
`
`chip 21 and wiring layer 4 to protect the metal bumps 23. (’879 patent at 11:47-65.)
`
`Importantly, the ’879 patent’s admitted prior art confirms that multichip
`
`module configurations employing wire bond and/or flip-chip interconnections, along
`
`with other components (i.e., substrates with wiring layers, electrode sections,
`
`through-holes, external connection terminals, metal bumps, wire bonds, and resin
`
`encapsulants) were already well-known in semiconductor packaging long before the
`
`’897 patent’s 1998 priority date. (’879 patent at 1:19-2:54.) The ’879 patent’s
`
`allegedly novel concept is nothing more than applying an adhesive layer onto a
`
`semiconductor wafer and then dicing the wafer to produce individual chips with pre-
`
`applied adhesive backsides. This concept was not novel.
`
`B.
`
`The Prosecution History
`
`The ’879 patent is a divisional of U.S. Patent No. 6,100,594 (“’594 patent”)
`
`and claims priority to a Japanese application filed on January 14, 1998. (’879 patent
`
`– 9 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`at Cover.) In 2018, original owner Sharp Kabushiki Kaisha assigned the patent to
`
`non-practicing entity Katana Silicon Technologies LLC. The chart below shows the
`
`’879 patent’s family tree.
`
`
`
`In response to a restriction requirement, Applicant filed all method claims as
`
`a divisional of the ’594 patent. During prosecution, the Examiner rejected pending
`
`claims 30, 31, and 32 under §103(a) over “Admitted Prior Art” and U.S. Patent No.
`
`6,157,080 (“Tamaki”). (Ex. 1012.) The Office Action included a six-page recitation
`
`of claim limitations the Examiner considered as AAPA. (Ex. 1012 at 126-130.)
`
`– 10 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Applicant successfully argued that Tamaki was not prior art under § 103(c)
`
`because Tamaki, like the ’879 patent, was commonly assigned to Sharp Kabushiki
`
`Kaisha. (Ex. 1012 at 137-138.) The Examiner allowed the claims because the prior
`
`art allegedly did not teach first and second semiconductor chips mounted with an
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`adhesive layer between them. (Ex. 1012 at 144.) Importantly, Applicant never
`
`disputed the Examiner’s characterization of the prior art.
`
`C. Alleged Priority Date
`For the purposes of this Petition only, Petitioner assumes the priority date is
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`January 14, 1998.
`
`D.
`State of the Art and Applicant Admitted Prior Art
`In its Background section, Applicant described the state of the art and
`
`problems to be solved with specific reference to Japanese patent applications—Aoki
`
`and Tadasu. Petitioner relies on Aoki and Tadasu and other statements made by the
`
`Applicant in accordance with the PTAB’s June 9, 2022 “Updated Guidance on the
`
`Treatment of Statements of the Applicant in the Challenged Patent in Inter Partes
`
`Review under Section 311” expressly providing that AAPA can be used to establish
`
`background knowledge possessed by a POSITA, to furnish a motivation to combine,
`
`to assess whether a patent’s claims would have been obvious, and/or to supply a
`
`missing limitation.
`
`– 11 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`(1) Aoki
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`Japanese Unexamined Patent Application Publication No. 121002/1997
`
`(“Aoki”) published on May 6, 1997—more than one year before the ’879 patent’s
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`U.S. filing date—and therefore is §102(b) prior art. Applicant disclosed a partial
`
`translation of Aoki in an IDS during prosecution of the ’879 patent. Exhibit 1015 is
`
`a certified full translation of Aoki.
`
`Prior Art (wire bond interconnections)
`’879 Patent - Prior art Figure 13(a)
`Aoki - Figure 1
`
`
`Applicant admitted that Aoki disclosed a conventional wire bonded
`
`
`
`
`
`“semiconductor device having a CSP (chip size package) structure shown in the ’879
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`patent’s Figure 13(a)” describing the CSP structure wherein: “41 is a wiring
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`component, 42 is a semiconductor chip, 43 is a wire, 44 is a resin sealing member,
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`45 is a through-hole, 46 is a substrate, 47 is a wiring pattern, 48 is an insulating
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`material, 49 is an external connection-use terminal, 50 is an electrode . . .” (’879
`
`patent at 1:40-46, 6:17-23.) Aoki’s Figure 1 is identical to the ’879 patent’s Figure
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`13(a) and identifies the same conventional components. (Aoki at ¶¶ [0080]-[0088].)
`
`– 12 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Prior Art (flip-chip interconnections)
`’879 Patent - Prior art Figure 13(b)
`Aoki - Figure 24
`
`
`
`
`
`Likewise, the ’879 patent’s Figure 13(b) depicts a conventional flip-chip
`
`semiconductor device where “61 is a through-hole, 62 is a wiring component, 63 is
`
`an electrode, 64 is a semiconductor chip, 65 is a resin member, 66 is a wiring pattern,
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`67 is an inner connection area, 68 is an external connection area, 69 is an external
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`connection-use terminal, and 70 is a bump electrode.” (’879 patent at 1:46-53, 6:17-
`
`23.) Aoki’s Figure 24 is identical to the ’013 patent’s Figure 13(b) and identifies the
`
`same components. (Aoki at ¶¶ [0016]-[0024].) Each of these admittedly
`
`conventional components are expressly recited in the ’879 patent’s flip-chip and
`
`wire bond claims and were clearly within the general knowledge of a POSITA well
`
`before the ’879 patent’s priority date. (Suhling, ¶¶33-70.)
`
`(2) Tadasu
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`Japanese Unexamined Patent Application Publication No. 90486/1993
`
`(“Tadasu”) published on April 9, 1993 and is statutory prior art under §102(b).
`
`– 13 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Applicant admits that as early as 1993, semiconductor chips were vertically stacked
`
`using flip-chip bump interconnections formed using wire bonding as described in
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`Tadasu. (’879 patent at 1:64-2:5.) A certified translation of Tadasu is attached as Ex.
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`1016.
`
`Any argument by the Patent Owner that these Japanese publications are not
`
`prior art and AAPA is misplaced. Although Aoki and the ’879 patent were—in
`
`1998—commonly owned by Sharp, Applicant’s own work is prior art when—as is
`
`the case here—it falls within the statutory exception under § 102(b). In re Fout, 675
`
`F.2d 297, 301 (CCPA 1982) (finding an applicant’s own invention is prior art when
`
`it falls within a statutory exception under Section 102(b), (c) or (d)); see also
`
`Riverwood Int’l Corp. v. R.A. Jones & Co., Inc., 324 F.3d 1346, 1348 (Fed. Cir.
`
`2003) (“[W]here the inventor continues to improve upon his own work product, his
`
`foundational work product is not, without a statutory basis, prior art solely because
`
`he admits knowledge of his own work.”). As for Tadasu, no common ownership
`
`issue exists, and it published in 1993—more than five years before the ’879 patent’s
`
`1998 U.S. filing date. Therefore, Tadasu is both statutory prior art and AAPA for
`
`purposes of this Petition.
`
`V. CLAIM CONSTRUCTION
`At this time, Petitioner does not believe construction of any term is necessary
`
`to resolve the invalidity challenges set forth in this Petition. See Vivid 10 Techs., Inc.
`
`– 14 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Petitioner reserves the
`
`right to construe terms in the litigation and/or to respond to any constructions that
`
`Patent Owner presents in this proceeding.
`
`Petitioner notes, however, that the term “electrode section” is not commonly
`
`used in the semiconductor packaging industry and seems to be a result of the ’879
`
`patent’s translation from Japanese to English. While the term does not require a
`
`construction because it can be understood by a person of ordinary skill in the art and
`
`its meaning is not likely to be disputed, explanation may be helpful to the Board.
`
`’879 Patent - Figure 2(b)
`
`
`
`The ’879 patent describes that “semiconductor chips are each wire bonded to
`
`electrode sections 13 on the wiring layer.” (’879 patent at 3:19-21, 7:1-4.) Figure
`
`2(b) shows the electrode sections around the perimeter and describes that “electrode
`
`– 15 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`sections 13 are formed on both ends of the wiring layer 4 ... and that each wiring
`
`section 14 connects the land sections 12 to electrode sections 13.” (’879 patent at
`
`7:45-52.)
`
`’879 Patent - Figure 7(a)
`
`
`
`Additionally, Figure 7(a) illustrates semiconductor chip 1 and semiconductor
`
`chip 2 connected to electrode sections 13 on wiring layer with wires 7. (’879 patent
`
`at 10:40-45.)
`
`A POSITA reading the ’879 patent would understand the “electrode sections”
`
`to be electrical terminals, usually called bond pads, that are part of the substrate’s
`
`wiring layer. (Suhling, ¶103.) Wire bond or flip-chip bump interconnections from
`
`the chip are made to these terminals on the substrate, to essentially provide the
`
`substrate’s interface to the chip’s integrated circuitry. (Suhling, ¶¶104-107.)
`
`– 16 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`VI. LEVEL OF ORDINARY SKILL
`As of the alleged January 14, 1998 priority date, a POSITA would have been
`
`a person having at least: i) a bachelor-level degree in electrical engineering,
`
`mechanical engineering, material science, or a related subject and five or more years
`
`of experience working in the field of semiconductor packaging; ii) a Master’s-level
`
`degree in mechanical engineering, electrical engineering, material science, or a
`
`related field, and at least 1-3 years of experience in the design/development of
`
`semiconductor packages; or iii) a Ph.D.-level degree in mechanical engineering,
`
`material science, electrical engineering, or a related field, and at least some
`
`experience in the area of semiconductor packaging. Additional education may
`
`substitute for professional experience, and significant work experience may
`
`substitute for formal education. (Suhling, ¶¶28-32.)
`
`VII. DESCRIPTION OF THE PRIOR ART
`A. Ball
`
`The Ball patent relates to multichip modules having a “stacked package
`
`structure” where semiconductor chips (dies) are vertically stacked on top of one
`
`another using a combination of face-down (flip-chip) or face-up (wire bond)
`
`interconnection configurations. (Ball at Title, Abstract, 1:8-12, 2:16-20, 3:33-37,
`
`3:41-42, and claim 1.)
`
`– 17 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`Ball - Figure 1
`
`
`
`Figure 1 illustrates the preferred embodiment of multichip module 10
`
`comprising upper die 12 and opposing lower die 14. (Ball at 4:58-59, 5:3-6.) Lower
`
`die 14 is connected to insulative substrate 16 via flip-chip electrical connections 20
`
`extending from bond pad 22 on lower die face surface 18 to electrical contact
`
`elements 26 on surface 24 of substrate 16. (Ball at 5:6-18, 5:37.) Sealing/underfill
`
`compound 42 is disposed between lower die 14 and substrate 16 to prevent
`
`contamination of the flip-chip electric connections 20 and to form a more robust
`
`mechanical connection of lower die 14 to substrate 16. (Ball at 5:28-32.)
`
`Ball further teaches adhering a second chip to the backside of the first chip.
`
`Specifically, backside 32 of upper die 12 is adhered to lower die 14 with adhesive
`
`– 18 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`layer 28 applied over backside 30 of lower die 14. (Ball at 5:18-22.) Face side 34 of
`
`upper die 12 includes circuitry and a plurality of bond pads 36. (Ball at 5:23-24.)
`
`Bond wires 38 connect bond pads 36 on upper die 12 to corresponding terminals 40
`
`on upper surface 24 of substrate 16. (Ball at 5:24-27.) As shown by the dashed line
`
`48, the multichip module is encapsulated. (Ball at 5:32-36.) Finally, substrate 16
`
`connects to a chassis or motherboard by edge connections, bump connections, pin
`
`connections, or other conductive arrangements known in the art. (Ball at 5:37-40.)
`
`B.
`Fogal
`The Fogal patent also relates to stacked die multichip modules using a wire
`
`bond interconnection. (Fogal at Title, Abstract.)
`
`Fogal - Figure 1
`Figure 1 depicts first chip 18 having base face 20 and bonding face 22. (Fogal
`
`
`
`– 19 –
`
`

`

`PTAB Case No. IPR 2023-00073
`U.S. Pat. No. 6,352,879
`
`at 2:36-38.) Base face 20 is adhered to substrate 12 by an adhesiv