GLOSSARY AND SYMBOLS
`
`The ISHM Glossary of Hybrid-Circuit Terms (Updated edition(cid:173)
`Summer 1987) by G.S. Szekely provided the foundation for this glossary.
`Definitions have in some cases been modified to fit this work. Other terms
`used by the authors and the packaging profession have been added and
`some terms in the original work have not been deleted. Material chemical
`symbols are found at the end of this glossary.
`
`A
`
`ACCELERATED STRESS TEST. A test conducted at a stress, e.g., chemical
`or physical, higher than that encountered in normal operation, for the purpose
`of producing a measurable effect, such as a fatigue failure, in a shorter time than
`experienced at operating stresses.
`
`ACCELERATOR. An organic compound which is added to an epoxy resin
`to shorten the cure time.
`
`ACTIVE COMPONENTS. Electronic components, such as transistors, diodes,
`electron tubes, thyristors, etc., which can operate on an applied electrical signal
`so as to change its basic characteristics, i.e., rectification, amplification, switch(cid:173)
`ing, etc.
`
`ADDITIVE PLATING. Processing a hybrid circuit substrate by sequentially
`plating conductive, resistive, and insulative materials, each through a mask, thus
`defining the areas of traces, pads, and elements.
`
`ADVANCED STATISTICAL ANALYSIS PROGRAM (ASTAP). The "Ad(cid:173)
`vanced Statistical Analysis Program" is the mM circuit analysis simulation
`program. It performs DC, time domain, and frequency domain simulations. Statis(cid:173)
`tics can be applied to all simulations to predict operating tolerances. Among its
`many features is a transmission line analysis program. Also see SPICE.
`
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`11-932
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`GLOSSARY AND SYMBOLS
`
`ALLOY. A solid-state solution or compound formation of two or more metals.
`Alternatively, a combination of metals resulting in a phase or phases containing
`some of each constituent.
`
`ALPHA PARTICLE. Decay product of some radioactive isotopes. It is a high(cid:173)
`energy (mv range) helium nucleus capable of generating electronlhole pairs in
`microelectronic devices and switching cells, causing soft errors in some devices.
`
`APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC). Applica(cid:173)
`tion Specific Integrated Circuit is an integrated circuit chip with personalization
`customized for a specific product. Personalization refers to wiring on the inte(cid:173)
`grated circuit chip.
`
`AREA ARRAY TAB. Tape automated bonding where edge-located pads and
`additional pads on the inner surface area of a chip are addressed in the bonding
`scheme. This is practiced with extremely complex dice, VLSI etc. Also for use
`with ICs where peripheral pad pitch cannot be further reduced and all 1I0s must
`be accommodated.
`
`ARRAY. A group of elements (pads, pins) or circuits arranged in rows and
`columns on one substrate.
`
`ASPECT RATIO. The ratio of the length of hole to the diameter of hole in
`a board.
`
`ASSEMBLY. A hybrid circuit which includes discrete or integrated compo(cid:173)
`nents that have been attached to the next level of package, usually a card.
`
`ASSEMBLYIREWORK. Terms denoting joining and replacement processes
`of microelectronic components. Assembly refers to the initial attachment of
`device and interconnections to the package. Rework refers to the removal of a
`device including interconnections, preparation of the joining site for a new device,
`and rejoining of the new device. Rework is necessary for either repair or engineer(cid:173)
`ing change.
`
`B
`
`BACKBONDING. Bonding active chips to the substrate using the back of the
`chip, leaving the face, with its circuitry face up. The opposite of backbonding
`is face down bonding.
`
`BACK-END-OF-THE-LINE (BEOL). That portion of the integrated circuit
`fabrication where the active components (transistors, resistors, etc.) are intercon-
`
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`

`

`GLOSSARY AND SYMBOLS
`
`11-933
`
`nected with wiring on the wafer. It includes contacts, insulator, metal levels, and
`bonding sites for chip-to-package connections. Dicing the wafer into individual
`integrated circuit chips is also a BEOL process. The front-end-of-the-line (FEOL)
`denotes the first portion ofthe fabrication where the individual devices (transistors,
`resistors, etc.) are patterned in the semiconductor.
`
`BACK PANEL. A planar package component holding plugged-in lower-level
`package components (e.g., cards) as well as discrete wires and cables interconnect(cid:173)
`ing these components.
`
`BACKSIDE METALLURGY (BSM). A metallization pad electrically con(cid:173)
`nected to internal conductors within a multilayered ceramic package, to which
`pins are brazed.
`
`BALL GRID ARRAY (BGA). A Ball Grid Array is an area array of solder
`balls joined to a SCM or MCM and used to electrically and physically connect
`the package to the next level of package, usually a printed circuit board.
`
`BALL LIMITING METALLURGY (BLM). The solder wettable terminal
`metallurgy which defines the size and area of a soldered connection, such as C4
`and a chip. The BLM limits the flow of the solder ball to the desired area, and
`provides adhesion and contact to the chip wiring.
`
`BANDWIDTH. The maximum pulse rate or frequency that can reliably propa(cid:173)
`gate through a transmission line. For a data bus, bandwidth is commonly used
`to describe the maximum data rate which is the single line pulse rate multiplied
`by the number of parallel bus bit lines.
`
`BIFET. The combination of bipolar and PET transistors integrated together on
`the same piece of silicon for enhanced performance and cost.
`
`BINDER. Materials (organic or inorganic) added to thick-film compositions
`and to unfired substrate materials to give sufficient strength temporarily for
`prefire handling.
`
`BIPOLAR TRANSISTOR. Original transistor design in which two semicon(cid:173)
`ductor junctions (regions of opposite polarity doping) are separated by a narrow
`region, called the base. Minority carriers are injected in the base from the emitter
`across the base-emitter junction, travel through the base, and are attracted to the
`collector through the base-collector junction. These transistors consume more
`power than Field-Effect Transistors (PET), but also achieve higher performance.
`
`BLOCK COPOLYMER. A copolymer compound resulting from the chemical
`reaction between n number of molecules, which are a block of one monomer,
`
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`11-934
`
`GLOSSARY AND SYMBOLS
`
`and .on" number of molecules, which are a block of another monomer. Example:
`stearine (rigid) with silicone (elastic).
`
`BOARD. This package element can best be defined as an organic printed(cid:173)
`circuit card or board on which smaller cards or modules can be mounted. Its
`connections to the next higher level involve discrete wire or cables.
`
`BOILING. Phase change and formation of bubbles in a superheated liquid.
`
`BONDABILITY. Those surface characteristics and conditions of cleanliness
`of a bonding area which must exist in order to provide a capability for successfully
`bonding an interconnection material by one of several methods, such as ultrasonic
`or thermocompression wire bonding.
`
`BRAZE. A joint formed between two different materials by formation of liquid
`at the interface.
`
`BRAZING.
`Joining of metals by melting a non-ferrous, filler brazing metal,
`such as eutectic gold-tin alloy, having a melting point lower than that of the base
`metals. Also known as hard soldering.
`
`BTAB. The acronym for tape automated bonding when the raised bump for
`each bond site is prepared on the tape material as opposed to the bump being
`on the chip.
`
`BUMPED TAPE. A tape for the TAB process where the inner-lead bond sites
`have been formed into raised metal bumps on the tape rather than on the chip.
`This ensures mechanical and electrical separation between inner lead bonds and
`the non-pad areas of the chip (die) being bonded.
`
`BURN·IN. The process of electrically stressing a device (usually at an elevated
`temperature and voltage environment) for an adequate period of time to cause
`failure of marginal devices.
`
`BURN· OFF. Removal of unwanted materials-typically organics from green(cid:173)
`sheets or organic contamination from substrates.
`
`C
`
`CAMBER. A term that describes the amount of overall warpage present in
`a substrate.
`
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`GLOSSARY AND SYMBOLS
`
`11-935
`
`CAPACITANCE. The electrostatic element that stores charge. In packaging
`systems, it is used in lumped equivalent circuits to represent part of a line
`discontinuity. It is also used in a distributed system to represent the electrostatic
`storage property of a transmission line. Because it delivers current in response
`to a change in voltage, another use is to filter powering systems.
`
`CARD. A printed-circuit panel (usually multilayer) that provides the intercon(cid:173)
`nection and power distribution to the electronics on the panel, and provides
`interconnect capability to the next level package. It is also known as a daughter
`board. It plugs into a mother printed-circuit board.
`
`CARD·ON·BOARD. Packaging technology in which multiple printed-circuit
`panels (cards) are connected to printed-circuit panel (board) at 90° angles.
`
`CELL DESIGN, STANDARD. A semicustom product implemented from a
`fully diffused or ion implanted semiconductor wafer carrying horizontal rows of
`primary cells, interlaced with wiring channels (bays). Vertical wiring is supplied
`by additional processed layers which may use the cell areas or lie in channels
`on an overhead layer. Channel widths may vary to suit particular chip logic, so
`that chip sizes are not fixed for all products of a family.
`
`CENTRAL PROCESSOR (CP). Computer processor responsible for fetching,
`interpreting, and executing program instructions. Also called Processor Unit (PU)
`and Central Processing Unit (CPU).
`
`Inorganic, nonmetallic material, such as alumina, beryllia, or
`CERAMIC.
`glass-ceramic, whose final characteristics are produced by subjection to high
`temperatures. Often used in forming ceramic-substrates for packaging semicon(cid:173)
`ductor chips.
`
`CERAMIC BALL GRID ARRAY (CBGA). A ceramic package using ball
`grid array technology. See ball gird array technology.
`
`CERAMIC COLUMN GRID ARRAY (CCGA). A ceramic package using
`ball grid array technology. See ceramic gird array technology.
`
`CERAMIC DUAL·IN·LINE PACKAGE (DIP), Dual-in-line package in ce(cid:173)
`ramic. See Dual-in-line Package.
`
`CERAMIC QUAD FLAT PACK (CQFP). Quad Flat Pack in ceramic. See
`Quad Flat Pack.
`
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`11-936
`
`GLOSSARY AND SYMBOLS
`
`CERMET. A solid homogeneous material usually consisting of a finely divided
`admixture of a metal and ceramic in intimate contact. Cermet thin films are
`normally combinations of dielectric materials and metals.
`
`CHANNELS. Provide communications paths for input to and output from the
`computer system.
`
`CHARACTERISTIC IMPEDANCE (Zo). The voltage-to-current ratio of an
`electric signal propagating through an infinitely long transmission line. If L
`denotes the inductance per unit length and C denotes the capacitance per unit
`length, then ~ = (LlC)O.5.
`
`CHEMICAL VAPOR DEPOSITION (CVD). Depositing circuit elements on
`a substrate by chemical reduction of vapor of volatile chemical in contact with
`the substrate.
`
`CHEMORHEOLOGY. The study of the processability or flow (rheology) and
`the chemistry of the polymer system. Processability parameters include, for
`instance, heating rates, hold temperatures, injection speeds, and compaction pres(cid:173)
`sures. The chemical aspect, on the other hand, involves the rate of reaction, the
`mechanisms, the kinetics, and the cessation of the chemical reaction at the end
`of the polymerization.
`
`CHIP. The uncased and normally leadless form of an electronic component
`part, either passive or active, discrete or integrated. Also referred to as a die.
`
`CHIP CARRIER. A special type of enclosure or package to house a semicon(cid:173)
`ductor device. It has electrical terminations around its perimeter, or solderpads
`on its underside, rather than an extended lead frame or plug-in pins.
`
`CHIP DESIGN, DEPOPULATED. A gate array or standard cell array chip
`in which the wiring capacity (and hence chip area) is deliberately chosen to make
`automatic wiring possible only for those chips having some amount less than
`their maximum possible logic cell occupancy. This increases wafer productivity
`and circuit placement flexibility.
`
`CIDP-ON-BOARD (COB). One of many configurations in which a chip is
`directly bonded to a circuit board or substrate. These approaches include wirebon(cid:173)
`ding, TAB, or solder interconnections, similar to the C4 structure. In low-end
`and consumer systems, chip-on-board generally refers to wirebonding of chips
`directly to board. See also Direct Chip Attach (DCA).
`
`CIRCUIT-BOARD PACKAGING. Packaging of chips by the use of organic
`printed-circuit boards. See Printed-Circuit Board.
`
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`

`

`GLOSSARY AND SYMBOLS
`
`11-937
`
`CLADDING. Thin layer of a corrosion-resistant metal coating bonded to a
`metal core, usually by heating and rolling. Typical examples are steels clad with
`stainless steel, nickel alloys, or copper alloys. Copper cladding on both sides of
`invar is accomplished this way.
`
`CLOCK SKEW. A cycle time adder caused by the amount of tolerance associ(cid:173)
`ated with the clock signal arrival times at all of the system latch inputs.
`
`CMOS. See Complementary Metal-Oxide Semiconductor.
`
`COATED-METAL CORE SUBSTRATE. A substrate consisting of an or(cid:173)
`ganic or inorganic insulation coating bonded to metal. Insulated surface or surfaces
`are used for circuit deposition.
`
`COEFFICIENT OF THERMAL EXPANSION (CTE). The ratio of the
`change in dimensions to the change in temperature-per-unit starting length, usually
`expressed in cm/cm/DC. The acronyms TCE and CTE are synomous.
`
`COFFIN-MANSON EQUATION. A commonly used formula, first proposed
`by S.S. Manson and L.F. Coffin, relating the fatigue lifetime of a metal to the
`imposed strain amplitude. Others have extended the formula to incorporate time
`and temperature dependent phenomena.
`
`COFIRING. Processing thick-film conductors and dielectrics through the firing
`cycle at the same time to form multilayer structures.
`
`COLORANT. An inorganic or organic compound that is added to a polymeric
`resin to impart a desired color.
`
`COLUMN GRID ARRAY (CGA). A Column Grid Array is an area array of
`solder columns joined to an SCM or MCM and used to electrically and physically
`connect the package to the next level of package, usually a printed circuit board.
`A Column Grid Array is used when the package performance requires a higher
`riliability that provided with the similiar Ball Grid Array.
`
`COMPLIANT BOND. A bond which uses an elastically and/or plastically
`deformable member to impart the required energy to the lead.
`
`COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS).
`This refers to logic in which cascaded field effect transistors (PET) of opposite
`polarity are used to minimize power consumption.
`
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`

`11-938
`
`GLOSSARY AND SYMBOLS
`
`COMPRESSION SEAL. A seal between an electronic package and its leads.
`The seal is formed as the heated metal, when cooled, shrinks around the glass
`insulator, thereby forming a tight compression joint.
`
`CONDUCTION. Thermal transmission of heat energy from a hotter region to
`a cooler region in a conducting medium.
`
`CONDUCTIVE ADHESIVE. An adhesive material, usually epoxy, that has
`metal powder added to increase electrical conductivity. Usual conductor added
`is silver.
`
`CONDUCTIVE EPOXY. An epoxy material (polymer resin) that has been
`made conductive by the addition of a metal powder, usually gold or silver. Best
`common conductors are silver, copper, and gold. See also Superconductor, and
`Conductor Adhesive.
`
`CONDUCTOR, ELECTRICAL. A class of materials that conduct electricity
`easily. They have very low resistivity which is usually expressed in micro-ohm(cid:173)
`cm. The best conductors include silver, copper, gold, and superconducting-ce(cid:173)
`ramics.
`
`CONDUCTOR, THERMAL. A class of materials, such as copper, aluminum,
`and beryllia, that conduct heat.
`
`CONFORMAL COATING. A thin nonconductive coating, either plastic or
`inorganic, applied to a circuit for environmental and/or mechanical protection.
`
`CONNECTIONS. The connections belonging to nets interconnecting logic
`units on a given package level-including connections to terminals on that level(cid:173)
`connecting it to the next higher package level.
`
`CONNECTIVITY. See Wiring Density.
`
`CONTACT ANGLE. The angle between the bonding material, usually a liq(cid:173)
`uid-like solder, and the bonding pad. Also called wetting angle.
`
`CONTACT RESISTANCE. Excess electrical resistance in series with the
`bulk conductor resistance of two contacting electrical conductors arising from the
`nature of the contact geometry and surface properties of the contacting surfaces.
`
`CONTROLLED COLLAPSE CHIP CONNECTION (C4). A solder joint
`connecting a substrate and a flip chip, where the surface tension forces of the
`liquid solder supports the weight of the chip and controls the height (collapse)
`of the joint.
`
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`

`GLOSSARY AND SYMBOLS
`
`11-939
`
`CONTROLLING COLLAPSE. Controlling the reduction in height of the
`solder balls in a flip-chip processing operation.
`
`CONVECTION. Transmission of thermal energy from a hotter to a cooler
`region through a moving medium, such as air or water.
`
`COPLANAR LEADS (FLAT LEADS). Ribbon-type leads extending from
`the sides of the circuit package, all lying in the same plane for surface mount appli(cid:173)
`cations.
`
`COPOLYMER. A compound, resulting from the chemical reaction and poly(cid:173)
`merization of two chemically different monomers. The resulting larger molecules
`contain repeating structural units of the original molecules.
`
`CORDIERITE. A crystalline ceramic material of composition 2MgO-2A120r
`5Si02 that can be crystallized from glass of same composition or sintered
`from powders.
`
`COUPLED NOISE.
`(Same as Cross talk) The electromagnetic and electrostatic
`linkages between two nearby conductors that allow one line to induce a signal
`on the other. See also Cross Talk.
`
`COUPLER. A chemical agent, frequently an organosilane, used to enhance
`the bond between a resin and a glass reinforcement.
`
`COUPLING CAPACITOR. A capacitor used to block dc signals, and to pass
`high-frequency signals between parts of an electronic circuit.
`
`CRAZING. Fine cracks which may extend on or through layers of plastic or
`glass materials.
`
`CREEP. Nonrecoverable deformation proceeding at relatively low strain rates,
`less than about lQ-6/sec, usually associated with sufficiently high temperature
`to allow significant rates of diffusion.
`
`CROSSOVER. The transverse crossing of metallization paths without mutual
`electrical contact. This is achieved by the deposition of an insulating layer between
`the conducting paths at the area of crossing.
`
`CROSS TALK. Signals from one line leaking into another nearby conductor
`because of capacitance or inductive coupling or both (i.e., owing to the capacitance
`of a thick-film crossover.).
`
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`

`11-940
`
`GLOSSARY AND SYMBOLS
`
`CRYSTALLIZATION. Formation of crystalline phase out of amorphous ma(cid:173)
`terial during high-temperature processing. Undesirable or uncontrollable crystalli(cid:173)
`zation is called divitrification.
`
`CUMULATIVE DISTRIBUTION FUNCTION (CDF). Distribution of a pa(cid:173)
`rameter as a fraction of the total number of measurements with respect to a
`statistic, e.g. "probits" or standard deviations relative to a particular statistical
`distribution, i.e., normal, etc.
`
`CURING AGENT. An inorganic or organic compound which initiates the
`polymerization of a resin.
`
`CURING CYCLE. For a thermosetting material, commonly a resin compound
`such as a bonding adhesive, it is the combination of total time-temperature profile
`to achieve the desired result; for example, the complete irreversible hardening
`of the material, resulting in a strong bond.
`
`CURRENT CARRYING CAPACITY. The maximum current that can be
`continuously carried by a circuit without causing objectionable degradation in
`electrical or mechanical properties.
`
`CURRENT SLEW RATE. The rate of change in current with respect to time
`(dildt).
`
`CUSTOM DESIGN. A form of design in which the choice and arrangement
`of components and wiring on a package may vary arbitrarily within tolerances
`from a regular array.
`
`CYCLE TIME. Unit of time in which elements of the central processor com(cid:173)
`plete their logical functions. Some elements will require more than one cycle to
`complete a function. See Cycles per Instruction.
`
`CYCLES PER INSTRUCTION. The number of cycles required to process
`an instruction.
`
`D
`
`DECOUPLING CAPACITOR. A shunt-placed capacitance that is used to
`filter transients on a power distribution system.
`
`DELAY EQUATIONS. A set of mathematical terms that are used to predict the
`propagation times between driving and receiving circuits that are interconnected
`
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`

`

`GLOSSARY AND SYMBOLS
`
`11-941
`
`through signal wires. These equations are usually derived from simulation data
`using numerical curve fitting techniques.
`
`DELTA-I NOISE (AI). See Switching Noise.
`
`DESIGN LIMITS. The fail points that are incorporated into the hardware
`design rules that drive the computer-aided design system. See noise rules and
`wiring rules.
`
`DEVITRIFICATION. The undesirable formation of crystals in glass during
`firing. The desirable process is called crystallization.
`
`DEW POINT. The temperature at which moisture at a given partial pressure
`becomes saturated, and when cooled below which, it condenses.
`
`DIE.
`
`Integrated circuit chip as cut (diced) from finished wafer. See Chip.
`
`DIE BOND. Mechanical attachment of silicon to substrate usually by solder,
`epoxy, or gold-silicon eutectic, including interface metallurgies on chip and
`substrate. The die bond is made to the back (inactive) side of the chip with the
`circuit side (face) up.
`
`DIELECTRIC. Material that does not conduct electricity. Generally used for
`making capacitors, insulating conductors (as in crossover and multilayered cir(cid:173)
`cuits), and for encapsulating circuits.
`
`DIELECTRIC CONSTANT. The term used to describe a material's ability
`to store charge when used as a capacitor dielectric. It is the ratio of the charge
`that would be stored with free space to that stored with the material in question
`as the dielectric.
`
`DIELECTRIC LOSS. The power dissipated by a dielectric as the friction of its
`molecules opposes the molecular motion produced by an alternative electric field.
`
`DIFFERENTIAL SCANNING CALORIMETRY (DSC). A technique for
`measuring the physical transitions of a polymer as a function of temperature
`compared to another material undergoing a similar heating process but not under(cid:173)
`going any transitions or reactions. DSC uses a servo system to supply energy at
`a varying rate to both sample and reference so as to keep their temperatures
`equal. A DSC output plots energy supplied vs. average temperature.
`
`DIRECT ACCESS STORAGE DEVICE (DASD). Computer storage hard(cid:173)
`ware subsystem that uses magnetic recording on a rotating disk surface. Access
`
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`

`11-942
`
`GLOSSARY AND SYMBOLS
`
`to the information is accomplished with the use of a moveable arm which positions
`one or more read/write heads along the radius of the disk to the desired track.
`
`DIRECT CHIP ATTACH (DCA). A name applied to any of the chip-to(cid:173)
`substrate connections used to eliminate the first level of packaging: see also
`Chip-on-Board.
`
`Individual components or elements, such as re(cid:173)
`DISCRETE COMPONENT.
`sistors, capacitors, transistors, diodes, inductors, and others, as self-contained
`entities.
`
`DISTANCE TO NEUTRAL POINT (DNP). The separation of a joint from
`the neutral point on a chip. This dimension controls the strain on the joint imposed
`by expansion mismatch between chip and substrate. The neutral point is usually
`the geometric center of an array of pads and defines the point at which there is
`no relative motion of chip and substrate in the X-Yplane during thermal cycling.
`
`DOCTOR BLADE. A method of casting slurry into a thin sheet by the use
`of knife blade placed over moving carrier to control slurry thickness.
`
`DOUBLE-SIDED SUBSTRATE. A substrate carrying active circuitry on both
`its topside and bottomside, electrically connected by means of metallized through(cid:173)
`holes or edge metallization or both.
`
`DRIVER. The off chip circuit that supplies the signal voltage and current to
`the package lines. Also called an output buffer circuit.
`
`DRY FILM PHOTORESIST. Photoresist material that is processed dry, usu(cid:173)
`ally by lamination of prefabricated film.
`
`DRY PRESSING. Pressing and compacting together of dry powdered materials
`with additives in rigid die molds under heat and pressure to form a solid mass,
`usually followed by sintering to form shapes.
`
`DUAL-IN-LINE PACKAGE (DIP). A package having two rows of leads
`extending at right angles from the base and having standard spacings between
`leads and between rows of leads. DIPs are made of ceramic (Cerdip) and plas(cid:173)
`tic (Pdip).
`
`DYNAMIC FLEX. A form of flexible circuitry developed for applications
`where continued flexure is necessary. In contrast, static (flex), once installed,
`remains fixed.
`
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`GLOSSARY AND SYMBOLS
`
`/1-943
`
`DYNAMIC RANDOM ACCESS MEMORY (DRAM). Electronic informa(cid:173)
`tion storage that employs transient phenomena, typically charge stored in a leaky
`capacitor. Refresh cycles are required to restore and thus maintain the information.
`DRAM is the simplest and least expensive of electronic memories, but it is also
`the least impressive performer.
`
`E
`
`EFFECTIVE INDUCTANCE (LEFF). A simplified characterization of the
`goodness of an AC power distribution system. It consists of a single lumped
`inductance that when multiplied by the total current slew rate predicts the total
`switching noise across the circuit load.
`
`ELECTRICALLY LONG TRANSMISSION LINE. One in which the delay
`from the near-end to the far-end is greater than one-half of the near-end signal's
`transition time. When this occurs, the reflections from the far-end do not distort
`the near-end signal during its transition time.
`
`ELECTRICALLY SHORT TRANSMISSION LINE. One in which the delay
`from the near-end to the far-end is less than one-half of the near-end signal's
`transition time. For this case, reflections from the far-end interfere with the near(cid:173)
`end transition waveform causing distortion that usually increases the net's delay.
`
`ELECTROLESS PLATING. Metal deposition, usually in an aqueous me(cid:173)
`dium, which proceeds by an exchange reaction between metal complexes in the
`solution and the particular metal to be coated; the reaction does not require
`externally applied electric current.
`
`ELECTROPLATING. Deposition of an adherent metallic coating onto a con(cid:173)
`ductive object placed into an electrolytic bath composed of a solution of the salt
`of the metal to be plated. Using the terminal as the anode (possibly of the same
`metal as the one used for plating), a DC current is passed through the solution
`affecting transfer of metals ions onto the cathodic surface.
`
`ELECTROSTATIC DISCHARGE (ESD). Discharge of static charge on a
`surface or body through a conductive path to ground. An electronic component or
`higher-level assembly may suffer damage when it is included in the discharge path.
`
`ELONGATION. The ratio of the increase in wire length at rupture, in a tensile
`test, to the initial length, expressed in percent.
`
`EMITTER-COUPLED LOGIC (ECL). Emitter-coupled logic is also known
`as current-switch (logic) circuits. In it, a current source feeds emitters of several
`
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`GLOSSARY AND SYMBOLS
`
`transistors. The base of all but one acts as input tenninals; the last base is
`connected to a reference voltage. Very popular circuit for high-performance
`applications, it is often combined with an emitter-follower output stage to further
`enhance its performance. It is then called SeEF, for current-switch emitter fol(cid:173)
`lower.
`
`ENAMELING. A process that produces pore-free glass dielectric coating over
`a metal-core substrate.
`
`ENCAPSULATION. Sealing up or covering an element or circuit for mechani(cid:173)
`cal and environmental protection.
`
`END OF LIFE (EOL). The end of the useful operating life of a component
`or equipment detennined by a "wear -out" or life tenninating mechanism measured
`in units of time. EOL is usually specified as an objective in reliability calculations.
`
`ENGINEERING CHANGE (EC). A change in design. An electrical design
`change is frequently implanted by cutting out or adding an electrical path to
`the manufactured hardware, e.g., laser deleting a line or adding a wire on a
`ceramic substrate.
`
`ENTITY. A group of circuits separated from other circuits by a physical
`package boundary and associated input and output connections.
`
`EUTECTIC. A term applied to the mixture of two or more substances with
`the the lowest melting point possible between those components.
`
`EXTERNAL RESISTANCE. A term used to represent thermal resistance
`from a convenient point on the outside surface of an electronic package to an
`ambient reference point.
`
`F
`
`FAILURE. The temporary or permanent impairment of device function caused
`by physical, chemical, mechanical, electrical, or electromagnetic disturbance
`or damage.
`
`FAILURE RATE. The rate at which devices from a given population can
`be expected (or were found) to fail as a function of time (e.g., %/1000 hr.
`of operation).
`
`FAST WAVE PROPAGATION. The transmission of energy along a signal
`line at the speed-of-light (velocity) expected for the dielectric structure. In the
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`GLOSSARY AND SYMBOLS
`
`11-945
`
`case of a low-loss line, the fast wave refers to the portion of the signal that
`travels at the velocity expected for the dielectric medium.
`
`FATIGUE. Used to describe the failure of any structure caused by repeated
`application of stress over a period of time.
`
`FERROELECTRIC. A crystalline dielectric that exhibits dielectric hysteresis;
`an electrostatic analogy to ferromagnetic materials.
`
`FIELD EFFECT TRANSISTOR (FET). A transistor in which a voltage
`in a
`applied to a thin conductor over a thin insulator controls current flow
`semiconductor region (gate) or one polar type. This component originates and
`terminates in two regions of the opposite polar type located at either end of the
`gate region.
`
`FIELD REPLACEABLE UNIT (FRU). A component or sub-system of an
`electronic assembly which may be replaced at the site of installation. A first- or
`second-level package is commonly an FRU for most computers.
`
`FILLER. A substance, usually ceramic or metal powder, used to modify the
`properties of fluids or polymers.
`
`FINITE ELEMENT MODELING. A computationally intensive numerical
`modeling tool in which the body is discretized into small regularly shaped ele(cid:173)
`ments.
`
`FIRST-INCIDENT SWITCHING. The case that occurs when all of the re(cid:173)
`ceivers on a multi-drop net switch at the first time the signal arrives from the
`driver. Nets that are not first-incident are referred to as multi-reflection nets.
`
`FLAME RETARDER. An inorganic or organic compound added to a polymer
`mixture that causes the resulting plastic to self-extinguish after a flame is removed.
`
`FLAT PAC. An integrated circuit package having its leads extending from all
`four sides and parallel to the base.
`
`FLEXIBLE CIRCUIT CARRIER. Printed circuits employing flexible sub(cid:173)
`strates, processed by patterning copper onto thin flexible Kapton or polyimide
`films. Originally used only as connector; now employed for multilayers.
`
`FLEXIBLE COATING. A plastic coating that is still flexible after curing.
`
`FLEXURAL STRENGTH. Strength of a material measured by bending, typi(cid:173)
`cally used for brittle materials, such as glasses and ceramics; expressed in MPa.
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`11-946
`
`GLOSSARY AND SYMBOLS
`
`FLIP-CHIP. A leadless, monolithic structure containing circuit elements,
`which is designed to electrically and mechanically interconnect to the hybrid
`circuit by means of an appropriate number of bumps, which are covered with a
`conductive bonding agent, located on its face. Alternatively, bonding of chips
`with contact pads, face down by solder connection. See also Controlled Collapse
`Chip Connection (C4).
`
`FLOOR PLANNING. A procedure in physical design which permits approxi(cid:173)
`mate shaping and p