File Histories
`The world’s leading IP decision makers
`turn to us for one reason. Trust.
`
`Good decisions require reliable intelligence. That’s why more
`IP decision makers rely on us.
`
`We empower companies to build and protect their valuable
`assets with services that span the full IP lifecycle. Our blend
`of global expertise, resources, and technology translates to
`results you can rely on with certainty. In any language, we’re
`the name you can trust.
`
`IP Services from Clarivate Analytics
`Patent search and analytics
`• Prior art search
`• Patent watch
`• Patent profiles
`
`Patent licensing
`• Patent-to-product mapping
`• Standards mapping
`• Licensing opportunity analysis
`• Patent acquisition analysis
`• Claims charting
`
`Patent preparation and prosecution
`• Patent drafting
`• Prosecution services
`
`IP analytics
`• Technology landscaping
`• Patent portfolio audit
`• Competitive portfolio assessment
`
`IP management
`• Data validation services
`• IP payments
`• IP docketing
`• IP management consulting
`• Paralegal services
`• Proofreading
`
`Translation services and file histories
`
`For more information, call us at +1-800-445-9760
`or email fhservice@clarivate.com
`
`Alexandria
`+1 800 445 9760 (US)
`+1 703 916 1500 (International)
`filehistories.clarivate.com
`
`IP 1702 300
`07.2017
`© 2017 Clarivate Analytics
`
`clarivate.com
`
`1/218
`
`MICRON 1014
`
`

`

`
`
`FILE HISTORY
`US 6,100,594
`
`6,100,594
`PATENT:
`INVENTORS: FUKUI YASUKI
`SOTA YOSHIKI
`MATSUNE YUJI
`NARAI ATSUYA
`
`TITLE:
`
`Semiconductor device and method of
`manufacturing the same
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
`
`US1998223272A
`
`30 DEC 1998
`08 AUG 2000
`
`COMPILED:
`
`21 OCT 2022
`
`2/218
`
`MICRON 1014
`
`

`

`[ Q$/L~ OJ.P.E.
`
`SCANNED
`
`G~~i
`.A. ~
`
`fPATENT
`
`DATE
`
`WI0
`II-F
`
`05
`05t
`
`A
`-U
`N
`
`-
`
`o 4
`
`
`
`C%3
`--
`=0DI, "
`
`U
`
`a
`
`SECTOR
`
`CLASS
`
`SUBCLASS
`
`ART UNIT
`
`§-XAMINER
`
`FILED WITH:
`
`1DISK (CRF) 5 FICHE
`
`(Mft ed 1i pe"
`
`on right hiside flap)
`
`Z11PREPARED AND APPROVED FOR ISSUE
`ISSUING CLASSIFICATION
`CROSS REFERENCE(S)
`
`ORIGINAL
`
`CLASS
`
`SUBCLASS
`77
`,?Q
`
`i7_ i
`CLASS
`
`SUBCLASS (ONE SUBCLASS PER BLOCK)
`__I III III
`
`_
`
`, -j/ --
`INTERNATIONAL CLASSIFICATION
`
`-
`
`-7
`
`0 Continued on Issue Slip Inside File Jacket
`
`mTERMINAL
`DISCLAIMER
`
`DRAWINGS
`Figs. Drwg.
`
`Print Fig.
`
`, CLAIMS ALLOWED
`Prnt Claim for O.G.
`Total Claims
`
`Sheetd Drwg.
`
`":
`Qa) The term of this patent
`subsequent to
`has been disclaimed.
`
`(date)
`
`___
`
`(Assistant Examiner)
`
`(Date)
`
`Q b) The term of this patent shall
`not extend beyond the expiration date,
`of U.S Patent. No.
`
`c) The torminal __months of
`this patent have beeti disclaimed.
`
`1
`
`SHEILA V. CLARK
`OrRPIMARY EXAMINER
`
`~ 4 >~'t
`
`(Primary Examner)
`
`(Date)rt
`
`' NO44TICE OF ALLOWANCE
`AL
`E MAILD
`
`_+2 _2Z..
`
`..
`
`ISSUE FEE
`
`"Amount Due
`
`~e
`
`ISSUE BATCH NOMBE&
`
`d
`
`b
`
`(LegalIstumnt Examiner
`
`WARNING:
`The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Office Is restricted to authorized employees and contractors only.
`,lt NI 193.g-J! Itiz
`
`Form PTO-436A
`(Rev, Woo)
`
`(LABEL ARE 5 w,_nqti
`
`Forma :
`
`7 tz
`
`3/218
`
`MICRON 1014
`
`

`

`6,100,594
`
`SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
`THE SAME
`
`Transaction History
`Transaction Description
`Date
`12-30-1998 Request for Foreign Priority (Priority Papers May Be Included)
`01-11-1999 Initial Exam Team nn
`02-02-1999 Information Disclosure Statement (IDS) Filed
`02-02-1999 Information Disclosure Statement (IDS) Filed
`02-04-1999 Application Dispatched from OIPE
`04-22-1999 Case Docketed to Examiner in GAU
`04-26-1999 Restriction-Election Requirement
`04-27-1999 Mail Restriction Requirement
`05-24-1999 Response to Election - Restriction Filed
`08-19-1999 Information Disclosure Statement (IDS) Filed
`08-19-1999 Information Disclosure Statement (IDS) Filed
`08-19-1999 Miscellaneous Incoming Letter
`09-13-1999 Information Disclosure Statement (IDS) Filed
`09-13-1999 Information Disclosure Statement (IDS) Filed
`03-22-2000 Mail Notice of Allowance
`03-22-2000 Notice of Allowance Data Verification Completed
`04-28-2000 Workflow - File Sent to Contractor
`06-21-2000 Issue Fee Payment Verified
`06-29-2000 Workflow - Drawings Finished
`06-29-2000 Workflow - Drawings Matched with File at Contractor
`06-29-2000 Workflow - Drawings Received at Contractor
`06-29-2000 Workflow - Complete WF Records for Drawings
`07-02-2000 Application Is Considered Ready for Issue
`07-20-2000 Issue Notification Mailed
`08-08-2000 Recordation of Patent Grant Mailed
` 
`
`4/218
`
`MICRON 1014
`
`

`

`PATENT APPLICATION
`
`09223272
`
`jc52s U.S. PTO
`O9/223272
`
`12109
`
`CONTENTS
`Date received
`(Incl. C. of M.)
`or
`Date Mailed
`
`42.
`
`-
`
`4 4 .
`4 5 .-
`
`INITIALS
`JAN
`
`.
`
`4.
`
`Date received
`(incl. C. of M.)
`or
`Date Mailed
`
`9.
`
`f
`
`10.
`11.
`
`12.
`
`13.
`
`14.
`
`15.
`
`16.
`
`17.
`
`18.
`
`19.
`
`20.
`
`21.
`
`22.
`
`23.
`
`24.
`
`25.
`
`26.
`
`27.
`
`28.
`
`29.
`
`30.
`
`31.
`
`32.
`
`33.
`
`34.
`
`35.
`
`36.
`
`37.
`
`38.
`
`39.
`40.
`
`Ai
`
`46.
`
`47.
`
`48.
`
`49.
`50.
`51.
`
`52.
`
`53.
`
`54.
`
`55.
`
`56.
`
`57.
`
`58.
`
`59.
`
`6 0 .
`
`61.
`
`62.
`
`63.
`
`64.
`
`65.
`
`6 6 .
`
`67.
`
`68.
`
`69.
`
`-
`
`-
`
`70. __
`
`71.
`
`,.
`
`72.
`
`73.
`
`74.
`
`75.
`
`76.
`
`77.
`
`78.
`
`79.
`
`80.
`
`81.
`
`82.
`
`t--
`
`\-
`
`_
`
`_
`
`_
`
`5/218
`
`MICRON 1014
`
`

`

`ISSUE SLIP STAPLE
`
`iE" it, '2--itiona cross references)
`
`POSITWON
`
`INITIALS
`
`ID NO.
`
`FEE DETERMINATION
`O.I.P.E. CLASSIFIER
`FORMALITY REVIEW
`
`-
`
`K)
`
`_._________
`
`/ .....
`
`i
`
`6
`
`DATE
`
`/ //
`
`INDEX OF CLAIMS
`Non-elected
`N ....................
`................................. Rejected
`Interference
`I ................................
`.Allowed
`A ................................. Appeal
`(Through numeral)... Canceled
`................................. Objected
`0
`................................. Restricted
`
`Claiml
`
`Date
`
`Claim
`
`Date
`
`Claim
`
`Date
`
`1
`
`51
`52
`53
`54
`55
`56
`
`58
`59
`60
`61
`62
`
`63
`
`65
`66
`'67
`68
`69
`70
`
`71
`72
`73
`74
`75
`76
`77
`78
`793
`80
`181
`82
`83
`
`s51
`861
`87
`88=
`89
`90
`
`911
`921
`931
`941
`951
`961
`971
`
`991
`
`_
`
`t
`
`ci
`
`o
`
`101
`1L04
`102
`10
`104'
`
`1016
`
`107
`
`1109
`1145
`
`112
`18
`
`11
`114
`117
`118
`119
`115
`120
`121
`022
`
`124
`125
`126
`
`113
`
`128
`
`140
`131
`132
`
`14,3
`11315
`
`1401
`
`1544
`
`If more than 150 claims or 10 actions
`staple additional sheet here
`
`1
`
`61k
`
`I
`
`tv 101111
`
`Il '1311 1 1
`q_14111
`1
`1511 1 1
`
`l;
`
`20
`J211
`
`26
`
`26
`
`28
`29 ~
`
`3 4
`
`35
`136
`137.
`38
`391
`40
`411
`42
`43
`441
`451
`461_
`471
`48A
`49
`50
`
`_
`
`_
`
`_
`
`6/218
`
`MICRON 1014
`
`

`

`SEARCH NOTES
`(INCLUDING SEARCH STRATEGY)
`
`Date
`
`Exmr.
`
`INTERFERENCE SEARCHED
`Exmr.
`Date
`Sub.
`Class
`
`' 221
`
`7/218
`
`MICRON 1014
`
`

`

`United States Patent [19]
`Fukui et al.
`
`[54] SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`[75]
`
`Inventors: Yasuki Fukui, Tenri; Yoshiki Sota,
`Nara; Yuji Matsune, Tenri; Atsuya
`Narai, Yamatokoriyama, all of Japan
`
`[73] Assignee: Sharp Kabushiki Kaisha, Osaka, Japan
`
`[21] Appl. No.: 09/223,272
`
`[22] Filed:
`[30]
`
`Dec. 30, 1998
`
`Foreign Application Priority Data
`
`Jan. 14, 2000
`
`[JP]
`
`[51]
`
`Int. Cl.
`
`..................
`
`10-005221
`..................................
`Japan
`......... H01L 23/48; HO1L 23/52;
`HO1L 29/40
`257/777; 257/685; 257/686
`[52] U.S. Cl. ...........................
`[58] Field of Search .....................................
`257/777, 685,
`257/686, 723, 724, 778
`
`[56]
`
`References Cited
`
`FOREIGN PATENT DOCUMENTS
`
`5-90486
`9-121002
`
`4/1993
`5/1997
`
`Japan
`Japan
`
`1111111111111I111II11111111II1111
`
`US006100594A
`[11] Patent Number:
`[45] Date of Patent:
`
`111111111
`
`1111uG
`
`I
`
`NI
`
`6,100,594
`Aug. 8, 2000
`
`OTHER PUBLICATIONS
`U.S. Patent application Ser. No. 09/136,339, filed Nov. 5,
`1998.
`U.S. Patent application Ser. No. 09/186,339, filed Nov. 5,
`1998.
`
`Primary Examiner-Sheila V. Clark
`Attorney, Agent, or Firm-Nixon & Vanderhye, P.C.
`[57]
`ABSTRACT
`
`A first semiconductor chip is produced by affixing a thermo-
`compression sheet to the back surface of a wafer having a
`circuit formed on its front surface. The first semiconductor
`chip is mounted on a circuit board including an insulating
`substrate and a wiring layer provided on the insulating
`substrate so that the back surface of the first semiconductor
`chip faces the circuit board. A second semiconductor chip
`produced in the same manner as the first semiconductor chip
`is mounted on the first semiconductor chip with its back
`surface facing the first semiconductor chip. Each of the first
`and second semiconductor chips is wire-bonded
`to the
`wiring layer with a wire. The first and second semiconductor
`chips and the wire are sealed with a sealing resin. The wiring
`layer is connected to external connection terminals through
`via holes provided in the insulating substrate.
`
`29 Claims, 15 Drawing Sheets
`
`S
`
`6
`
`1
`
`(2
`
`(7
`
`7
`
`S6
`
`3
`
`12
`
`10
`
`8/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet I of 15
`
`691009594
`
`FIG.1
`
`B
`
`4T7
`
`9
`
`12M1
`
`12
`
`10
`
`6
`
`3
`
`9/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 2 of 15
`
`691009594
`
`FIG.2 (a)
`
`0
`C30000M
`O000-
`00002
`-00O0
`
`0
`C300000
`=O000 =
`0000 C
`0OOO=
`
`0
`C300000
`OOg00
`OOOO
`=0OO0O
`
`3
`
`5
`
`l1b
`
`6
`
`1200M
`go00O2
`goOO=
`-O3O
`
`0
`
`0
`
`0
`
`q
`
`12
`
`11a
`
`13
`
`12
`
`14
`
`15
`
`13
`
`FI G.2 (b)
`
`=-O
`
`O--
`
`10/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 3 of 15
`
`6,100,594
`
`FI G.3(a)
`
`0@@@
`
`11
`
`10
`
`FIG.3(b)
`
`UDU
`DDOD C L
`
`aDDDD L
`DD
`DD
`pl DD
`l
`
`Dl
`Dl
`3
`
`14-)13 K12
`
`10
`
`11/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 4 of 15
`
`6,100,594
`
`7
`
`7
`
`7a
`
`FIG.4
`
`7a
`
`I
`
`12/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 5 of 15
`
`691009594
`
`FIG.5(a)
`I
`
`I
`
`6
`
`I
`
`IZ~
`
`FI G.5(b)
`
`FIG.5(c)
`
`FIG.5(d)
`
`2 6
`
`5
`7
`
`fFE $
`
`6)
`
`5
`
`7
`
`Fk E
`
`OE
`
`FIG.5(e)
`
`8
`
`7 2
`
`6
`
`-
`
`.ax.
`
`657
`FIG.5(f)2 6
`
`8
`
`6 7
`5 10
`2 61
`.
`
`FIG.5(g)
`
`--
`
`8
`7
`7
`10 5
`10 6
`
`13/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 6 of 15
`
`6,100,594
`
`FI G. 6 (a)
`
`m
`
`m
`
`14/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 7 of 15
`
`691009594
`
`FI G.7 (a)
`
`7
`
`7
`
`.17
`
`b
`
`13
`
`FIG.7(b)
`
`7
`
`13
`
`-
`
`7
`
`17a
`
`17b
`
`2
`
`13
`
`13
`
`17 a
`
`15/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 8of 15
`
`6,100,594
`
`F IG.8 (a)
`
`17b
`
`Fl
`
`G 8 (b)
`
`17b
`
`2
`
`13
`
`18
`
`18
`
`a
`
`16/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`U.S.PtentAug. 8, 2000
`
`Sheet 9of 156,059
`
`691009594
`
`FIG. 9(a)
`
`217b
`
`5 'd
`
`A
`
`18
`
`17a
`
`F IG. 9(b)
`
`18
`
`MM
`
`R2
`'d7b17b
`
`17a
`
`17/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 10 of 15
`
`691009594
`
`FIG.10
`
`8K
`
`21
`
`1
`
`22
`
`6
`
`(7
`
`4)
`
`9 12
`
`10
`
`24 10
`
`23 3
`
`j5
`
`18/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 11 of 15
`
`6,100,594
`
`a r ---
`
`n r--na
`
`I"
`
`-- -- --- -- -- I
`
`FIG.11(a)
`
`e%
`
`n
`
`FIG.11(b)
`1
`
`IZ
`
`FIG.11(c)
`
`FI G.11 (d)
`
`I-y
`
`FIG.11(e)
`
`23
`
`24
`
`21
`
`24
`2F
`
`23
`
`5'
`
`6
`22
`~~1
`
`5)
`
`24
`23
`21 22 6
`
`7
`
`23" 24
`
`5)
`21 6 228
`. 27
`
`F I G.1 1 (f )
`
`23 25
`
`21
`
`6 22 78
`r 59 h,9
`
`23
`24
`FIG.11(g) 21 6
`
`5
`
`10
`22 8
`
`24
`
`10
`
`19/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 12 of15
`
`6,100,594
`
`F IG.1 2(a)
`
`FIG.12 (b)
`
`20/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 13 of 15
`
`6,100,594
`
`FIG.13(a)
`
`43 51
`
`42
`
`48
`
`I
`
`51
`
`43
`
`52
`
`47
`
`46
`
`45
`
`50
`
`49
`
`53
`
`FIG.1 3 (b)
`
`64
`
`63
`
`67
`
`7O
`
`66
`
`61
`
`-LKJ
`
`L'
`
`69770
`
`L Zn
`
`68
`
`65
`
`63
`67
`62
`
`(
`21/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 14 of 15
`
`691009594
`
`FIG.14(a)
`
`89
`
`81
`
`/82
`
`/87
`
`88
`
`87a
`
`87a
`
`84 7
`
`=J
`
`86
`
`8 5
`
`83
`
`90
`
`FIG.14 (b)
`
`81
`
`89
`
`82
`
`87
`
`88
`
`89
`
`8 8 7 a
`
`90
`
`91
`
`83
`
`22/218
`
`MICRON 1014
`
`

`

`U.S. Patent
`
`Aug. 8, 2000
`
`Sheet 15 of 15
`
`691009594
`
`FIG.15
`
`92
`
`/ C
`
`82
`
`87
`
`/81
`
`87a
`
`85
`
`86 8483
`
`23/218
`
`MICRON 1014
`
`

`

`6,100,594
`
`1
`SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`FIELD OF THE INVENTION
`
`The present invention relates to a semiconductor device
`and a method of manufacturing the same, and more particu-
`larly relates to a semiconductor device having a structure
`substantially miniaturized to a chip size, i.e., a CSP (Chip
`Size Package) structure, and a method of manufacturing
`such a semiconductor device.
`
`5
`
`1o
`
`BACKGROUND OF THE INVENTION
`
`Miniaturization of a semiconductor device is in progress
`so as to achieve a high-density semiconductor device for use
`on a printed circuit board. Recently, a semiconductor device
`substantially miniaturized to a chip size has been developed.
`The structure of such a miniaturized semiconductor device
`is called a CSP structure. Japanese Publication of Unexam-
`ined Patent Application No. 121002/1997 (Tokukaihei
`9-121002) discloses a semiconductor device having the CSP 20
`structure shown in FIG. 13(a). This semiconductor device
`includes a semiconductor chip 42 disposed with its circuit
`formed surface facing up, and wires 43 for electrically
`connecting the semiconductor chip 42 to a wiring pattern 47.
`The above publication discloses another semiconductor
`device having the CSP structure shown in FIG. 13(b). This
`semiconductor device includes a semiconductor chip 64
`disposed with its circuit formed surface facing down, and a
`bump electrode 70 for electrically connecting the semicon-
`ductor chip 64 to a wiring pattern 66.
`In FIG. 13(a), 41 is a wiring component, 42 is a semi-
`conductor chip, 43 is a wire, 44 is a resin sealing member,
`45 is a throughhole, 46 is a substrate, 47 is a wiring pattern,
`48 is an insulating material, 49 is an external connection-use 3s
`terminal, 50 is an external connection area, 51 is an
`electrode, 52 is a window opening section, and 53 is an inner
`connection area. In FIG. 13(b), 61 is a throughhole, 62 is a
`wiring component, 63 is an electrode, 64 is a semiconductor
`chip, 65 is a resin sealing member, 66 is a wiring pattern, 67 40
`is an inner connection area, 68 is an external connection
`area, 69 is an external connection-use terminal, and 70 is a
`bump electrode.
`In some devices such as portable devices, a plurality of
`semiconductor chips are mounted in a package so as to 45
`increase the added value and capacity of memory, etc. For
`example, a multi-chip module is provided with a plurality of
`semiconductor chips arranged parallel to each other in a
`package. However, such an arrangement makes it impos-
`sible to produce a package smaller than the total area of the so
`semiconductor chips to be mounted. In order to solve the
`problem, a stacked package including a plurality of semi-
`conductor chips laminated in a package to achieve a high
`packaging density is disclosed in Japanese Publication of
`Unexamined Patent Application No. 90486/1993 55
`(Tokukaihei 5-90486).
`Specifically, the semiconductor devices disclosed in the
`above publication are each packaged in ceramic packages
`and arranged in the following manner. In one of the semi-
`conductor devices, a pair of semiconductor chips are 60
`adhered to each other with their back surfaces where a
`circuit is not formed facing each other, and are mounted on
`another pair of semiconductor chips via metal bumps. In the
`other semiconductor device, a pair of semiconductor chips
`are adhered to each other with the circuit formed surface of 65
`one semiconductor chip facing the back surface of the other
`semiconductor chip.
`
`2
`The above-mentioned stacked package is a small, high-
`density semiconductor device. However, a semiconductor
`device smaller than such a stacked package has been
`required. For that reason, a semiconductor device having a
`CSP structure as well as a stacked package structure is
`required to be produced.
`In a semiconductor device having a CSP structure where
`the semiconductor chips are laminated, an adhesive agent
`(paste) potting method and a method using a thermo-
`compression sheet are utilized for bonding the semiconduc-
`tor chip to the substrate, and for bonding the laminated
`semiconductor chips to each other.
`In the potting method, if the amount of the adhesive agent
`is excessive, a large amount of adhesive agent spreads
`beyond the outer edge of the semiconductor chip. For
`example, as shown in FIG. 14(a), when bonding semicon-
`ductor chips 81 and 82 to each other with their back surfaces
`facing each other, an adhesive agent 87 between the semi-
`conductor chips 81 and 82 overflows. In addition, as shown
`in FIG. 15, in the step of wire-bonding the semiconductor
`chip 82 disposed on the top to an electrode section of a
`wiring layer 84 (before a sealing resin 89 and packaging-use
`external terminals 90 are formed), wiring on an insulating
`substrate 83 must be provided far from the side surfaces of
`the semiconductor chips 81 and 82 so as to keep
`the
`overflown adhesive agent 87a from coming into contact with
`a jig 92 of a wire bonder. Such an arrangement causes the
`package size to be increased in the end. Furthermore, as
`shown in FIG. 14(b), when bonding the back surface of the
`semiconductor chip 82 to the circuit formed surface of the
`semiconductor chip 81, the overflown adhesive agent 87a
`may stick to an electrode pad provided on the semiconductor
`chip 81.
`On the other hand, if the amount of the adhesive agent is
`too small, a gap is produced between the semiconductor
`chips 81 and 82. This gap cannot be filled with the sealing
`resin 89, thereby causing problems such as separation of the
`semiconductor chip 82 from the semiconductor chip 81.
`The method using a thermo-compression sheet requires
`the steps of placing members at the right locations.
`Specifically, a thermo-compression sheet having the same
`size as the semiconductor chip 82 must be placed accurately
`at a specific location on the semiconductor chip 81. In
`addition, the semiconductor chip 82 must be bonded to the
`thermo-compression sheet so as to be located exactly on the
`top of the thermo-compression sheet.
`In FIGS. 14(a) and 14(b), 85 is an insulating sheet, 86 is
`a metal bump, and 91 is an adhesive sheet.
`
`SUMMARY OF THE INVENTION
`An object of the present invention is to provide a further-
`miniaturized semiconductor device having a stacked pack-
`age structure as well as a CSP structure.
`In order to achieve the above object, a semiconductor
`device in accordance with the present invention has a
`stacked package structure and a chip size package structure
`and is characterized in including:
`an insulating substrate including a wiring layer having
`electrode sections;
`a first semiconductor chip having a first insulating adhe-
`sion layer adhered to its back surface where a circuit is
`not formed, the first semiconductor chip being mounted
`on the wiring layer through the first insulating adhesion
`layer; and
`a second semiconductor chip having a second insulating
`adhesion layer adhered to its back surface where a
`
`24/218
`
`MICRON 1014
`
`

`

`6,100,594
`
`3
`circuit is not formed, the second semiconductor chip
`being mounted on a circuit-formed front surface of the
`first semiconductor chip through the second insulating
`adhesion layer;
`each of the first and second semiconductor chips being 5
`wire-bonded to the electrode section with a wire, the
`first and second semiconductor chips and the wire
`being sealed with a resin.
`In the above structure, the first semiconductor chip and
`the second semiconductor chip are each wire-bonded to the 1o
`electrode section provided on the wiring layer with the
`wires, and the second insulating adhesion layer is used for
`affixing the second semiconductor chip to the first semicon-
`ductor chip. This structure eliminates the need for wire-
`bonding the first and second semiconductor chips to points 1s
`on the wiring layer, far from the side surfaces of the first and
`second semiconductor chips, considering a situation in
`which the excessively applied adhesive agent overflows the
`space between the first and second semiconductor chips.
`Therefore, a miniaturized, high-density semiconductor 20
`device can be realized.
`Furthermore, in the case of using a thermo-compression
`sheet, when mounting the first or second semiconductor chip
`at a desired location, accurate positioning is required twice,
`i.e., positioning the thermo-compression sheet, etc., and
`positioning the first or second semiconductor chip on the
`thermo-compression sheet. In contrast, the first and second
`insulating adhesion layers according to the present invention
`are in advance disposed on the back surfaces of the first and
`second semiconductor chips, respectively. Therefore, the
`first or second semiconductor chip can be mounted at a
`desired location by accurately positioning it once. It is thus
`possible to miniaturize the semiconductor device without
`complicating its manufacturing process.
`A semiconductor device in accordance with the present
`invention can be arranged to include:
`an insulating substrate including a wiring layer having
`electrode sections;
`a first semiconductor chip having a circuit formed on its
`front surface and an insulating adhesion layer adhered 40
`to its back surface;
`a metal bump, disposed between the first semiconductor
`chip and the wiring layer, for bump-bonding the front
`surface of the first semiconductor chip to the wiring
`layer so that the front surface faces the wiring layer; 45
`and
`a second semiconductor chip whose back surface where a
`circuit is not formed is mounted on the back surface of
`the first semiconductor chip through the insulating
`adhesion layer;
`the second semiconductor chip being wire-bonded to the
`electrode section of the wiring layer with a wire, the
`first and second semiconductor chips and the wire
`being sealed with a resin.
`In the above arrangement, the first semiconductor chip is 55
`connected to the wiring layer through the metal bump, the
`second semiconductor chip is wire-bonded to the electrode
`sections on the wiring layer with wires, and the back
`surfaces of the first and second semiconductor chips are
`adhered to each other by the insulating layer. This arrange- 60
`ment eliminates the need for wire-bonding the second semi-
`conductor chip to points on the wiring layer, far from the
`side surfaces of the first and second semiconductor chips,
`considering a situation in which the excessively applied
`adhesive agent overflows the space between the first and 65
`second semiconductor chips. Therefore, a miniaturized,
`high-density semiconductor device can be realized.
`
`so
`
`4
`In the case of using the thermo-compression sheet, when
`mounting the second semiconductor chip on the first semi-
`conductor chip, accurate positioning is required twice in a
`conventional manufacturing method, i.e., positioning the
`thermo-compression sheet on the first semiconductor chip,
`and positioning the second semiconductor chip on the
`thermo-compression sheet. However, the insulating adhe-
`sion layer according to the present invention are disposed on
`the back surface of the second semiconductor chip in
`advance. Therefore, the second semiconductor chip can be
`mounted at a desired location on the first semiconductor chip
`by accurately positioning it once. It is thus possible to
`miniaturize the semiconductor chip without complicating its
`manufacturing process.
`A method of manufacturing a semiconductor device in
`accordance with the present invention includes the steps of:
`(a) forming a first insulating adhesion layer on a back
`surface of a first wafer having a circuit formed on its
`front surface;
`(b) producing separate first semiconductor chips from the
`first wafer by dicing;
`(c) mounting the first semiconductor chip on a wiring
`layer with its back surface facing the wiring layer;
`(d) forming a second insulating adhesion layer on a back
`surface of a second wafer having a circuit formed on its
`front surface;
`(e) producing separate second semiconductor chips from
`the second wafer by dicing;
`(f) mounting the second semiconductor chip on the first
`semiconductor chip with its back surface facing the first
`semiconductor chip;
`(g) wire-bonding the first semiconductor chip to an elec-
`trode section of the wiring layer with a wire;
`(h) wire-bonding the second semiconductor chip to an
`electrode section of the wiring layer with a wire; and
`(i) sealing the first and semiconductor chips and the wires.
`With the above manufacturing method, since the first or
`second semiconductor chip has the first or second insulating
`adhesion layer adhered to its back surface in advance when
`being in the wafer state, the first or second semiconductor
`chip can be mounted at a desired location without the step
`of accurately positioning the first or second insulating adhe-
`sion layer on the first or second semiconductor chip. It is
`thus possible to simplify the process of manufacturing the
`semiconductor chip.
`Moreover, in the above manufacturing method, the adhe-
`sive agent does not overflow the space between the first and
`second semiconductor chips, the first and second semicon-
`ductor chips can be wire-bonded to the wiring layer at a
`location closer to the edges of the first and second semicon-
`ductor chips. It is thus possible to realize a miniaturized,
`high-density semiconductor device.
`A method of manufacturing a semiconductor device in
`accordance with the present invention including the steps of:
`(a) forming an insulating layer and a metal bump on a
`wiring layer;
`(b) mounting a first semiconductor chip on the wiring
`layer with its circuit-formed surface facing the wiring
`layer;
`(c) forming an insulating adhesion layer on a back surface
`of a wafer having a circuit formed on its front surface;
`(d) producing separate second semiconductor chips from
`the wafer by dicing;
`(e) mounting the second semiconductor chip on the first
`semiconductor chip with its back surface facing the first
`semiconductor chip;
`
`25/218
`
`MICRON 1014
`
`

`

`6,100,594
`
`5
`
`5
`(f) wire-bonding the second semiconductor chip to the
`wiring layer with a wire; and
`(g) sealing the first and second semiconductor chips and
`the wire.
`In this manufacturing method, like the above-mentioned
`method of the present invention, since the second semicon-
`ductor chip has the insulating adhesion layer adhered to its
`back surface in advance when being in the wafer state, the
`second semiconductor chip can be mounted at a desired
`location without the step of accurately positioning the insu- 10
`lating adhesion layer on the second semiconductor chip. It is
`thus possible to simplify the process of manufacturing the
`semiconductor chip.
`Furthermore, in the above manufacturing method, the
`adhesive agent does not overflow the space between the first 15
`and second semiconductor chips, the second semiconductor
`chip can be wire-bonded to the wiring layer at a location
`closer to the edges of the first and second semiconductor
`chips. It is thus possible to realize a miniaturized, high-
`density semiconductor device.
`For a fuller understanding of the nature and advantages of
`the invention, reference should be made to the ensuing
`detailed description taken in conjunction with the accom-
`panying drawings.
`
`20
`
`6
`FIGS. 11(a) to 11(g) show one example of a process for
`manufacturing the semiconductor device.
`FIG. 12(a) is a perspective view showing that a second
`semiconductor chip in the semiconductor device in accor-
`dance with the first embodiment or the second embodiment
`protrudes from a first semiconductor chip, and FIG. 12(b) is
`a perspective view showing that the second semiconductor
`chip is reinforced.
`FIG. 13(a) is a cross-sectional view showing a semicon-
`ductor device having a CSP structure manufactured by a
`conventional wire bonding method, and FIG. 13(b) is a
`cross-sectional view showing a semiconductor device hav-
`ing a CSP structure manufactured by a conventional face-
`down bonding method.
`FIG. 14(a) and FIG. 14(b) are cross-sectional views of
`conventional semiconductor devices having a stacked pack-
`age structure.
`FIG. 15 is a cross-sectional view of the semiconductor
`device shown in FIG. 14(a) during manufacturing.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Embodiment 1
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`25
`
`40
`
`FIG. 1 is a cross-sectional view of a semiconductor device
`in accordance with the first embodiment of the present
`invention.
`FIG. 2(a) is a plan view of a circuit board before being
`cut, and FIG. 2(b) is a partially enlarged view of the circuit
`board shown in FIG. 2(a).
`FIG. 3(a) is an explanatory view showing an arrangement
`of ball-like external connection-use terminals, and FIG. 3(b) 35
`is an explanatory view showing an arrangement of trapezoi-
`dal external connection-use terminals.
`FIG. 4 is an explanatory view showing how laminated
`semiconductor chips are each wire-bonded to the circuit
`board.
`FIGS. 5(a) to 5(g) show one example of a process for
`manufacturing the semiconductor device.
`FIG. 6(a) is a partially enlarged view of the circuit board
`including a wiring layer disposed on one surface of an
`insulating substrate, and FIG. 6(b) is a partially enlarged
`view of a circuit board including a wiring layer disposed on
`each surface of the insulating substrate.
`FIG. 7(a) is an explanatory view showing a wiring state
`when two laminated semiconductor chips are connected to so
`the same electrode section, and FIG. 7(b) is an explanatory
`view showing another state that the two laminated semicon-
`ductor chips are connected to the same electrode section.
`FIG. 8(a) is an explanatory view showing a wiring state
`that the two laminated semiconductor chips are connected to ss
`different electrode sections, and FIG. 8(b) is an explanatory
`view showing another wiring state that the two laminated
`semiconductor chips are connected to different electrode
`sections.
`FIG. 9(a) is an explanatory view showing one example of 60
`an arrangement of dummy pads formed on a first semicon-
`ductor chip, and FIG. 9(b) is an explanatory view showing
`another example of the arrangement of the dummy pads
`disposed on the first semiconductor chip.
`FIG. 10 is a cross-sectional view of a semiconductor 65
`device in accordance with the second embodiment of the
`present invention.
`
`The following descriptions will explain one embodiment
`of the present invention with reference to FIGS. 1 to 9.
`As shown in FIG. 1, in a semiconductor device according
`to this embodiment, a first semiconductor chip 1 and a
`second semiconductor chip 2 are laminated in this order on
`a circuit board 5 including an insulating substrate 3 and a
`wiring layer 4 mounted on the insulating substrate 3.
`Regarding the first semiconductor chip 1 and the second
`semiconductor chip 2, the surface (front surface) on which
`an element is formed is hereinafter referred to as a "circuit
`formed surface", and the surface opposite thereto is referred
`to as a "back surface".
`The semiconductor chip 1 is disposed with its back
`surface facing the insulating substrate 3. The second semi-
`conductor chip 2 is mounted on the circuit formed surface of
`the first semiconductor chip 1
`through a thermo-
`compression sheet (adhesion layer) 6 so that its back surface
`is adhered to the thermo-compression sheet 6.
`The semiconductor device in accordance with the present
`embodiment is arranged so that the second semiconductor
`chip 2 is mounted on the circuit formed surface of the first
`semiconductor chip 1. With this arrangement, the second
`semiconductor chip 2 on the top of the first semiconductor
`chip 1 does not influence (interfere with) electrode pads of
`the first semiconductor chip 1. The circuit formed surface of
`the first semiconductor chip 1 is in advance coated with an
`insulating-resin, etc. Namely, the coating is applied to the
`circuit formed surface of the first semiconductor chip 1 by
`a spin coating method, etc. when the first semiconductor
`chip 1 is in a wafer state before subjected to dicing. In this
`case, the coating material on the electrode pads (not shown)
`disposed on the circuit formed surface of the first semicon-
`ductor chip 1 is removed.
`The first semiconductor chip 1 and the second semicon-
`ductor chip 2 are each connected (wire-bonded) to electrode
`sections of the wiring layer 4 on the insulating substrate 3
`with wires 7.
`The first semiconductor chip 1, the second semiconductor
`chip 2 and the wires 7, arranged as above, are covered by a
`sealing resin 8.
`The insulating substrate 3 includes via holes 9 at the
`locations corresponding to below-described land sections 12
`
`26/218
`
`MICRON 1014
`
`

`

`6,100,594
`
`5
`
`1o
`
`20
`
`7
`constituting the wiring layer 4. Ball-like packaging-use
`external terminals 10 are connected in an area-array-like
`arrangement to the land sections 12 through the via holes 9
`from the side of the insulating substrate 3, on which side the
`first semiconductor chip 1 and the second semiconductor
`chip 2 are not formed.
`Next, the following descriptions will explain in further
`detail the above-mentioned members constituting the semi-
`conductor device in accordance with the present embodi-
`ment.
`FIG. 2(a) is a plan view of the circuit board 5 before being
`cut in the process of manufacturing the semiconductor
`device. As shown in FIG. 2(a), four guide holes 11 are
`formed in both side sections of the insulating substrate 3 (the
`upper part and the lower part of the insulating substrate 3 in 1s
`FIG. 2(a)) of the circuit board 5 before being cut. The guide
`holes 11a formed in one of the side section and the guide
`holes 11b formed in the other side secti