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`
`
`FILE HISTORY
`US 6,229,217
`
`6,229,217
`PATENT:
`INVENTORS: FUKUI YASUKI
`SOTA YOSHIKI
`MATSUNE YUJI
`NARAI ATSUYA
`
`TITLE:
`
`Semiconductor device and method of
`manufacturing the same
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
`
`US2000604079A
`
`27 JUN 2000
`08 MAY 2001
`
`COMPILED:
`
`21 OCT 2022
`
`2/204
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`

`-
`
`-
`
`--
`
`-..
`
`-..
`
`~-±-.---
`
`_________
`
`-ESP
`
`Fp'Y
`
`.4--PATENT NUMBER
`6229217
`
`62217aV II1
`
`Y :
`
`j
`
`I<
`
`.i," a
`
`-A
`
`ORIGINAL/
`
`CLASS
`
`SUBCLASS
`
`-77 7S 9_
`INTjERNATIONAL CLASSIFICATION
`ei/ i- A
`
`11 1. 4 . . t i'[ lll i 1" .
`
`'lt~ A,
`
`ISSUING CLASSIFICATION
`CROSS REFERENCE(S)
`SUBCLASS (ONE SUBCLASS PER BLOCK)
`
`CLASS
`
`4
`
`P10-2040
`12199
`
`_
`
`v
`
`-//
`
`L] Continued on issue Slip Inside File Jacket
`
`rn TERMINAL
`DISCLAIMER
`
`Sheets Drwg.
`
`DRAWINGS
`Figs. Drwg.
`
`Print Fig.
`
`CLAIMS ALLOWED
`Total Claims
`Print Claim for 0.0.
`
`(date)
`
`El The term of this patent
`subsequent to
`has been disclaimed.
`H2 The term of this patent shall
`not extend beyond the expiration date
`of U.S Patent. No.
`
`_
`
`_
`
`_-
`
`NOTICE OF ALLOWANCE MAILED
`
`(Assistant Examiner)
`
`(Date)
`
`e "
`
`&.
`
`SHEILA V. CFE
`IMARY EXA
`
`IER
`
`(primary Examiner)",
`
`Amount Due
`
`ate aid
`
`H The terminal __ months of
`this patent have been disclaimed.
`
`(lt
`
`(LglIs~t
`
`Em
`Exminer)
`
`(ak
`
`r
`
`ISSUE BATCHN NMBER
`
`WARNING:
`The Information disclosed herein may be restricted, Unauthorized disclosure may be prohibited by the United States Code Title 35, Sections 122, 181 and 368.
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`FILED WITH: [] DISK (CRF) H FICHE
`
`Form PTO-436A
`(Rev. 6/99)
`
`[] CD-ROM
`(Attached in pocket on right inside flop)
`
`ISSUE rit IN IILE
`
`(FACE)
`
`3/204
`
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`

`

`6,229,217
`
`Semiconductor device and method of manufacturing the same
`
`Transaction History
`Transaction Description
`Date
`06-27-2000 Information Disclosure Statement (IDS) Filed
`06-27-2000 Information Disclosure Statement (IDS) Filed
`06-27-2000 Preliminary Amendment
`06-27-2000 Initial Exam Team nn
`08-16-2000 Correspondence Address Change
`09-12-2000 Application Dispatched from OIPE
`10-04-2000 Case Docketed to Examiner in GAU
`12-04-2000 Mail Notice of Allowance
`12-04-2000 Notice of Allowance Data Verification Completed
`12-20-2000 Workflow - Drawings Finished
`12-20-2000 Workflow - Drawings Matched with File at Contractor
`12-20-2000 Workflow - Drawings Received at Contractor
`12-20-2000 Workflow - Drawings Sent to Contractor
`01-09-2001 Workflow - File Sent to Contractor
`02-23-2001 Miscellaneous Incoming Letter
`02-23-2001 Workflow - Informational Disclosure Statement - Finish
`02-23-2001 Workflow - Informational Disclosure Statement - Begin
`03-02-2001 Issue Fee Payment Verified
`03-29-2001 Workflow - Complete WF Records for Drawings
`04-01-2001 Application Is Considered Ready for Issue
`04-20-2001 Issue Notification Mailed
`05-08-2001 Recordation of Patent Grant Mailed
`02-05-2004 File Marked Lost
`04-14-2004 File Marked Found
`07-01-2004 Mail Examiner's Amendment
`06-05-2006 Correspondence Address Change
` 
`
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`V
`
`PATENT APPLICATION
`
`jcQ56 U.S. PTO
`
`09/604079
`0
`06/2/
`
`09604079
`
`..... BEST COPY
`
`p
`
`'cation
`
`papers.
`
`- INITIALS HL
`
`-
`
`Date Received
`(Incl. C. of M.)
`or
`Date Mailed
`
`/
`
`7
`
`'4
`
`/J
`
`CONTENTS
`Date Received
`(Incl. C. of M.)
`or
`Date Mailed
`
`-
`
`-.
`
`-
`
`42.
`
`43.
`
`44.
`
`45.
`
`46.
`47.
`/48.
`49.
`
`50.
`51.
`52.
`
`53.
`
`54.
`
`55.
`56.
`57.
`58.
`59.
`60.
`61.
`62.
`
`63.
`
`64.
`65.
`66.
`67.
`68.
`69.
`70.
`71.
`72.
`73.
`74.
`75.
`76.
`77.
`78.
`79.
`80.
`81.
`82.
`OUTSIDE)
`
`j-)
`
`7
`
`6
`,~<
`
`r&3-f2<
`
`(LEFT
`
`5/204
`
`MICRON 1013
`
`

`

`ISSUE SLIP STAPLE AREA (for additional cross references)'
`
`I
`
`.POSITION
`
`INITIALS
`
`ID NO.
`ID NO.
`
`~DATE
`, DATE
`
`'--'
`
`FEE DETERMINATION
`O.I.P.E. CLASSIFIER
`FORMALITY REVIEW
`RESPONSE FORMA LITY REVIEW
`
`_____________________
`
`2,\\bEW
`
`_____
`
`____..-
`
`___
`
`Claim
`
`10 ~
`
`97
`
`9
`
`12
`13
`I' 14
`
`15
`f 16
`
`178
`
`22
`
`25
`26
`
`28
`29
`
`37
`32-1
`
`34
`35
`4
`36
`
`39
`
`* 40
`
`49
`47
`48
`45
`
`INDEX OF CLAIMS
`N ................................. N on-elected
`......................... R ejected
`.......
`I .................................
`................................. A llow ed
`Interference
`A ................................. Appeal
`(Through numeral)... Canceled
`......... Objected
`0 ....... : .
`..... Restricted
`....
`...........................
`
`Claim
`
`Date
`
`-
`
`-
`
`Date
`
`0
`
`101
`102
`103
`104
`105
`106
`107
`108
`109
`110
`111
`112
`113
`114
`115
`116
`117
`118
`119
`120
`121
`122
`123
`
`124
`125
`126
`127
`128
`129
`130
`131.
`132
`13E
`13E
`
`137
`
`138
`139
`140
`141
`142
`143
`144
`145
`146
`147
`14E
`14
`11 5
`
`If more than 150 claims or 10 actions
`staple additional sheet here
`
`(LEFT INSIDE)
`
`6/204
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`

`SEARCHED
`
`Class
`
`Sub.
`
`Date
`
`717
`
`Exmr.
`2p&-
`
`SEARCH NOTES
`(INCLUDING SEARCH STRATEGY)
`
`Date
`
`Exmr.
`
`'pi'
`
`/,Oq
`
`//0
`/67
`
`INTERFERENCE SEARCHED
`Class
`Sub.
`Date
`Exmr.
`25-?
`227
`1
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`

`(12) United States Patent
`Fukui et al.
`
`USOO6229217B1
`(10) Patent No.:
`US 6,229,217 B1
`(45) Date of Patent:
`May 8, 2001
`
`(54) SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`(75) Inventors: Yasuki Fukui, Tenri; Yoshiki Sota,
`Nara; Yuji Matsune, Tenri; Atsuya
`Narai, Yamatokoriyama, all of (JP)
`(73) Assignee: Sharp Kabushiki Kaisha, Osaka (JP)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/604,079
`(22) Filed:
`Jun. 27, 2000
`Related U.S. Application Data
`
`63) Conti
`f application No. 09/223.272, filed D
`Zf Z, illed On Lec.
`Ontinuation of application NO.
`30, 1998, now Pat. No. 6,100,594.
`Foreign Application Priority Data
`(30)
`Jan. 14, 1998 (JP) ..................................................... 10-5221
`51) Int. Cl."
`H01L23/48
`5
`1)
`Int. Cl. .............................
`; H01L 23/52
`(52) U.S. Cl. ........................... 257/777; 257/685; 257/686
`(58) Field of Search ..................................... 257/777, 685,
`257/686, 723, 724, 778; 438/108, 109,
`110, 107
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`6,077,724 * 6/2000 Chen.
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`5-90486
`9-1210O2
`
`4/1993 (JP).
`5/1997 (JP).
`
`* cited by examiner
`
`Primary Examiner. Sheila V. Clark
`(74) Attorney, Agent, or Firm Nixon & Vanderhye, P.C.
`(57)
`ABSTRACT
`
`A first Semiconductor chip is produced by affixing a thermo
`compression sheet to the back Surface of a wafer having a
`circuit formed on its front Surface. The first semiconductor
`chip is mounted on a circuit board including an insulating
`Substrate and a wiring layer provided on the insulating
`Substrate So that the back Surface of the first Semiconductor
`chip faces the circuit board. A Second Semiconductor chip
`produced in the same manner as the first Semiconductor chip
`is mounted on the first Semiconductor chip with its back
`Surface facing the first Semiconductor chip. Each of the first
`and Second Semiconductor chips is wire-bonded to the
`wiring layer with a wire. The first and Second Semiconductor
`chipS and the wire are Sealed with a Sealing resin. The wiring
`layer is connected to external connection terminals through
`via holes provided in the insulating Substrate.
`
`33 Claims, 15 Drawing Sheets
`
`1111111111111111111111 Hill Hill 11111111111111111111111111111111111111111111 IN lill IN
`
`8 27
`
`22
`
`6
`
`7
`
`4)
`
`10
`
`m
`
`/
`8/204
`
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 1 of 15
`
`US 6,229,217 B1
`
`
`
`FIG.1
`
`61
`
`2
`
`7
`
`mmm 1
`
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`U.S. Patent
`
`May 8, 2001
`
`Sheet 2 of 15
`
`US 6,229,217 B1
`
`FIG. 2 (a)
`
`11b
`
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`OOOOO OOOOO
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`
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`15
`
`FIG. 2 (b)
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`10/204
`
`MICRON 1013
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`

`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 3 of 15
`
`US 6,229,217 B1
`
`FIG.3(a)
`
`
`
`C C C C C C3
`C. C C C C C C3
`
`Alm
`W
`
`63h 6n
`qQF %g 0 0 a 0
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`
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`
`1
`
`10
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`11/204
`
`MICRON 1013
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`

`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 4 of 15
`
`US 6,229,217 B1
`
`FIG. A.
`
`v2
`
`17
`
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 5 of 15
`
`US 6,229,217 B1
`
`FIG.5(b)
`
`FIG.5(c)
`
`FIG.5(d)
`
`FIG. 5 (e)
`
`i
`
`2
`
`i
`
`6
`
`5
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`
`13/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 6 of 15
`
`US 6,229,217 B1
`
`FIG.6 (a)
`
`
`
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`
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`14/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 7 of 15
`
`US 6,229,217 B1
`
`FIG.7(a)
`
`
`
`7
`
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`
`FIG. 7(b)
`
`113
`
`7
`
`17b
`
`15/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 8 of 15
`
`US 6,229,217 B1
`
`
`
`F IG .8 (a)
`
`17b
`
`Fl
`
`17b
`
`2
`
`13
`
`18
`
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`
`16/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 9 of 15
`
`US 6,229,217 B1
`
`FIG. 9 (a)
`
`18
`
`17a
`
`FIG.9(b)
`
`
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`
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`
`17/204
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`

`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 10 Of 15
`
`US 6,229,217 B1
`
`21
`
`22
`
`6
`
`7
`
`FIG.1O
`
`
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`
`8
`
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`
`18/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 11 of 15
`
`US 6,229,217 B1
`
`FIG.11(a)
`FIG.11(b)
`
`
`
`23
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`s
`g
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`7
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`19/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 12 Of 15
`
`US 6,229,217 B1
`
`FIG.12 (a)
`
`FIG.12 (b)
`
`
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`
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`19
`
`20/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 13 of 15
`
`US 6,229,217 B1
`
`FIG. 13(a)
`
`
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`21/204
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`

`U.S. Patent
`
`May 8, 2001
`
`Sheet 14 of 15
`
`US 6,229,217 B1
`
`FIG.14 (a)
`
`a
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`22/204
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`U.S. Patent
`
`May 8, 2001
`
`Sheet 15 of 15
`
`US 6,229,217 B1
`
`FIG.15
`
`
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`US 6,229,217 B1
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`1
`SEMCONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`This is a continuation of application Ser. No. 09/223,272,
`filed Dec. 30, 1998, now U.S. Pat. No. 6,100,594, the entire
`content of which is hereby incorporated by reference in this
`application.
`
`FIELD OF THE INVENTION
`The present invention relates to a Semiconductor device
`and a method of manufacturing the Same, and more particu
`larly relates to a Semiconductor device having a structure
`Substantially miniaturized to a chip size, i.e., a CSP (Chip
`Size Package) structure, and a method of manufacturing
`Such a Semiconductor device.
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`another pair of Semiconductor chips via metal bumps. In the
`other Semiconductor device, a pair of Semiconductor chips
`are adhered to each other with the circuit formed Surface of
`one Semiconductor chip facing the back Surface of the other
`Semiconductor chip.
`The above-mentioned Stacked package is a Small, high
`density Semiconductor device. However, a Semiconductor
`device Smaller than Such a Stacked package has been
`required. For that reason, a Semiconductor device having a
`CSP structure as well as a Stacked package Structure is
`required to be produced.
`In a semiconductor device having a CSP structure where
`the Semiconductor chips are laminated, an adhesive agent
`(paste) potting method and a method using a thermo
`compression sheet are utilized for bonding the Semiconduc
`tor chip to the Substrate, and for bonding the laminated
`Semiconductor chips to each other.
`In the potting method, if the amount of the adhesive agent
`is excessive, a large amount of adhesive agent spreads
`beyond the Outer edge of the Semiconductor chip. For
`example, as shown in FIG. 14(a), when bonding Semicon
`ductor chips 81 and 82 to each other with their back surfaces
`facing each other, an adhesive agent 87 between the Semi
`conductor chips 81 and 82 overflows. In addition, as shown
`in FIG. 15, in the step of wire-bonding the semiconductor
`chip 82 disposed on the top to an electrode Section of a
`wiring layer 84 (before a Sealing resin 89 and packaging-use
`external terminals 90 are formed), wiring on an insulating
`substrate 83 must be provided far from the side surfaces of
`the semiconductor chips 81 and 82 so as to keep the
`overflown adhesive agent 87a from coming into contact with
`a jig 92 of a wire bonder. Such an arrangement causes the
`package size to be increased in the end. Furthermore, as
`shown in FIG. 14(b), when bonding the back surface of the
`semiconductor chip 82 to the circuit formed surface of the
`semiconductor chip 81, the overflown adhesive agent 87a
`may Stick to an electrode pad provided on the Semiconductor
`chip 81.
`On the other hand, if the amount of the adhesive agent is
`too Small, a gap is produced between the Semiconductor
`chips 81 and 82. This gap cannot be filled with the sealing
`resin 89, thereby causing problems Such as Separation of the
`semiconductor chip 82 from the semiconductor chip 81.
`The method using a thermo-compression sheet requires
`the Steps of placing members at the right locations.
`Specifically, a thermo-compression sheet having the same
`Size as the Semiconductor chip 82 must be placed accurately
`at a specific location on the Semiconductor chip 81. In
`addition, the semiconductor chip 82 must be bonded to the
`thermo-compression sheet So as to be located exactly on the
`top of the thermo-compression sheet.
`In FIGS. 14(a) and 14(b), 85 is an insulating sheet, 86 is
`a metal bump, and 91 is an adhesive sheet.
`SUMMARY OF THE INVENTION
`An object of the present invention is to provide a further
`miniaturized Semiconductor device having a Stacked pack
`age Structure as well as a CSP structure.
`In order to achieve the above object, a Semiconductor
`device in accordance with the present invention has a
`Stacked package structure and a chip size package Structure
`and is characterized in including:
`an insulating Substrate including a wiring layer having
`electrode Sections,
`a first Semiconductor chip having a first insulating adhe
`Sion layer adhered to its back Surface where a circuit is
`
`BACKGROUND OF THE INVENTION
`Miniaturization of a Semiconductor device is in progreSS
`So as to achieve a high-density Semiconductor device for use
`on a printed circuit board. Recently, a Semiconductor device
`Substantially miniaturized to a chip size has been developed.
`The Structure of Such a miniaturized Semiconductor device
`is called a CSP structure. Japanese Publication of Unexam
`ined Patent Application No. 121002/1997 (Tokukaihei
`25
`9-121002) discloses a semiconductor device having the CSP
`structure shown in FIG. 13(a). This semiconductor device
`includes a Semiconductor chip 42 disposed with its circuit
`formed Surface facing up, and wires 43 for electrically
`connecting the Semiconductor chip 42 to a wiring pattern 47.
`The above publication discloses another Semiconductor
`device having the CSP structure shown in FIG. 13(b). This
`Semiconductor device includes a Semiconductor chip 64
`disposed with its circuit formed Surface facing down, and a
`bump electrode 70 for electrically connecting the semicon
`ductor chip 64 to a wiring pattern 66.
`In FIG. 13(a), 41 is a wiring component, 42 is a semi
`conductor chip, 43 is a wire, 44 is a resin Sealing member,
`45 is a throughhole, 46 is a substrate, 47 is a wiring pattern,
`48 is an insulating material, 49 is an external connection-use
`terminal, 50 is an external connection area, 51 is an
`electrode, 52 is a window opening Section, and 53 is an inner
`connection area. In FIG. 13(b), 61 is a throughhole, 62 is a
`wiring component, 63 is an electrode, 64 is a Semiconductor
`chip, 65 is a resin Sealing member, 66 is a wiring pattern, 67
`is an inner connection area, 68 is an external connection
`area, 69 is an external connection-use terminal, and 70 is a
`bump electrode.
`In Some devices Such as portable devices, a plurality of
`Semiconductor chips are mounted in a package So as to
`increase the added value and capacity of memory, etc. For
`example, a multi-chip module is provided with a plurality of
`Semiconductor chips arranged parallel to each other in a
`package. However, Such an arrangement makes it impos
`Sible to produce a package Smaller than the total area of the
`Semiconductor chips to be mounted. In order to Solve the
`problem, a Stacked package including a plurality of Semi
`conductor chipS laminated in a package to achieve a high
`packaging density is disclosed in Japanese Publication of
`Unexamined Patent Application No. 90486/1993
`(Tokukaihei 5-90486).
`Specifically, the Semiconductor devices disclosed in the
`above publication are each packaged in ceramic packages
`and arranged in the following manner. In one of the Semi
`conductor devices, a pair of Semiconductor chips are
`adhered to each other with their back Surfaces where a
`circuit is not formed facing each other, and are mounted on
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`not formed, the first Semiconductor chip being mounted
`on the wiring layer through the first insulating adhesion
`layer; and
`a Second Semiconductor chip having a Second insulating
`adhesion layer adhered to its back Surface where a
`circuit is not formed, the Second Semiconductor chip
`being mounted on a circuit-formed front Surface of the
`first Semiconductor chip through the Second insulating
`adhesion layer;
`each of the first and Second Semiconductor chips being
`wire-bonded to the electrode section with a wire, the
`first and Second Semiconductor chips and the wire
`being Sealed with a resin.
`In the above Structure, the first Semiconductor chip and
`the Second Semiconductor chip are each wire-bonded to the
`electrode Section provided on the wiring layer with the
`wires, and the Second insulating adhesion layer is used for
`affixing the Second Semiconductor chip to the first Semicon
`ductor chip. This structure eliminates the need for wire
`bonding the first and Second Semiconductor chips to points
`on the wiring layer, far from the Side Surfaces of the first and
`Second Semiconductor chips, considering a situation in
`which the excessively applied adhesive agent overflows the
`Space between the first and Second Semiconductor chips.
`Therefore, a miniaturized, high-density Semiconductor
`device can be realized.
`Furthermore, in the case of using a thermo-compression
`sheet, when mounting the first or Second Semiconductor chip
`at a desired location, accurate positioning is required twice,
`i.e., positioning the thermo-compression sheet, etc., and
`positioning the first or Second Semiconductor chip on the
`thermo-compression sheet. In contrast, the first and Second
`insulating adhesion layers according to the present invention
`are in advance disposed on the back Surfaces of the first and
`Second Semiconductor chips, respectively. Therefore, the
`first or Second Semiconductor chip can be mounted at a
`desired location by accurately positioning it once. It is thus
`possible to miniaturize the Semiconductor device without
`complicating its manufacturing process.
`A Semiconductor device in accordance with the present
`invention can be arranged to include:
`an insulating Substrate including a wiring layer having
`electrode Sections,
`a first Semiconductor chip having a circuit formed on its
`front Surface and an insulating adhesion layer adhered
`to its back Surface;
`a metal bump, disposed between the first Semiconductor
`chip and the wiring layer, for bump-bonding the front
`Surface of the first Semiconductor chip to the wiring
`layer So that the front Surface faces the wiring layer;
`and
`a Second Semiconductor chip whose back Surface where a
`circuit is not formed is mounted on the back Surface of
`the first Semiconductor chip through the insulating
`adhesion layer;
`the Second Semiconductor chip being wire-bonded to the
`electrode Section of the wiring layer with a wire, the
`first and Second Semiconductor chips and the wire
`being Sealed with a resin.
`In the above arrangement, the first Semiconductor chip is
`connected to the wiring layer through the metal bump, the
`Second Semiconductor chip is wire-bonded to the electrode
`Sections on the wiring layer with wires, and the back
`Surfaces of the first and Second Semiconductor chips are
`adhered to each other by the insulating layer. This arrange
`ment eliminates the need for wire-bonding the Second Semi
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`conductor chip to points on the wiring layer, far from the
`Side Surfaces of the first and Second Semiconductor chips,
`considering a situation in which the excessively applied
`adhesive agent overflows the Space between the first and
`Second Semiconductor chips. Therefore, a miniaturized,
`high-density Semiconductor device can be realized.
`In the case of using the thermo-compression sheet, when
`mounting the Second Semiconductor chip on the first Semi
`conductor chip, accurate positioning is required twice in a
`conventional manufacturing method, i.e., positioning the
`thermo-compression sheet on the first Semiconductor chip,
`and positioning the Second Semiconductor chip on the
`thermo-compression sheet. However, the insulating adhe
`Sion layer according to the present invention are disposed on
`the back Surface of the Second Semiconductor chip in
`advance. Therefore, the Second Semiconductor chip can be
`mounted at a desired location on the first Semiconductor chip
`by accurately positioning it once. It is thus possible to
`miniaturize the Semiconductor chip without complicating its
`manufacturing process.
`A method of manufacturing a Semiconductor device in
`accordance with the present invention includes the Steps of:
`(a) forming a first insulating adhesion layer on a back
`Surface of a first wafer having a circuit formed on its
`front Surface;
`(b) producing separate first Semiconductor chips from the
`first wafer by dicing,
`(c) mounting the first Semiconductor chip on a wiring
`layer with its back Surface facing the wiring layer;
`(d) forming a second insulating adhesion layer on a back
`Surface of a Second wafer having a circuit formed on its
`front Surface;
`(e) producing separate Second semiconductor chips from
`the Second wafer by dicing;
`(f) mounting the Second Semiconductor chip on the first
`Semiconductor chip with its back Surface facing the first
`Semiconductor chip;
`(g) wire-bonding the first Semiconductor chip to an elec
`trode Section of the wiring layer with a wire,
`(h) wire-bonding the Second Semiconductor chip to an
`electrode Section of the wiring layer with a wire; and
`(i) Sealing the first and Semiconductor chips and the wires.
`With the above manufacturing method, since the first or
`Second Semiconductor chip has the first or Second insulating
`adhesion layer adhered to its back Surface in advance when
`being in the wafer State, the first or Second Semiconductor
`chip can be mounted at a desired location without the Step
`of accurately positioning the first or Second insulating adhe
`Sion layer on the first or Second Semiconductor chip. It is
`thus possible to simplify the process of manufacturing the
`Semiconductor chip.
`Moreover, in the above manufacturing method, the adhe
`Sive agent does not overflow the Space between the first and
`Second Semiconductor chips, the first and Second Semicon
`ductor chips can be wire-bonded to the wiring layer at a
`location closer to the edges of the first and Second Semicon
`ductor chips. It is thus possible to realize a miniaturized,
`high-density Semiconductor device.
`A method of manufacturing a Semiconductor device in
`accordance with the present invention including the Steps of:
`(a) forming an insulating layer and a metal bump on a
`wiring layer;
`(b) mounting a first Semiconductor chip on the wiring
`layer with its circuit-formed Surface facing the wiring
`layer;
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`(c) forming an insulating adhesion layer on a back Surface
`of a wafer having a circuit formed on its front Surface;
`(d) producing separate Second semiconductor chips from
`the wafer by dicing,
`(e) mounting the Second Semiconductor chip on the first
`Semiconductor chip with its back Surface facing the first
`Semiconductor chip;
`(f) wire-bonding the Second Semiconductor chip to the
`wiring layer with a wire; and
`(g) Sealing the first and Second semiconductor chips and
`the wire.
`In this manufacturing method, like the above-mentioned
`method of the present invention, Since the Second Semicon
`ductor chip has the insulating adhesion layer adhered to its
`back Surface in advance when being in the wafer State, the
`Second Semiconductor chip can be mounted at a desired
`location without the Step of accurately positioning the insu
`lating adhesion layer on the Second Semiconductor chip. It is
`thus possible to simplify the process of manufacturing the
`Semiconductor chip.
`Furthermore, in the above manufacturing method, the
`adhesive agent does not overflow the Space between the first
`and Second Semiconductor chips, the Second Semiconductor
`chip can be wire-bonded to the wiring layer at a location
`closer to the edges of the first and Second Semiconductor
`chips. It is thus possible to realize a miniaturized, high
`density Semiconductor device.
`For a fuller understanding of the nature and advantages of
`the invention, reference should be made to the ensuing
`detailed description taken in conjunction with the accom
`panying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a croSS-Sectional view of a Semiconductor device
`in accordance with the first embodiment of the present
`invention.
`FIG. 2(a) is a plan view of a circuit board before being
`cut, and FIG. 2(b) is a partially enlarged view of the circuit
`board shown in FIG. 2(a).
`FIG.3(a) is an explanatory view showing an arrangement
`of ball-like external connection-use terminals, and FIG.3(b)
`is an explanatory view showing an arrangement of trapezoi
`dal external connection-use terminals.
`FIG. 4 is an explanatory view showing how laminated
`Semiconductor chips are each wire-bonded to the circuit
`board.
`FIGS. 5(a) to 5(g) show one example of a process for
`manufacturing the Semiconductor device.
`FIG. 6(a) is a partially enlarged view of the circuit board
`including a wiring layer disposed on one Surface of an
`insulating Substrate, and FIG. 6(b) is a partially enlarged
`View of a circuit board including a wiring layer disposed on
`each Surface of the insulating Substrate.
`FIG. 7(a) is an explanatory view showing a wiring State
`when two laminated Semiconductor chips are connected to
`the same electrode Section, and FIG. 7(b) is an explanatory
`View showing another State that the two laminated Semicon
`ductor chips are connected to the Same electrode Section.
`FIG. 8(a) is an explanatory view showing a wiring State
`that the two laminated Semiconductor chips are connected to
`different electrode sections, and FIG. 8(b) is an explanatory
`View showing another wiring State that the two laminated
`Semiconductor chips are connected to different electrode
`Sections.
`FIG. 9(a) is an explanatory view showing one example of
`an arrangement of dummy pads formed on a first Semicon
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`ductor chip, and FIG. 9(b) is an explanatory view showing
`another example of the arrangement of the dummy pads
`disposed on the first Semiconductor chip.
`FIG. 10 is a cross-sectional view of a semiconductor
`device in accordance with the Second embodiment of the
`present invention.
`FIGS. 11(a) to 11(g) show one example of a process for
`manufacturing the Semiconductor device.
`FIG. 12(a) is a perspective view showing that a second
`Semiconductor chip in the Semiconductor device in accor
`dance with the first embodiment or the second embodiment
`protrudes from a first semiconductor chip, and FIG. 12(b) is
`a perspective view showing that the Second Semiconductor
`chip is reinforced.
`FIG. 13(a) is a cross-sectional view showing a semicon
`ductor device having a CSP structure manufactured by a
`conventional wire bonding method, and FIG. 13(b) is a
`croSS-Sectional view showing a Semiconductor device hav
`ing a CSP Structure manufactured by a conventional face
`down bonding method.
`FIGS. 14(a) and FIG. 14(b) are cross-sectional views of
`conventional Semiconductor devices having a Stacked pack
`age Structure.
`FIG. 15 is a cross-sectional view of the semiconductor
`device shown in FIG. 14(a) during manufacturing.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`Embodiment 1
`The following descriptions will explain one embodiment
`of the present invention with reference to FIGS. 1 to 9.
`AS shown in FIG. 1, in a Semiconductor device according
`to this embodiment, a first Semiconductor chip 1 and a
`Second Semiconductor chip 2 are laminated in this order on
`a circuit board 5 including an insulating Substrate 3 and a
`wiring layer 4 mounted on the insulating Substrate 3.
`Regarding the first Semiconductor chip 1 and the Second
`Semiconductor chip 2, the Surface (front Surface) on which
`an element is formed is hereinafter referred to as a “circuit
`formed Surface', and the Surface opposite thereto is referred
`to as a “back Surface'.
`The semiconductor chip 1 is disposed with its back
`Surface facing the insulating Substrate 3. The Second Semi
`conductor chip 2 is mounted on the circuit formed Surface of
`the first Semiconductor chip 1 through a thermo
`compression sheet (adhesion layer) 6 So that its back Surface
`is adhered to the thermo-compression sheet 6.
`The Semiconductor device in accordance with the present
`embodiment is arranged So that the Second Semiconductor
`chip 2 is mounted on the circuit formed surface of the first
`Semiconductor chip 1. With this arrangement, the Second
`Semiconductor chip 2 on the top of the first Semiconductor
`chip 1 does not influence (interfere with) electrode pads of
`the first semiconductor chip 1. The circuit formed surface of
`the first Semiconductor chip 1 is in advance coated with an
`insulating-resin, etc. Namely, the coating is applied to the
`circuit formed surface of the first semiconductor chip 1 by
`a spin coating method, etc. when the first Semiconductor
`chip 1 is in a wafer State before Subjected to dicing. In this
`case, the coating material on the electrode pads (not shown)
`disposed on the circuit formed Surface of the first Semicon
`ductor chip 1 is removed.
`The first Semiconductor chip 1 and the Second Semicon
`ductor chip 2 are each connected (wire-bonded) to electrode
`Sections of the wiring layer 4 on the insulating Substrate 3
`with wires 7.
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