File Histories
`The world’s leading IP decision makers
`turn to us for one reason. Trust.
`
`Good decisions require reliable intelligence. That’s why more
`IP decision makers rely on us.
`
`We empower companies to build and protect their valuable
`assets with services that span the full IP lifecycle. Our blend
`of global expertise, resources, and technology translates to
`results you can rely on with certainty. In any language, we’re
`the name you can trust.
`
`IP Services from Clarivate Analytics
`Patent search and analytics
`• Prior art search
`• Patent watch
`• Patent profiles
`
`Patent licensing
`• Patent-to-product mapping
`• Standards mapping
`• Licensing opportunity analysis
`• Patent acquisition analysis
`• Claims charting
`
`Patent preparation and prosecution
`• Patent drafting
`• Prosecution services
`
`IP analytics
`• Technology landscaping
`• Patent portfolio audit
`• Competitive portfolio assessment
`
`IP management
`• Data validation services
`• IP payments
`• IP docketing
`• IP management consulting
`• Paralegal services
`• Proofreading
`
`Translation services and file histories
`
`For more information, call us at +1-800-445-9760
`or email fhservice@clarivate.com
`
`Alexandria
`+1 800 445 9760 (US)
`+1 703 916 1500 (International)
`filehistories.clarivate.com
`
`IP 1702 300
`07.2017
`© 2017 Clarivate Analytics
`
`clarivate.com
`
`1/206
`
`MICRON 1012
`
`

`

`
`
`FILE HISTORY
`US 6,352,879
`
`6,352,879
`PATENT:
`INVENTORS: FUKUI YASUKI
`SOTA YOSHIKI
`MATSUNE YUJI
`NARAI ATSUYA
`
`TITLE:
`
`Semiconductor device and method of
`manufacturing the same
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
`
`US2000604081A
`
`27 JUN 2000
`05 MAR 2002
`
`COMPILED:
`
`29 JUL 2022
`
`2/206
`
`MICRON 1012
`
`

`

`U.S. UTILITY Patent Application
`
`SBCANNED'E-F
`C- A N I
`
`O_.A.
`
`M A R 0
`
`2
`
`U
`
`z 0
`
`CI,
`
`Co )
`
`1,
`
`0
`
`~
`
`C
`
`!fl
`
`y
`
`j
`
`i
`
`lyl i:: I::. S I...1 I-,
`
`r- :J N" i. I
`c: -1:-. 1:::1
`S ..4. ro j. e.:,
`c:, r-, cl i.,-i
`
`rf) 1:,:! +.- V-1 k 1 1" rn iA l"'I I.,,[ -f at :::: -1::.
`1-.11 :i. r.I
`
`Si;.trflp,
`
`PTO-2040
`12/99
`
`ORIGINAL
`
`!. .
`
`ISSUING CLASSIFICATION
`ft"....CROSS REFERENCE(S)
`...
`
`,!
`
`'
`
`CLASS
`
`SUBCLASS
`
`CLAS
`
`SUBCLASS (ONEUBCLASS PER BL
`
`INTERNATIONAL CLASSIFICATION,,
`
`"
`
`"_
`
`_
`
`1+ -0 1 .
`
`,( ........
`
`[- Continued on Issue Slip Inside File Jacket
`
`TERMINAL
`DISCLAIMER
`
`Sheets Drwg.
`
`DRAWINGS
`Figs. Drwg.
`
`PrintFig.
`
`CLAIMS ALLOWED
`Print Claim for O.G.
`Total Claims
`
`(date)
`
`] The term of this patent
`subsequent to
`_
`,has been disclaimed.
`,,[ The term of this patent shall
`not extend beyond the expiration date
`of, U.S Patent. No.
`
`L ,c-%L
`,"./
`(Assistant Examilner)
`
`6
`
`(0
`
`'
`MATTHEW SMITH
`SUPERVISORY PATENT EXAMINER
`TECHNOLOGY CENTER 2800
`
`NOTICE OF ALLOWANCE MAILED
`
`S, UE FEE
`
`'
`
`. , x
`
`(Primary Examiner)
`
`-
`
`*te
`
`H The terminal
`rponths of
`this patent have been disclaimed.
`
`-9
`(Legal Instruments Examiner)
`
`m
`A
`i<ISSUE
`
`BATCH NUMBER
`
`,
`
`"
`
`/
`
`/
`' (Date)
`
`'WARNING:
`The iniolration disclosed herein may be restricted, Unauthorized disclosure may be prohibited by the United States Code Titlq.p 95Z tios 122, 181 and 368.
`Possession outbids t,,, U.S. Patent & Trademark Office is restricted to authorized employees and contractors only,
`[] DISK (CRF) [] FICHE
`[ CD-ROM
`FILED WITH:
`(Attached In pocket on right Inside flap)
`
`Form PTO-436A
`(Rev. 6/99)
`
`Isue Fee
`
`Ir-A nnrm
`
`3/206
`
`MICRON 1012
`
`

`

`6,352,879
`Semiconductor device and method of manufacturing the same
`Transaction History
`Transaction Description
`Date
`06-27-2000 Preliminary Amendment
`06-27-2000
`Information Disclosure Statement (IDS) Filed
`06-27-2000
`Information Disclosure Statement (IDS) Filed
`06-27-2000
`Initial Exam Team nn
`08-15-2000 Correspondence Address Change
`08-17-2000 Application Dispatched from OIPE
`09-14-2000 Case Docketed to Examiner in GAU
`01-27-2001 Case Docketed to Examiner in GAU
`01-29-2001 Non-Final Rejection
`02-01-2001 Mail Non-Final Rejection
`05-01-2001 Response after Non-Final Action
`05-05-2001 Date Forwarded to Examiner
`07-17-2001 Mail Notice of Allowance
`07-17-2001 Notice of Allowance Data Verification Completed
`09-28-2001
`Issue Fee Payment Verified
`09-28-2001
`Issue Fee Payment Received
`10-17-2001 Mail Examiner's Amendment
`10-24-2001 Workflow - File Sent to Contractor
`11-20-2001 Receipt into Pubs
`12-21-2001 Workflow - Drawings Finished
`12-21-2001 Workflow - Drawings Matched with File at Contractor
`12-21-2001 Workflow - Drawings Received at Contractor
`12-21-2001 Workflow - Drawings Sent to Contractor
`01-24-2002 Application Is Considered Ready for Issue
`01-25-2002 Receipt into Pubs
`02-14-2002
`Issue Notification Mailed
`03-05-2002 Recordation of Patent Grant Mailed
`03-05-2002 Patent Issue Date Used in PTA Calculation
`
` 
`
`4/206
`
`MICRON 1012
`
`

`

`PATENT APPLICATI
`
`)N
`ON
`
`- O9/6O ,OB1
`jc856 US. PTO
`
`09604081
`
`CONTENTS
`Date Received
`(Incl. C. of M.)
`or
`Date Mailed
`
`JUL 100 3 4,
`.
`INITIALS
`
`Date Received
`(Incl. C. of M.)
`or
`Date Malledl
`
`~47.
`
`4. <. 48.
`
`rf
`
`VI/ 10.-11.-
`
`12.
`
`13.
`
`14.
`
`15.
`
`16.
`
`17.
`
`18.
`19.
`
`20.
`
`21.
`
`22.
`23.
`
`24.
`
`25.
`
`26.
`
`27.
`
`28.
`
`29.
`
`30.
`
`31.
`
`32.
`
`33.
`
`34.
`
`35.
`36.
`37.
`
`38.
`
`39.
`
`40.
`
`41.
`
`_64.
`
`49.
`
`51.
`
`52.
`
`53.
`
`54.
`
`55.
`
`56.
`
`57.
`
`58.
`
`59.
`
`60.
`
`61.
`
`62.
`
`63.
`
`65.
`
`66.
`
`67.
`
`68.
`
`69.
`
`70.
`
`71.
`
`72.
`
`73.
`
`74.
`
`75.
`
`76.
`
`78.
`79.
`
`80.
`
`81.
`
`82.
`
`_77.
`
`(LEFT OUTSIDE)
`
`5/206
`
`MICRON 1012
`
`

`

`ISSUE SLIP STAPLE AREA (for additional cross references)
`
`POSITION
`
`INITIALS
`
`ID NO.
`
`)DATE
`
`FEE DETERMINATION(
`O.I.P.E. CLASSIFIER
`FORMALITY REVIEW
`RESPONSE FORMALITY REVIEW
`
`_/____,,
`
`_ .
`
`/
`
`,
`
`INDEX OF CLAIMS
`N ................................. Non-elected
`................................. Rejected
`. . .
`I ................................
`Interference
`................................. A llow ed
`A .............
`Appeal
`(Through numeral)... Canceled
`0 ................................. Objected
`........ Restricted
`.... ... ........
`
`-
`
`Claim
`
`76
`
`Date
`
`Claim
`
`ir-
`
`Date
`
`Claim
`
`Date
`
`if
`
`101
`1021
`103
`104
`105
`106
`
`110
`111
`
`112
`113
`114
`115
`116
`117
`118
`119
`120
`121
`122
`123
`124
`125
`126
`127
`128
`129
`130
`131
`132
`133
`134
`135
`
`137
`138
`
`139 __
`140
`141
`142
`114 1~
`
`114
`145
`
`14E
`14-
`
`14E
`150
`
`1
`
`1
`
`_
`
`_
`
`-
`
`-
`
`-
`
`-
`
`-
`
`51
`52
`53
`
`54
`55
`56
`57
`58
`59
`60
`61
`
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`7B
`79
`80
`81
`
`82
`83
`84
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`loc
`
`11
`
`I
`
`-
`
`'1
`
`i
`
`2 2 2 2
`
`2
`
`--4-
`
`4 4
`
`5
`382
`
`_6
`
`q 38
`
`47
`
`48
`
`49
`
`46,
`
`101
`
`If more than 150 claims or 10 actions
`
`staple additional sheet here
`
`(LEFT INSIDE)
`
`6/206
`
`MICRON 1012
`
`

`

`SEARCHED
`
`SEARCH NOTES
`(INCLUMIGtEARCH STRATEGY)
`
`Date
`
`C/, s/d,
`
`Exmr.
`VIAL
`
`-fee
`
`Date
`
`Class
`
`'U,
`
`Sub.
`
`/10
`
`p/vlv
`
`))
`
`I
`
`Exmr.
`(Au
`
`-9-
`
`'25i
`
`."7-
`
`(/
`
`Lw a1/0/
`+ /2' CI
`
`lob
`
`"frd.-
`73
`
`1113
`
`60,i.
`
`43 %j
`
`INTERFERENCE SEARCHED
`Exy;r.
`Date
`Sub.
`Class
`
`/
`
`(RIGHT OUTSIDE)
`
`I
`
`I
`
`7/206
`
`MICRON 1012
`
`

`

`(12) United States Patent
`Fukui et al.
`
`US006352879B]
`US 6,352,879 Bi
`Mar. 5, 2002
`
`(0o) Patent No.:
`(45) Date of Patent:
`
`(54) SEMICONDUCTOR DEVICE AND METHOD
`O MANUFACTURING THE SAME
`
`(75)
`
`inventors: Yasuki Fukui, Itnri; Yoshild Sot,
`Nara; Vuli Matsune, Tend; Atsuya
`Naai, Yamatokoriyama, all of (JP)
`
`(73) Assignee: Sharp Kabushiki Kaisha, Osaka OP)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) AppL No.: 09/604,081
`Jun. 27, 2000
`
`(22) Filed:
`
`Related U.S. Application Data
`
`(62) Division of application No. 0/223272, filed on Dec. 30,
`1998, now Pat. No. 6.100,594.
`Foreign Application Priority Data
`
`(30)
`
`6/1996 Godwalicar et al.
`5,527,740 A
`438/107
`5,766.986 A
`6/1998 Weber eta! .......... 48/24
`5.898.22) A
`4/1999 Ball ................
`257723
`7/1999 [ujirmoto eal........438/113
`5$3O,599 A
`7/20M Fjelsad .............
`48/t27
`6,093584 A
`6,130,483 A * 10/200() Shizuk, ct al .......... 257778
`438/110
`6,133,067 A * 10/2000 Jeng of al...........
`6,133.637 A * 10/200(b
`ikila el al
`257777
`...........
`6,:57,080 A * 122(100 Tamai el al.........
`257738
`
`FOREIGN PATENT DOCUMENTS
`
`5 90486 A
`JP
`9-1210(12 A
`JP
`* cited by examiner
`
`4/1993
`S/1097
`
`Printarv Exwiner-Matthew Smith
`A.istant Examineru-Cbong A Iuu
`(74) Attorney, Agent, or Firtn-Nixon & Vanderhye PC.
`
`(57)
`
`ABSTRACT
`
`A first semiconductor chip is produced by affixing a thermo-
`compression sheet to the back surface of a wafr having a
`circuit Formcd on its front surface. The first semiconductor
`)...............................
`10-5221
`chip is mounted on a circuit board including an insulating
`substrate and a wiring layer provided on the insulating
`substrate so that the back surface of the firsl semicnnaducior
`chip faces the circuit board. A second semiconductor chip
`produced in the same manner as the first semiconductor chip
`is mounted on the first semiconductor chip with its back
`surface facing the first semiconductor chip. Each of the first
`and second semiconductor chips is wire-lrnded
`to the
`wiring layer with a wire. The frst and second semiconductor
`chips and the wire arc scaled with a sealing resin. The wiring
`layer is connected to external connection terminals through
`via holes provided in the insulaing substrate.
`
`(JP)
`Jan, 14. 1998
`(51)
`Int. CI? ......
`
`.....
`
`(52) U.S. C.
`
`...... H L 21/44; H01L 21/48;
`21/50
`l1l0
`........... 438/106; 438/107; 438/109;
`438/118; 438/127
`438/110. 107-109,
`(58) Field of Search ........ ....
`438/114, 118, 124, 458, 106; 257/777,
`738. 778
`
`(56)
`
`References Cited
`
`U.S. PAtENT DOCUMENTS
`l .-
`- 11/1994 Golwalkar of
`5,366,933 A
`4381107
`5.422435 A -
`6/1995 'faki
`t a.............. 174/52.4
`
`15 Claims, 15 Drawing Sheets
`
`12
`
`10
`
`8/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet I of 15
`
`US 6,352,879 B1
`
`FIG.1
`
`-5
`
`12
`
`10
`
`9/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 2 of 15
`
`US 6,352,879 B1
`
`FIG. 2 (a)
`
`0
`
`0
`
`0
`
`a
`
`-0000g =0000-
`N0000M
`.0002
`S0000: .
`20000
`=00001
`0001
`00000
`=00000
`0
`
`0
`
`=0000:
`
`-00000
`=-000-:
`0
`F0000 Q
`0000-0 9000-0
`E000
`00000
`QQ00
`q
`I1a
`
`0
`
`12
`
`FIG.2(b) w-Z
`m0
`
`0-0z
`
`10/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 3 of 15
`
`US 6,352,879 B1
`
`FIG.3(a)
`
`FIG.3(b)
`
`11/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 4 of 15
`
`US 6,352,879 B1
`
`FIG.4
`
`12/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 5 of 15
`
`US 6,352,879 B1
`
`FIG.5(a)
`
`FI G.5(b)
`rc.,
`
`2
`
`6 1
`
`FIG.5
`
`(C)
`
`65
`
`FIG.5(d)
`
`2 67
`
`FA
`
`FIG.5(9)
`
`13/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 6 of 15
`
`US 6,352,879 B1
`
`FIG.6 (a)
`
`FIG,6 (b)
`
`3
`
`A
`
`14/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 7 of 15
`
`US 6,352,879 BI
`
`FIG.7(a)
`
`FIG .7 (b)
`
`15/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 8 of 15
`
`US 6,352,879 B1
`
`FIG.8(a)
`
`17b
`
`FI G. 8 (b)
`
`16/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 9 of 15
`
`US 6,352,879 B1
`
`FIG.9 (a)
`
`2
`
`,"
`
`b
`
`FIG.9(b)
`
`17/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5,2002
`
`Sheet 10 of 15
`
`US 6,352,879 B1
`
`FIG.10
`
`18/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5, 2002
`
`Sheet 11 of 15
`
`US 6,352,879 B1
`
`FIG.1 1(a)
`
`FIG.A1 (b)
`
`FIG.11(c)
`
`23
`
`24
`4
`
`S
`
`r'-
`
`n
`
`nr
`
`21
`
`24
`
`23'
`
`5'
`
`22
`
`6
`
`I
`
`23 1/24
`
`S'
`
`23 24
`
`19/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5,2002
`
`Sheet 12 of 15
`
`US 6,352,879 B1
`
`FIG.12(a)
`
`FIG.12(b)
`
`20/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5,2002
`
`Sheet 13 of 15
`
`US 6,352,879 BI
`
`FIG. 13(a)
`
`FIG.13(b)
`
`52
`-41
`
`63
`
`I
`) Z;t
`
`67
`
`I f I
`"Z e ( -Zy 4;z-,e
`70 66
`61
`69
`
`70
`
`68
`
`65
`
`3
`67
`62
`
`21/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5,2002
`
`Sheet 14 of 15
`
`US 6,352,879 B1
`
`FIG.14 (a)
`
`908
`
`FIG.14 (b)
`
`22/206
`
`MICRON 1012
`
`

`

`U.S. Patent
`
`Mar. 5,2002
`
`Sheet 15 of 15
`
`US 6,352,879 BI
`
`FIG .15
`
`87/
`
`,81
`
`85
`
`86 8483
`
`23/206
`
`MICRON 1012
`
`

`

`US 6,352,879 B1
`
`SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`This is a divisional of application Scr. No 09/223,272,
`filed Dec. 30, 1998, the entire content of which is hereby 5
`incorporated by reference in this application now U.S. Pat.
`No. 6,100,594
`
`FIL 1) OF TIlE INVENTIOIN
`The present invention relates to a semiconductor device
`and a method of manufacturing the same, and more particu-
`larly relates io a semiconductor device having a structure
`substantially miniaturized to a chip size, iz., a CSP (Chip
`Size Package) structure, and a method of manufacturing
`such a semiconductor device
`
`BACKGROUND OF THE INVENTION
`Miniaturization of a semiconductor device is in progress
`so asto achieve a high-density semiconductor device for use
`on a printed circuit board. Recently, a semiconductor device 20
`substantially miniaturized to a chip size has been developed.
`The structure of such a miniaturized semiconductor device
`is called a CSP structure. Japanese Publication of Unexam-
`ined Patent Application No. 121002/1997 (Tokiukaihei
`9-121002) discloses a semiconductor device having the CSP 25
`structure shown in FIG. 13(a). This semiconductor device
`includes a semiconductor chip 42 disposed with its circuit
`formed surface facing up, and wires 43 for electrically
`con nectingthe semiconductorchip 42 to a wiring pattern47. 31
`The above publication discloses another semiconductor
`device having the CSP structure shown in FIG. 13(b). This
`semiconductor device includes a semiconductor chip 64
`disposed with its circuit formed surface facing down, and a
`bump electrode 70 for electrically connecting the semicon 35
`ductor chip 64 to a wiring pattern 66
`In FIG. 13(a), 41 is a wiring component, 42 is a semi-
`conductor chip, 43 is a wire, 44 is a resin sealing member,
`45 is a throughhole, 46 is a substrate, 47 is a wiring pattern,
`48 is an insulating material, 49 is an external connectionuse 40
`terminal, 50
`is an external connection area., 51
`is an
`electrode, 52 is a window opening section, and 53 is an inner
`connection area. In FIG. 13(b), 61 is a throughhole. 62 is a
`wiring component, 63 is an electrode, 64 is a semiconductor
`chip, 65 is a resin sealing member, 66 is a wiring pattern, 67
`Is an inner connection area, 68 is an external connection
`area, 69 is an external connection-use terminal, and 70 is a
`bump electrode.
`In some devices such as portable devices, a plurality of
`semiconductor chips are mounted in a package so as to so
`increase the added value and capacity of memory, etc. For
`example, a multi-chip module is provided with a plurality of
`semiconductor chips arranged parallel to each other in a
`package. However, such an arrangement makes it impos-
`sible to produce a package smaler than the total area of the ss
`semiconductor chips to be mounted. In order to solve the
`problem, a stacked package including a plurality of semi-
`conductor chips laminated in a package to achieve a high
`packaging density is disclosed in Japanese Publication of
`Unexamined Patent Application No. 90486/1993 60
`(okukaihei 5-9(486).
`Specifically, the semiconductor devices disclosed in the
`above publication are each packaged in ceramic packages
`and arranged in the following manner. In one of the semi
`conductor devices, a pair of semiconductor chips are 65
`adhered to each other with their back surfaces where a
`circuit is not formed facing each other, and are mounted on
`
`another pair of semiconductor chips via metal bumps. In the
`other semiconductor device, a pair of semiconductor chips
`are adhered to each other with the circuit formed surface of
`one semiconductor chip facing the back surface of the other
`semiconductor chip.
`The above-mentined stacked package is a small, high-
`density semiconductor device. However, a semiconductor
`device smaller
`than such a stacked package has been
`required. For that reason, a semiconductor device having a
`CSP structure as well as a stacked package siicture is
`required to be produced.
`In a semiconductor device having a CSP structure where
`the semiconductor chips are laminated, an adhesive agent
`(paste) potting method and a method using a thermo.
`compression sheet are utilized for bonding the semiconduc-
`tor chip to the substrate, and for bonding the laminated
`semiconductor chips to each other.
`In the potting method, if the amount of the adlhesive agent
`is excessive, a large amount of adhesive agent spreads
`beyond the outer edge of the semiconductor chip. For
`example, as shoiwn in FIG. 140a), when bonding semicon-
`ductor chips 81 and 82 to each other with their back surfaces
`facing each other, an adhesive agent 87 between the semi-
`conductor chips 81 and 82 overflows. In addition, as shown
`in FIG. 15, in the step of wire-bonding the semiconductor
`chip 82 disposed on the top to an electrode scction of a
`wiring layer 84 (before a sealing resin 89 and packaging use
`external terminals 90 are formed), wiring on an insulating
`substrate 83 must be provided far from the side surfaces of
`the semiconductor chips 81 and 82 so as to keep the
`overflown adhesive agent gSa from coming into contact with
`a jig 92 of a wire bonder. Such an arrangement causes the
`package size to be increased in the end. Furthermore, as
`shown in FIG. 14(b), when bonding the back surface of the
`semiconductor chip 82 to the circuit formed surface of the
`semiconductor chip 81, the overflown adhesive agent 87a
`may stick to an electrode pad providel on the semiconductor
`chip S1.
`On the other hand, if the amount of the adhesive agent is
`too small, a gap is produced between the semiconductor
`chips 81 and 82. This gap cannot be filled with the sealing
`resin 89, thereby causing problems such as separation of the
`semiconductor chip 82 from the semiconductor chip 81.
`The method using a thermocompression sheet requires
`the steps of placing members at
`the right locations.
`Specifically, a thermo-compression sheet having the same
`size as the semiconductor chip 82 must be placed accurately
`at a specific location an the semiconductor chip 81. In
`addition, the semiconductor chip 82 must be bonded to the
`therono-compression sheet so as to be located exactly on the
`top of the thermo-compre.sion sbeet.
`In FIGS. 14(a) and 14(b), 85 is an insulating sheet, 86 is
`a metal bump, and 91 is an adhesive sheet.
`SUMMARY OF TEE INVENTION
`An object of the present invention is to provide a further-
`miniaturized semiconductor device having a stacked pack.
`age structure as well as a CSP structure.
`In order to achieve the above object, a semiconduclor
`device in accordance with the present
`invention has a
`stacked package strUctUre and a chip size package structure
`and is characterized in including:
`an insulating substrate including a wiring layer having
`electrode sections;
`a first semiconductor chip having a first insulating adhe-
`sion layer adhered to its back surface where a circuit is
`
`24/206
`
`MICRON 1012
`
`

`

`US 6,352,879 B1
`
`not formed, the first semiconductor chip being mounted
`on the wiring layer through the first insulating adhesion
`layer; and
`a second semiconductor chip having a second insulating
`adhesion layer adhered to
`its back surface where a
`circuit is not formed, the sacond semiconductor chip
`being mounted on a circuit formed front surface or the
`first semiconductor chip through the second insulating
`adhesion layer;
`each of the first and second semiconductor chips being
`wire-bonded It the electrode section with a wire, the
`first and second semiconductor chips and
`the wire
`being sealed with a resin.
`In the above structure, the first semiconductor chip and
`ihe second semiconductor chip arm each wire-bonded to the
`electrode section provided on the wiring layer with the
`wires, and the second insulating adhesion layer is used for
`affixing the second semiconductor chip to the first semicon
`ductor chip. This structure eliminates the need for wire-
`bonding the first and second semiconductor chips to points
`on the wiring layer, far from the side surfaces of the first and
`second semiconductor chips, considering a situation in
`which the excessively applied adhesive agent overflows the
`space between the first and second semiconductor chips
`Tberefore, a miniaturized, high-density semiconductor
`device can be realied
`Furthermore, in the case of using a thermo-compression
`sheet, when mounting the first or second semiconductor chip
`at a desired location, accurate positioning is required twice,
`t.e., positioning the thermo-compression sheet, etc., and
`positioning the first or second semiconductor chip on the
`thermo-compression sheet In contrast, the first and second
`insulating adhesion layers according to the present invention
`are in advance disposed on the back surfaces of the first and
`second semiconductor chips, respectively. Therefore,
`the
`first or second semiconductor chip can be mounted at a
`desired location by accurately positioning it once. It is thus
`possible to miniaturize the semiconductor device without
`complicating its manufacturing process.
`A semiconductor device in accordance with the present
`invention can be arranged to include:
`an insulating substrate including a wiring layer having
`electrode sections;
`a first semiconductor chip having a circuit formed on its
`front surface and an insulating adhesion layer adhered
`to its back surface;
`a metal bump, disposed between the first semiconductor
`chip and the wiring layer, for bump-bonding the front
`surface of the first semiconductor chip to the wiring
`layer so that the front surface faces the wiring layer;
`and
`a second semiconductor chip whose back surface where a
`circuit is not formed is mounted on the back surface of
`the first semiconductor chip through the insulating
`adhesion layer;
`the second semiconductor chip being wire-lboded to the
`electrode section of the wiring layer with a wire, the
`first and second semiconductor chips and
`the wire
`being sealed with a resin
`In the above arrangement, the first semiconductor chip is
`connected to the wiring layer through the metal bump, the
`second semiconductor chip is wire-bonded to the electrode
`sections on the wiring layer with wires, and
`the back
`surfaces of the first and second semiconductor chips are
`adhered to each other by the insulating layer. This arrange-
`ment eliminates the need for wire-lboding the second semi-
`
`30
`
`35
`
`25
`
`conductor chip to points on the wiring layer, far from the
`side surfaces of the first and second semiconductor chips,
`considering a situation in which thc excessively applied
`adhesive agent overflows the space between the first and
`5 second semiconductor chips. Therefore, a miniaturized,
`high-density semiconductor device can be realized.
`In the case of using the thermocompression sheet, when
`mounting the second semiconductor chip on the first seti
`conductor chip, accurate positioning is required twice in a
`to conventimonal manufacturing method, i.e., positioning the
`thermo-compression sheet on the first semiconductor chip,
`and positioning the second semiconductor chip on
`the
`thermo-compression sheet. However, the insulating adhe
`sion layer according to the present invention are disposed on
`is the back surface of the second semiconductor chip in
`advance. Therefore, the second semiconductor chip can be
`mounted at a desired location on the first semiconductor chip
`by accurately positioning it once, It is thus possible to
`miniaturize fle semiconductor chip without complicating its
`2a manufacturing process.
`A method oF manufacturing a semiconductor device in
`accordance with the present invention includes the steps of:
`(a) forming a first insulating adhesion layer on a back
`surface of a first wafer having a circuit formed on its
`front surface;
`(b) producing separate first semiconductor chips from the
`first wafer by dicing;
`(c) mounting the first semiconductor chip on a wiring
`layer with its back surface facing the wiring layer;
`(d) forming a second insulating adhesion layer on a back
`surface of a second wafer having a circuit formed on its
`front surface;
`(e) producing separate second semiconductor chips from
`the second wafer by dicing;
`(H) mounting the second semiconductor chip on the first
`semiconductor chip with its back surface facing the first
`semiconductor chip;
`(g) wire-bonding the first semiconductor chip to an elec-
`trode section of the wiring layer with a wire;
`(h) wire-bonding the secnd semiconductor chip to an
`electrode section of the wiring layer with a wire; and
`(i) sealing the first and semiconductor chips and the wires.
`41 With the above manufacturing method, since the first or
`second semicondu ctor chip has the first or second insulating
`adhesion layer adhered to its back surface in advance when
`being in the wafer state, the first or second semiconductor
`chip can be mounted at a desired location without the step
`so of accurately positioning the first or second insulating adhe-
`sion layer on the first or second semiconductor chip. It is
`thus possible to simplify the process of manufacturing the
`semiconductor chip.
`Morever, in the above manufacturing method, the adhe
`55 sive agent does not overflow the space between the first and
`second semiconductor chips, the first and second semicon-
`ductor chips can be wire-bonded to the wiring layer at a
`location closer to the edges of the first and second semicon-
`ductor chips. It is thus possible to realize a miniaturized,
`60 high-density semiconductor device.
`A method of manufacturing a semiconductor device in
`accordance with the present invention including the steps of:
`(a) forming an insulating layer and a metal bump on a
`wiring layer;
`(b) mounting a first semiconductor chip on the wiring
`layer with its circuit-formed surface facing the wiring
`layer;
`
`40
`
`65
`
`25/206
`
`MICRON 1012
`
`

`

`US 6,352,879 B1
`
`(c) forming an insulating adhesion layer on a back surface
`of a wafer having a circuil formed on its front surface;
`(i) producing separate second semiconductor chips from
`the wafer by dicing;
`(e) mounting the second semiconductor chip on the firs
`semiconductor chip with its back surface facing the firt
`semiconductor chip;
`(f) wim-bonding the second semiconductor chip to the
`wiring layer with a wire; and
`(g) sealing the first and second semiconductor chips and
`the wire.
`In this manufacturing method, like the above mentioned
`method of the present invention, since the second semicon-
`ductor chip has the insulating adhesion layer adhered to its
`back surface in advance when being in the wafer state, the
`lx mounted at a desired
`second semiconductor chip can
`location without the step of accurately positioning the insu
`lating adhesion layer on the second semiconductor chip. It is
`thus possible to simplify the process of manufacturing the
`semiconductor chip
`Furthermore, in the above manufacturing method, the
`adhesive agent does not overflow the space between the first
`and second semiconductor chips, the second semiconductor
`chip can be wire-bonded to the wiring layer at a location
`closer to the edges of the first and second semiconductor
`chips. It is thus possible to realize a miniaturized, high-
`density semiconductor device.
`For a fuller understanding of the nature and advantages of
`the invention, reference should be made to the ensuing
`detailed description taken in conjunction with the accom-
`panying drawings.
`
`BRIEF DESCRIPI1ON OF TIlE DRAWINGS
`FIG. I is a cross-sectional view ofa semiconductor device
`in accordance with the first embodiment of the present
`invention.
`FIG. 2(a) is a plan view of a circuit board before being
`cut, and
`FIG. 2(b) is a partially enlarged view of the circuit board
`shown in FIG. 2(a).
`FIG. 3(a) is an explanatory view showing an arrangement
`of ball-like external connection-use terminals, and
`FIG. 3(b) is an explanatory view showing an arrangement
`of trapezoidal external connection-use terminals.
`FIG. 4 is an explanatory view showing how laminated
`semiconductor chips are each wire bonded to the circuit
`board.
`FIGS. 5(a) to 5(g) show one example of a process for
`manufacturing the semiconductor device.
`FIG. 6(a) is a partially enlarged view of the circuit board
`including a wiring layer disposed on one surface of an
`insulating substrate, and FIG. 6(5) is a partially enlarged
`view of a circuit board including a wiring layer disposed on
`each surface of the insulating substrate.
`FIG. 7(a) is an explanatory view showing a wiring state
`when two laminated semiconductor chips are connected to
`the same electrode section, and
`FIG. 7(b) is an explanatory view showing another state
`that the two laminated semiconductor chips are connected to
`the same electrcxle section.
`FIG. 8(a) is an explanatory view showing a wiring state
`that the two laminated semiconductor chips are connected to
`different electrode sections, and
`FIG. 8(b) is an explanatory view showing another wiring
`state that the two laminated semiconductor chips are con-
`nected to different electrode sections
`
`10
`
`FIG. 9(a) is an explanatory view showing one example of
`an arrangement of dummy pads formed on a firsl semicon-
`ductor chip, and
`FIG. 9(b) is an explanatory view showing another
`5 example ol the arrangement of the dummy pads disposed on
`the first semiconductor chip.
`FIG. 10 is a cross-setional view of a semiconductor
`device in accordance with the second embodiment of the
`present invention.
`FIGS. 11(a) to 11(g) show one example of a process for
`manufacturing the miconductor device.
`FIG. 12(a) is a perspective view showing that a second
`semiconductor chip in the semiconductor device in accor-
`is dance with the first embodiment or the second embodiment
`protrades from a first semiconductor chip, and
`FIG. 12(b) is a perspective view showing that the second
`semiconductor chip is reinforced.
`FIG. 13(a) is a cross-sectional view showing a semicon-
`2z ductor device having a CSP structUre manufactured by a
`conventional wire bonding method, and
`FIG. 13(b) is a cross-sectional view showing a semicn
`ductor device having a CSP structure manufactured by a
`conventional face-down bonding method.
`FIG. 14(a) and HG. 14(b) are cross-sectional views of
`conventional semiconductor devices having a stacked pack
`age structure.
`FIG. 15 is a cross-sectional view of the semiconductor
`device shown in FIG. 14(a) during manufacturing.
`
`25
`
`30
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`35
`
`Embodiment 1
`The following descriptions will explain one embodiment
`of the present invention with reference to FIGS. 1 to 9.
`As shown in FIG. 1, in a semiconductor device according
`to this embodiment, a first semiconductor chip I and a
`second semiconductor chip 2 arm laminated in this order on
`40 a circuit board 5 including an insulating substrate 3 and a
`wiring layer 4 mounted on the
`insulating substrate 3.
`Regarding the first semiconductor chip I and the second
`semiconductor chip 2, the surface (front surface) on which
`an element is formed is hereinafter referred to as a "circuit
`41 formed surface", and the surface opposite thereto is remerred
`to as a "back surface".
`The semiconductor chip I is disposed with its back
`surface facing the insulating substrate 3. Thbe second semi-
`conductor chip 2 is mounted on the circuit formed surface of
`so the first semiconductor chip I
`through a thermo-
`compression sheet (adhesion layer) 6 so that its back surface
`is adhered to the thermo-compression seet 6,
`The semiconductor device in accordance with the present
`embodiment is arranged so that the second semiconductor
`ss chip 2 is mounted on the circuit formed surface of the first
`semiconductor chip 1. With this arrangement, the second
`semiconductor chip 2 on the top of the first semiconductor
`chip I does not influence (interfere with) electrode pads of
`the first semiconductor chip 1. The circuit formed surface of
`the first semiconductor chip 1 is in advance coated with an
`insulating-resin, etc. Namely, the coating is applied to the
`circuit formed surface of the first semiconductor chip I by
`a spin coating method, etc. when the first semiconductor
`chip 1 is in a wafer state before subjected to dicing. In this
`65 case, the coating material on the electrode pads (not shown)
`disposed on the circuit formed surface of the first semicon-
`ductor chip 1 is removed.
`
`60
`
`26/206
`
`MICRON 1012
`
`

`

`US 6,352,879 B1
`
`The filst semiconductor chip I and the second semicon-
`ductor chip 2 are each connected (wire-bonded) to electrode
`sections of the wiring layer 4 on the insulating substrate 3
`with wires 7.
`The first semiconductor chip 1, the second semiconductor
`chip 2 and the wires 7, arranged as above, are covered by a
`scaling resin 8.
`The insulating substrate 3 includes via holes 9 at
`the
`locations corresponding to below-describd land sections 12
`constituting the wiring layer 4. Ball-like packaging-use
`external terminals 10 are connected in an area-array-like
`arrangement to the land sections 12 through the via holes 9
`from the side of the insulating substrate 3. on which side the
`first semiconductor chip I and the second semiconductor
`chip 2 are not formed.
`Next, the tdlowing descriptions will explain in further
`detail the above-mentioned members constituting the semi-
`conductor device in accordance with the present embodi
`menit-
`FIG. 2(a) is a plan view of the circuit board 5 before being
`cut in the pocess of manufacturing the semiconductor
`device. As