UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`__________________________
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`v.
`KATANA SILICON TECHNOLOGIES LLC,
`Patent Owner.
`
`__________________________
`
`IPR 2023-00073
`U.S. Patent No. 6,352,879
`__________________________
`
`
`
`
`DECLARATION OF JEFFREY C. SUHLING, PH.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 6,352,879
`
`
`
`
`
`
`
`MICRON 1002
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`

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`TABLE OF CONTENTS
`
`IPR 2023-00073
`U.S. Patent No. 6,352,879
`
` 
`
` 
`
` 
`
`
`Introduction and Qualifications ....................................................................... 1 
`Understanding of Legal Principles and Perspectives ...................................... 7 
`A. 
`Types of Claims ..................................................................................... 7 
`B. 
`Anticipation and Obviousness ............................................................... 8 
`C. 
`Claim Construction ............................................................................. 11 
`  Basis for My Opinions ................................................................................... 12 
`  Summary of My Opinions ............................................................................. 12 
`Level of Ordinary Skill in the Art in the Relevant Timeframe ..................... 12 
`  Background on Semiconductor Manufacturing Technology in 1998 ........... 15 
`A. 
`Semiconductor Packages ..................................................................... 15 
`B. 
`Traditional Leadframe Packages ......................................................... 16 
`C. 
`Ball-Grid Arrays .................................................................................. 18 
`D.  Wire Bonding ...................................................................................... 19 
`E. 
`Flip-Chip ............................................................................................. 25 
`F. 
`Industry Pressure to Miniaturize Semiconductor Packages ................ 29 
`1.  Multi-Chip Modules ................................................................. 31 
`2. 
`Application of Adhesive to Wafer Backside ........................... 34 
`Encapsulation/Sealing ......................................................................... 39 
`G. 
`Semiconductor Packages in the 1998 Timeframe ............................... 40 
`H. 
`  The ’879 Patent .............................................................................................. 40 
`A. 
`The Conventional Semiconductor Package and Manufacturing Process
`Described in the ’879 patent. ............................................................... 40 
`Prosecution History of the ’879 patent and its family members. ........ 46 
`1. 
`’594 Patent File History ........................................................... 47 
`2. 
`’217 Patent File History ........................................................... 48 
`3. 
`’806 Patent File History ........................................................... 48 
`4. 
`’879 Patent File History ........................................................... 49 
`Applicant Admitted Prior Art .............................................................. 50 
`
`C. 
`
`B. 
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`B. 
`
`IPR 2023-00073
`U.S. Patent No. 6,352,879
`1. 
`Aoki .......................................................................................... 52 
`Tadasu ...................................................................................... 55 
`2. 
`  Claim Construction ........................................................................................ 59 
`  Overview of the Prior Art .............................................................................. 63 
`A. 
`Ball ...................................................................................................... 63 
`B. 
`Fogal .................................................................................................... 64 
`C.  Mostafazadeh ....................................................................................... 65 
`D. 
`Tsumura ............................................................................................... 68 
`E.  Ma ........................................................................................................ 69 
`Flip-Chip Claims: Grounds for Challenge .................................................... 71 
`A.  Ground 1: Claim 7 is Obvious over Ball in view of Mostafazadeh .... 72 
`1.  Motivation to Combine Ball and Mostafazadeh ...................... 72 
`2. 
`Independent Claim 7 ................................................................ 77 
`Ground 2: Claims 8 and 9 are Obvious over Ball and Mostafazadeh in
`view of Tsumura .................................................................................. 99 
`1.  Motivation to Combine Ball and Mostafazadeh and Tsumura 99 
`2. 
`Dependent Claim 8 ................................................................ 100 
`3. 
`Dependent Claim 9 ................................................................ 106 
`  Wire Bond claims: Grounds for Challenge ................................................. 107 
`A.  Ground 3: Claims 1-2, 10-11, and 15 are Obvious over Ball, Fogal,
`and in further view of Mostafazadeh ................................................107 
`1.  Motivation to Combine Ball, Fogal, and Mostafazadeh ........ 107 
`2. 
`Independent Claim 1 .............................................................. 112 
`3. 
`Dependent Claim 2 ................................................................ 123 
`4. 
`Independent Claim 10 ............................................................ 127 
`5. 
`Dependent Claim 11 .............................................................. 129 
`6. 
`Independent Claim 15 ............................................................ 129 
`Ground 4: Claims 3-4 and 12 Are Obvious Over Ball and Fogal in
`view of Mostafazadeh and Tsumura .................................................131 
`1.  Motivation to Combine Ball, Fogal, Mostafazadeh, and
`Tsumura ................................................................................. 131 
`Dependent Claim 3 ................................................................ 132 
`Dependent Claim 4 ................................................................ 132 
`
`2. 
`3. 
`
`B. 
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`C. 
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`IPR 2023-00073
`U.S. Patent No. 6,352,879
`4. 
`Dependent Claim 12 .............................................................. 133 
`Ground 5: Claims 5-6 and 13-14 Are Obvious Over Ball and Fogal in
`view of Mostafazadeh and Ma ..........................................................134 
`1.  Motivation to Combine Ball, Fogal, Mostafazadeh, and Ma 134 
`2. 
`Dependent Claim 5 ................................................................ 135 
`3. 
`Dependent Claim 6 ................................................................ 137 
`4. 
`Dependent Claim 13 .............................................................. 139 
`5. 
`Dependent Claim 14 .............................................................. 140 
`  CONCLUSION ........................................................................................... 140 
`
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`
`LIST OF EXHIBITS
`
`IPR 2023-00073
`U.S. Patent No. 6,352,879
`
`Ex. 1001
`
`U.S. Patent No. 6,352,879 (“’879 patent”)
`
`Ex. 1002
`
`Declaration and Curriculum Vitae of Dr. Jeffrey Suhling (“Suhling”)
`
`Ex. 1003
`
`International Publication WO 1996/13066 (“Mostafazadeh”)
`
`Ex. 1004
`
`U.S. Patent No. 5,323,060 (“Fogal”)
`
`Ex. 1005
`
`U.S. Patent No. 7,166,495 (“Ball”)
`
`Ex. 1006
`
`U.S. Patent No. 5,790,384 (“Ahmad”)
`
`Ex. 1007
`
`U.S. Patent No. 4,821,944 (“Tsumura”)
`
`Ex. 1008
`
`U.S. Patent No. 6,014,586 (“Weinberg”)
`
`Ex. 1009
`
`U.S. Patent No. 6,682,954 (“Ma”)
`
`Ex. 1010
`
`European Patent No. EP0590598A1 (“Mita”)
`
`Ex. 1011
`
`Ex. 1012
`
`Ex. 1013
`
`Ex. 1014
`
`Ex. 1015
`
`Ex. 1016
`
`Ex. 1017
`
`File History - U.S. Reissue Patent No. RE38,806 (family member of
`’879 patent)
`File History - U.S. ’879 patent
`
`File History - U.S. Patent No. 6,229,217 (family member of ’806
`patent)
`File History - U.S. Patent No. 6,100,594 (family member of ’806
`patent)
`JP Unexamined Application Publication 1997/121002 & Certified
`Translation (“Aoki”)
`
`JP Unexamined Application Publication No. 90486/1993 & Certified
`Translation (“Tadasu”)
`
`Eugene J. Rymaszewski, Rao R. Tummala, & Toshihiko Watari, Ch.
`1, Microelectronics Packaging—An Overview, in
`MICROELECTRONICS PACKAGING HANDBOOK (Rao R. Tummala et al.
`eds., 2d ed. 1997).
`
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`Ex. 1018
`
`Ex. 1019
`
`Ex. 1020
`
`Ex. 1021
`
`Ex. 1022
`
`1023
`
`Ex. 1024
`
`Ex. 1025
`
`IPR 2023-00073
`U.S. Patent No. 6,352,879
`Kenneth Rose, Tsuneyo Chiba, William R. Heller & Wadie F.
`Mikhal, Ch. 2, Package Wiring and Terminals, in
`MICROELECTRONICS PACKAGING HANDBOOK (Rao R. Tummala et al.
`eds., 2d ed. 1997).
`
`Lewis S. Goldmann, Robert T. Howard & Dexter A. Jeannotte, Ch.
`5, Package Reliability, in MICROELECTRONICS PACKAGING
`HANDBOOK (Rao R. Tummala et al. eds., 2d ed. 1997).
`
`Paul A. Totta, Subash Khadpe, Nicholas G. Koopman, Timothy C.
`Reiley & Michael J. Sheaffer, Ch. 8, Chip-to-Package
`Interconnections, in MICROELECTRONICS PACKAGING HANDBOOK
`(Rao R. Tummala et al. eds., 2d ed. 1997).
`
`Rao R. Tummala, Phil Garrou, Tapan Gupta, N. Kuramoto, Koichi
`Niwa, Yuzo Shimada & Masami Terasawa, Ch. 9, Ceramic
`Packaging, in MICROELECTRONICS PACKAGING HANDBOOK (Rao R.
`Tummala et al. eds., 2d ed. 1997).
`
`Michael G. Pecht & Luu T. Nguyen, Ch. 10, Plastic Packaging, in
`MICROELECTRONICS PACKAGING HANDBOOK (Rao R. Tummala et al.
`eds., 2d ed. 1997).
`
`J. Richard Behun, Thomas Caulfield, Marie Cole, Timothy C.
`Reiley, Pratap Singh & Puligandla Viswanadham, Ch. 16, Package-
`to-Board Interconnections, in MICROELECTRONICS PACKAGING
`HANDBOOK (Rao R. Tummala et al. eds., 2d ed. 1997).
`
`MICROELECTRONICS PACKAGING HANDBOOK, Glossary and Symbols,
`pp. 931-76 (Rao R. Tummala et al. eds., 2d ed. 1997).
`
`Massenat, M., High Density Package, Cofired, Multi Chip Module,
`3D, A Mass Memory Mixed Technology for Space Applications,
`Proceedings of the 9th European Hybrid Microelectronics
`Conference, pp. 216-23 (1994).
`
`Ex. 1026
`
`Al-Sarawi, S. F., Abbott, D., Franzon, P. D., A Review of 3-D
`Packaging Technology, IEEE TRANSACTIONS ON COMPONENTS,
`
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`Ex. 1027
`
`IPR 2023-00073
`U.S. Patent No. 6,352,879
`PACKAGING, AND MANUFACTURING TECHNOLOGY, Part B, Vol.
`21(1), pp. 2-14, Feb 1998.
`
`D. B. Tuckerman, L.-O. Bauer, N. E. Brathwaite, J. Demmin, K.
`Flatow, R. Hsu, P. Kim, C.-M. Lin, K. Lin, S. Nguyen, & V.
`Thipphavong, Laminated Memory: A New 3-Dimensional
`Packaging Technology for MCM’s, PROCEEDINGS OF THE 1994 IEEE
`MULTI-CHIP MODULE CONFERENCE, pp. 58-63 (Mar. 1994).
`
`Ex. 1028
`
`U.S. Patent No. 5,804,004 to David B. Tuckerman et al.
`
`Ex. 1029
`
`G. Rochat, COB and COC for Low Cost and High Density Package,
`PROCEEDINGS OF THE 17TH IEEE/CPMT INTERNATIONAL
`ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, pp. 109-
`111 (Oct. 1995) (“Rochat”).
`
`Ex. 1030
`
`U.S. Patent No. 4,688,075 to William S. Phy.
`
`Ex. 1031
`
`U.S. Patent No. 5,411,921 to Atsuhito Negoro.
`
`Ex. 1032
`
`U.S. Patent No. 5,762,744 to Kazutaka Shibata et al.
`
`Ex. 1033
`
`U.S. Patent No. 5,110,388 to Mikio Komiyama et al.
`
`Ex. 1034
`
`U.S. Patent No. 6,007,920 to Norito Umehara et al.
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`IPR 2023-00073
`U.S. Patent No. 6,352,879
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`I, Jeffrey C. Suhling, Ph.D., declare as follows:
`
`1.
`
`I have been retained by Perkins Coie LLP on behalf of Micron
`
`Technology, Inc. (“Petitioner”), to provide certain opinions concerning the validity
`
`of the claims of U.S. Patent No. 6,352,879 (“the ’879 patent”).
`
`2.
`
`I am over 18 years of age. I have personal knowledge of the facts stated
`
`in this Declaration and could testify competently to them if asked to do so.
`
`3.
`
`I am being compensated for my time at a rate of $400 per hour. I am
`
`not receiving any other form of compensation. I have no interest in the outcome of
`
`this proceeding, and my compensation is not dependent on the content of my
`
`opinions or the outcome of this proceeding.
`
`INTRODUCTION AND QUALIFICATIONS
`4.
`My technical background and experience are summarized in my resume
`
`in Exhibit 1002 to the Petition.
`
`I earned a Bachelor of Science in Applied
`
`Mathematics, Engineering, and Physics (AMEP) from the University of Wisconsin
`
`in 1980. I earned a Master of Science in Engineering Mechanics from the University
`
`of Wisconsin in 1981, and a Doctorate in Engineering Mechanics from the
`
`University of Wisconsin in 1985.
`
`5.
`
`I am currently employed as a Quina Distinguished Professor and
`
`Department Chair at the Department of Mechanical Engineering at Auburn
`
`University in Auburn, Alabama. I have been on the faculty at Auburn University
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`IPR 2023-00073
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`since 1985. I am a member of the American Society for Mechanical Engineers
`
`(ASME), the Institute of Electrical and Electronics Engineers (IEEE), the Surface
`
`Mount Technical Association (SMTA), the International Microelectronics and
`
`Packaging Society (IMAPS), and currently serve on several boards.
`
`6. My primary areas of expertise and research are semiconductor
`
`packaging and solid mechanics. I have over 30 years of experience in each of these
`
`fields. In the area of semiconductor packaging, I have extensive experience in
`
`electronics assembly, packaging technologies and processes, stress and strain
`
`analysis of electronic products, on-chip silicon sensors, solder joint reliability,
`
`material
`
`testing and mechanical behavior of solders and microelectronic
`
`encapsulants, and finite element modeling (FEA) and reliability modeling of
`
`electronic products. I have regularly taught undergraduate-level and graduate-level
`
`courses on electronics packaging technology for the past 30 years, and have written
`
`a textbook on the topic. I have published and presented over 550 technical papers in
`
`various international journals and conferences.
`
`7.
`
`I co-founded the Center for Advanced Vehicle Electronics or “CAVE”
`
`in 1998. This organization is a research center for semiconductor packaging that has
`
`been continuously funded for the past 24 years by the National Science Foundation
`
`and over 50 member companies. The CAVE Center specializes in the assembly,
`
`manufacturing, mechanics, thermal, and reliability aspects of semiconductor
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`IPR 2023-00073
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`packaging in harsh environments such as automotive and aerospace electronics,
`
`computer servers, cellular phones and portable electronics, among other devices. I
`
`served as Center Director of CAVE from 2002-2008, and Center Associate Director
`
`from 1998-2008. I have continued to direct multiple CAVE research projects in
`
`semiconductor packaging and lead-free soldering since being promoted in 2008 to
`
`Department Chair of the Department of Mechanical Engineering at Auburn
`
`University.
`
`8.
`
`I have received over 125 contracts and grants to support my research,
`
`the bulk of which has been focused on various aspects of semiconductor packaging.
`
`In particular, I have obtained research support from the National Science
`
`Foundation, Semiconductor Research Corporation, NASA, Department of Defense
`
`- Army, Air Force, Navy, and over 50 companies including Texas Instruments, ST
`
`Microelectronics, Freescale Semiconductor, NXP, Cookson Electronics, Henkel
`
`Corporation, Schlumberger, John Deere Electronics, Chrysler Corporation,
`
`Continental Automotive, Siemens, LG, General Dynamics Corporation, and others.
`
`I have received several awards including being elected a Fellow of the American
`
`Society of Mechanical Engineers, as well as receiving the Electronic Packaging
`
`Division Mechanics Research Award from the same society.
`
`9.
`
`I am well versed in semiconductor packaging technology, and I have
`
`been working in that field for 34 years from 1988-present. I have published and
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`IPR 2023-00073
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`presented over 450 technical papers in the electronic packaging technical area, as
`
`well as attending over 60 technical conferences in the field. I have served as the
`
`Conference General Chair of the 2009 International Conference on Packaging and
`
`Integration of Electronic and Photonic Microsystems (InterPACK), as well as the
`
`General Chair of
`
`the 2019
`
`Intersociety Conference on Thermal and
`
`Thermomechanical Phenomena in Electronic Systems (ITherm). I have also served
`
`in several other leadership roles in the semiconductor packaging area, including my
`
`current elected position of Vice President - Education of the IEEE Electronics
`
`Packaging Society, as well as serving as the Chair of the ASME Electronic and
`
`Photonic Packaging Division, and as an Associate Editor for the ASME Journal of
`
`Electronic Packaging, a leading technical journal in the field.
`
`10. My expertise in the field of semiconductor packaging includes the
`
`design and manufacturing of packaged semiconductor chips such as the stacked die
`
`multichip packages addressed in the ’879 patent. In particular, I have extensive
`
`experience with design and fabrication of semiconductor chips, substrates,
`
`leadframes, and other building blocks of modern electronic assemblies and
`
`packages. In addition, I have worked for over 30 years on the manufacturing
`
`processes used for electronics assembly and packaging including die attachment to
`
`substrates, flip-chip and wire bond technologies to form the electrical connections
`
`between chips and substrate wiring layers, encapsulation operations to surround
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`chips and assemblies with resin based molding compounds, and dicing and
`
`singulation methods to extract individual chips and packages. I also have extensive
`
`experience with a wide variety of package form factors including various plastic
`
`packages, Ball Grid Arrays, Chip Size Packages, and Multichip Modules.
`
`11. From the chronological point of view, my experiences with the design,
`
`manufacture, and reliability of semiconductor components and multichip modules
`
`encompass the January 1998 alleged invention date of the ’879 patent. In particular,
`
`I began working with several types of low lead count plastic packages in 1988
`
`including Small Outline Transistors (SOTs) and DPAKs for power transistors, as
`
`well as Dual Inline Packages (DIPs). For the past 30 years from 1990-present, my
`
`research and development activities have concentrated on the design and
`
`manufacturing, mechanics and reliability, and thermal performance of such plastic
`
`encapsulated semiconductor chips. In addition to the early plastic package types
`
`mentioned above, my experiences have included other more advanced plastic
`
`packaging form factors including Dual Flat No-Lead (DFN) packages, Quad Flat
`
`No-Lead (QFN) packages, Plastic Leaded Chip Carriers (PLCCs), Quad Flat Packs
`
`(QFPs), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), and Multichip
`
`Modules (MCMs).
`
`12. Beginning in the 1990s, I collaborated with industry on several projects
`
`related to the design, manufacturing, and reliability of plastic packaging. Example
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`topics include: (1) thermal performance and solder joint reliability of chip resistors
`
`and DPAK components on insulated metal substrates; (2) measurements of
`
`mechanical stresses in semiconductor chips after die attachment and wire bonding
`
`to metal leadframes and substrates; (3) measurements of mechanical stresses in
`
`semiconductor chips during and after the plastic encapsulation process for several
`
`form factors including DIPs, Small Outline Packages (SOPs), PLCCs, QFPs, BGAs,
`
`and stacked die CSPs, etc.; (4) exploration of modified leadframe designs to increase
`
`plastic package reliability; (5) Determination of optimal mold compound materials
`
`to reduce semiconductor die stress; (6) finite element modeling of solder joint
`
`reliability for PLCC and QFP components in automotive engine controllers; (7)
`
`measurement and prediction of the reliability of BGA components in the automotive
`
`under-the- hood applications; among others.
`
`13. My work in these areas continues today. For example, Ball Grid Arrays
`
`(BGAs), Dual Flat No-Lead (DFN) packages, and Quad Flat No-Lead (QFN)
`
`packages are currently being studied in my ongoing research project on isothermal
`
`aging induced degradations of solder joint reliability in harsh environment
`
`applications. This work involves surface mount assembly of several types of plastic
`
`encapsulated semiconductor components to printed circuit boards, and subsequent
`
`isothermal aging and thermal cycling reliability testing of the assemblies. In
`
`addition, material testing has been performed to characterize the mechanical
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`properties of the semiconductor chip, leadframe, die attachment adhesive, molding
`
`compound, and solder materials; and then finite element modeling has been
`
`performed on the electronic assemblies to predict their reliability.
`
` UNDERSTANDING OF LEGAL PRINCIPLES AND PERSPECTIVES
`14.
`I am not a lawyer, and I will not provide any legal opinions. Although
`
`I am not a lawyer, I have been advised certain legal standards are to be applied by
`
`technical experts in forming opinions regarding the meaning and validity of patent
`
`claims.
`
`15.
`
`In forming my analysis, opinions and conclusions expressed in this
`
`declaration, I have applied the legal principles set forth below which were provided
`
`to me by counsel for Micron.
`
`A. Types of Claims
`16.
`I understand that there are two types of U.S. patent claims:
`
`1) independent claims and 2) dependent claims. I understand that independent claims
`
`only include the aspects stated in the independent claim. I further understand that
`
`dependent claims include the aspects stated in that dependent claim, and any other
`
`aspects stated in any claim from which that dependent claim depends.
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`B. Anticipation and Obviousness
`17.
`I understand that a claim is not patentable if it is anticipated or obvious.
`
`I understand that anticipation of a claim requires that every element of a claim is
`
`disclosed expressly or inherently in a single prior art reference.
`
`18.
`
`I further understand that obviousness of a claim requires that the claim
`
`be obvious from the perspective of a person of ordinary skill in the art (POSITA), at
`
`the time the invention was made. I understand that the earliest patent application
`
`filing leading to the ’879 patent was a Japanese application filed on January 14,
`
`1998, and I have assumed this is the ’879 patent's alleged invention date.
`
`19.
`
`I have therefore analyzed the unpatentability of the claims as of that
`
`day. I may refer to the relevant time period as the 1998 timeframe in this declaration,
`
`with the understanding that this does not include the time period on or after the filing
`
`date of the first application (January 14, 1998).
`
`20.
`
`I understand that to prove that prior art or a combination of prior art
`
`renders a patent obvious, it is necessary to:
`
`a)
`
`b)
`
`identify the particular references that, singly or in combination,
`make the patent obvious;
`specifically identify which elements of the patent claim appear in
`each of the asserted references; and
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`IPR 2023-00073
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`c) explain why a POSITA would have combined the references, and
`how they would have done so, to create the inventions claimed in
`the patent.
`I further understand that exemplary rationales that may support a
`
`21.
`
`conclusion of obviousness include:
`
`a)
`
`b)
`
`combining prior art elements according to known methods to yield
`predictable results;
`
`simple substitution of one known element for another to obtain
`predictable results;
`
`c) use of known technique(s) to improve similar devices (methods or
`products) in the same way;
`
`d) applying a known technique to a known device (method or
`product) ready for improvement to yield predictable results;
`
`e)
`
`f)
`
`g)
`
`“obvious to try” - choosing from a finite number of identified,
`predictable solutions with a reasonable expectation of success;
`
`known work in one field of endeavor may prompt variations of the
`work for use in either the same field or a different field based on
`design incentives or other market forces if the variations are
`predictable to a POSITA; and
`
`some teaching, suggestion, or motivation in the prior art that would
`have led a POSITA to modify the prior art reference or to combine
`prior art reference teachings to arrive at the claimed invention.
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`22.
`
`In analyzing obviousness, I understand that it is important to understand
`
`the scope of the claims, the level of skill in the relevant art, the scope and content of
`
`the prior art, the differences between the prior art and the claims, and any “secondary
`
`considerations” (described below). I also understand that if a technique has been
`
`used to improve one device, and a person of ordinary skill in the art would recognize
`
`that it would improve similar devices in the same way, using the technique is obvious
`
`unless its actual application is beyond his or her skill. Although I understand that it
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`is not required, there may also be a specific “teaching, suggestion or motivation” to
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`combine any first prior art reference with a second prior art reference. Such a
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`“teaching, suggestion, or motivation” to combine the first prior art reference with
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`the second prior art reference can be explicit or implicit, and may provide further
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`evidence of obviousness.
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`23.
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`I understand that secondary (or objective) considerations are relevant
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`to the determination of whether a claim is obvious. Such secondary (or objective)
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`considerations can include evidence of commercial success caused by an invention,
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`evidence of a long-felt need that was solved by an invention, evidence that others
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`copied an invention, or evidence that an invention achieved a surprising or
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`unexpected result. I understand that such evidence must have a nexus, or causal
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`relationship to the elements of a claim, to be relevant to the obviousness or non-
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`obviousness of the claim. I am not currently aware of any such evidence for the
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`IPR 2023-00073
`U.S. Patent No. 6,352,879
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`claims of the ’879 patent and reserve my right to review and respond to such
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`evidence if presented.
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`C. Claim Construction
`24.
`I understand that, for purposes of my analysis, the terms appearing in
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`the patent claims should be interpreted according to their “ordinary and customary
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`meaning.” In determining the ordinary and customary meaning, the words of a claim
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`are first given their plain meaning that those words would have had to a POSITA. I
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`understand that the structure of the claims, the specification, and the file history also
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`may be used to better construe a claim term. Additionally, treatises and dictionaries
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`may be used, in limited circumstances, to determine the meaning attributed by a
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`person of ordinary skill in the art to a claim term at the time of filing. I have followed
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`this approach in my analysis, and for all of the claim terms considered in this
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`declaration, I have applied the plain and ordinary meaning of those terms.
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`25.
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`I also understand that the words of the claims should be interpreted as
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`they would have been interpreted by a POSITA at the time the alleged invention was
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`made (not today). I have used the date of January 14, 1998 for reasons explained
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`above. However, the plain meanings/interpretations that I employed in my analysis
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`below would have also been correct if the date of invention was anywhere within the
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`late 1990s or early 2000s.
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`IPR 2023-00073
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` BASIS FOR MY OPINIONS
`26.
`In forming my opinions, I have relied on the ’879 patent, specification,
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`figures and claims along with the ’879 patent’s prosecution history, which I
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`understand is the written record with the U.S. Patent office, the exhibits to the
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`Petition for inter partes review of the ’879 patent, and additional materials identified
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`in this declaration, as well as my own experience and expertise as a skilled artisan
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`in the relevant art in the 1998 timeframe as set forth below.
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` SUMMARY OF MY OPINIONS
`27.
`I have been asked to consider whether claims 1-15 of the ’879 patent
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`(“the Challenged Claims”) are anticipated or rendered obvious by certain prior art
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`references. Based on the analysis set forth herein, including my experience and
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`knowledge in the field, my understanding of the claims, the prior art, the applicable
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`law, and the level of skill in art in the 1998 timeframe, my opinion is that the
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`Challenged Claims are invalid for the reasons set forth herein.
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` LEVEL OF ORDINARY SKILL IN THE ART IN THE RELEVANT
`TIMEFRAME
`28. The relevant time for assessing the level of skill of the hypothetical
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`person of ordinary skill in the art (“POSITA”) is the January 14, 1998 filing date of
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`the Japanese application, to which I understand the ’879 patent ultimately claims a
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`benefit for its date of alleged invention. To assess the level of ordinary skill in the
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`art at that time, I understand that one should consider factors such as: (1) the
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`IPR 2023-00073
`U.S. Patent No. 6,352,879
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`educational level of the inventor; (2) the type of problems encountered in the art;
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`(3) prior art solutions to those problems; (4) the rapidity with which innovations are
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`made; (5) the sophistication of the technology; and (6) the educational level of active
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`workers in the field.
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`29. Considering these factors, it is my opinion that one of ordinary skill in
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`the art of the ’879 patent prior to January 14, 1998, would have been a person having
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`at least: i) a bachelor-level degree in electrical engineering, mechanical engineering,
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`materials science or a related subject, and five or more years’ experience working in
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`the field of semiconductor packaging; ii) a Master’s-level degree in mechanical
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`engineering, electrical engineering, materials science or a related field and at least
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`1-3 years of experience in the design/development of semiconductor packages, or
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`iii) a Ph.D.-level degree in mechanical engineering, materials science, electrical
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`engineering, or a related field, and at least some experience in the area of
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`semiconductor packaging. Additional education could substitute for professional
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`experience, and significant work experience could substitute for formal education.
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`30.
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`I base the foregoing on my own experience as an educator at Auburn
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`University, where both I and my former students in the relevant 1998 timeframe
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`were involved in the design and development of semiconductor packages and
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`associated technology. Further, I have been a frequent attendee at conferences and
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`IPR 2023-00073
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`conventions, including several within or immediately before the relevant 1998
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`timeframe, at which I interacted with engineers working in the industry.
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`31. Along these lines, I have identified Microelectronics Packaging
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`Handbook, Parts 1-3, edited by Tummala, R. R., Rymaszewski, E. J., and
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`Klopfenstein, A. G., Kluwer Academic Publishers (2nd ed. 1997) (“Tummala”) as a
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`seminal reference appearing immediately before the relevant 1998 timeframe of
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`the ’879 patent. In particular, Chapter 1 of Tummala, titled “Microelectronics
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`Packaging–An Overview,” provides an overview of semiconductor package
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`development during the 1970s, 1980s, and 1990s, and the rapid evolution in
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`packaging technologies required to increase functionality and reduce the size
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`(semiconductor package footprint) of electronic products. In addition to the overall
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`microelectronics packaging overview provided by Chapter 1 of Tummala, I rely on
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`additional chapters of the Tummala reference herein to provide further detail into
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`the semiconductor packaging process.
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`32. The evolution of packaging technologies discussed in Chapter 1 of
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`Tummala (Microelectronics Packaging–An Overview) demonstrates that with the
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`above-noted ordinary skill in the art, engineers were able to quickly make
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`improvements and