UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`v.
`KATANA SILICON TECHNOLOGIES, LLC,
`Patent Owner.
`_______________
`Case IPR2023-00073
`U.S. Patent No. 6,352,879
`_______________
`___________________________________
`DECLARATION OF PETER ELENIUS
`___________________________________
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`Page 1 of 28
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
`
`I.
`
`INTRODUCTION
`
`1.
`
`I am over the age of 18 and am competent to make this Declaration. I have personal
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`knowledge, or have developed knowledge, of these technologies based upon my education,
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`training, and/or experience, of the matters set forth herein.
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`2.
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`I have been retained by counsel for Plaintiff Katana Silicon Technologies, LLC
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`(“Katana”), in the above matter. I am submitting this Declaration in support of Katana’s Patent
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`Owner Preliminary Response in IPR2023-00073 that is directed to the claims of U.S. Patent No.
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`6,352,879 (“the ’879 Patent”).
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`3.
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`I am being compensated at my normal rate, plus reimbursement for expenses, for
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`my analysis. My compensation does not depend on the content of my opinions or the outcome of
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`this proceeding.
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`II.
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`QUALIFICATIONS AND PROFESSIONAL EXPERIENCE
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`4.
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`My qualifications are stated more fully in my curriculum vitae, which has been
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`provided as Exhibit 1. Here, I provide a brief summary of my qualifications.
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`5.
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`Some highlighted information regarding my education, technical experience and
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`publications is provided below.
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`6.
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`I have forty years of experience in semiconductor packaging technology. I am
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`presently the Managing Partner of E&G Technology Partners (“E&G”). As Managing Partner at
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`E&G, I provide technology and business consulting services for the advanced integrated circuit
`
`(IC) packaging industry.
`
`7.
`
`From March 1996 to March 2002, I was Vice President of Technology and CTO
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`for Flip Chip Technologies LLC. From January 1995 to February 1996, I was the Flip Chip Product
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`Manager for Kulicke and Soffa Industries Inc. From July 1982 to December 1994, I worked for
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`IBM Inc. in the areas of flip chip equipment and process engineering with my last position being
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`an Advisory Engineering Manager.
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`8.
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`I am the co-inventor of thirteen United States patents, all related to semiconductor
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`packaging technology.
`
`9.
`
`I am the author and co-author of forty-six technical publications, all related to
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`semiconductor packaging technology.
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`10.
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`I am currently a member of the Institute of Electrical and Electronic Engineers
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`(IEEE) and the International Microelectronic and Packaging Society (IMAPS). I am also a member
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`of the IEEE Electronics Packaging Society.
`
`11.
`
`I have been an invited speaker at many semiconductor industry conferences and
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`have taught short courses related to both flip chip and wafer level packaging at conferences and
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`corporations. From 2000-2002, I was the General Chair for the first IMAPS Flip Chip Workshops.
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`In 2012, I was the General Chair for the IMAPS Device Packaging Conference.
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`12.
`
`I received my Bachelor of Science degree in mechanical engineering from the
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`University of Wisconsin, Madison in 1982. I received my Master of Science degree in
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`manufacturing systems from the University of Wisconsin, Madison in 1990.
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`13. My analyses set forth in this declaration are informed by my experience in the field
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`of semiconductor packaging. Based on my above-described experience, I am an expert in the field
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`relevant to the ’879 Patent at issue here and have been an expert in the relevant field since before
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`the claimed priority date of the ’879 Patent. I am familiar with how a person having ordinary skill
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`in the art (“POSITA”) would have understood and used the terminology found in the ’879 Patent
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`before and at the time of its respective filing date.
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
`
`III.
`
`PETITION FOR INTER PARTES REVIEW
`
`14.
`
`I understand that Micron Technology, Inc., filed a petition for Inter Partes Review
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`on October 28, 2022. PTAB Case No. IPR 2023-00073 is for challenging the validity of claims
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`1-15 of the ’879 Patent. That petition relied on an expert declaration from Dr. Jeffrey Suhling. Ex.
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`1002.
`
`IV.
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`LEGAL STANDARDS
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`15.
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`I am not an attorney. Counsel has informed me about several principles and
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`standards of patent law, which I have used in developing my opinions expressed herein.
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`16. My opinions are also informed by my understanding of the relevant law. I
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`understand that the patentability analysis is conducted on a claim-by-claim and element-by-
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`element basis, and that there are several possible reasons that a patent claim may be found to be
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`unpatentable.
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`17.
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`I understand that earlier publications and patents may act to render a patent
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`unpatentable for one of two reasons: (1) anticipation and (2) obviousness.
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`A.
`18.
`
`Anticipation
`It is my understanding that the claims of a patent are anticipated by a prior art
`
`reference if each and every element of the claim is found either explicitly or inherently in a single
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`prior art reference or system. I understand that inherency requires a showing that the missing
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`descriptive matter in the claim is necessarily or implicitly present in the allegedly anticipating
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`reference, and that it would have been so recognized by a person of ordinary skill in the art
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`("POSITA"). In addition, I understand that an enabling disclosure is a disclosure that allows a
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`POSITA to make the invention without undue experimentation. Although anticipation typically
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`involves the analysis of a single prior art reference, I understand that additional references may be
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`used to show that the primary reference has enabling disclosure, to explain the meaning of a term
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`used in the primary reference, and/or to show that a characteristic is inherent in the primary
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`reference.
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`B.
`19.
`
`Obviousness
`I understand that the prior art may render a patent claim "obvious." I understand
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`that two or more prior art references that each disclose fewer than all elements of a patent claim
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`may nevertheless be combined to render a patent claim obvious if the combination of the prior art
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`collectively discloses all elements of the claim and one of ordinary skill in the art at the time would
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`have been motivated to combine the prior art in such a way. I understand that this motivation to
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`combine need not be explicit in any of the prior art, but may be inferred from the knowledge of
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`one of ordinary skill in the art at the time the patent was filed. I also understand that one of ordinary
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`skill in the art is not an automaton, but is a person having ordinary creativity. I further understand
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`that one or more prior art references, articles, patents or publications that disclose fewer than all
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`of the elements of a patent claim may render a patent claim obvious if including the missing
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`element would have been obvious to one of skill in the art (e.g., the missing element represents
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`only an insubstantial difference over the prior art or a reconfiguration of a known system).
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`20.
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`Under the doctrine of obviousness, a claim may be invalid if the differences
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`between the invention and the prior art are such that the subject matter as a whole would have been
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`obvious at the time the invention was made to a POSITA to which the subject matter pertains.
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`21.
`
`To assess obviousness, I understand that I am to consider the scope and content of
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`the prior art, the differences between the prior art and the claim, the level of ordinary skill in the
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`art, and any secondary considerations to the extent they exist.
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`22.
`
`I understand that any evidence of secondary indicia of non-obviousness should be
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`considered when evaluating whether a claimed invention would have been obvious to one of
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`ordinary skill at the time of invention. These secondary indicia of non-obviousness may include,
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`for example:
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`• a long felt but unmet need in the prior art that was satisfied by the claimed
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`invention;
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`• commercial success of processes claimed by the patent;
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`• unexpected results achieved by the invention;
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`• praise of the invention by others skilled in the art;
`
`•
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`the taking of licenses under the patent by others; and
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`• deliberate copying of the invention.
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`23.
`
`I understand that there must be a nexus between any such secondary indicia and the
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`claimed invention.
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`24.
`
`It is also my understanding that there are additional considerations that may be used
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`as further guidance as to when the above factors will result in a finding that a claim is obvious,
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`including the following:
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`•
`
`the claimed subject matter is simply a combination of prior art elements
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`according to known methods to yield predictable results;
`
`•
`
`the claimed subject matter is a simple substitution of one known element for
`
`another to obtain predictable results;
`
`•
`
`the claimed subject matter uses known techniques to improve similar devices
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`or methods in the same way;
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`•
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`the claimed subject matter applies a known technique to a known device or
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`method that is ready for improvement to yield predictable results;
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`
`•
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`the claimed subject matter would have been "obvious to try" choosing from a
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`finite number of identified, predictable solutions, with a reasonable
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`expectation of success;
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`•
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`there is known work in one field of endeavor that may prompt variations of it
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`for use in either the same field or a different one based on design incentives or
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`other market forces if the variations would have been predictable to a
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`POSITA;
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`•
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`there existed at the time of conception and reduction to practice a known
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`problem for which there was an obvious solution encompassed by the patent's
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`claims; and
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`•
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`there is some teaching, suggestion, or motivation in the prior art that would
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`have led a POSITA to modify the prior art reference or to combine prior art
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`reference teachings to arrive at the claimed subject matter.
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`25.
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`Finally, I understand that a claim may be deemed invalid for obviousness in light
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`of a single prior art reference, without the need to combine references, if the elements of the claim
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`that are not found in the reference can be supplied by the knowledge or common sense of one of
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`ordinary skill in the relevant art.
`
`C.
`26.
`
`CLAIM CONSTRUCTION PRINCIPLES
`I have been informed that the claims of a patent define the scope of the invention
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`and the patentee’s rights. I have been told that patent claims generally should be interpreted
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`consistent with their plain and ordinary meaning as would have been understood by persons of
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`ordinary skill in the art, after reviewing the patent claim language, the specification, and the
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`prosecution history (i.e., the intrinsic record). In this regard, I have also been told that, in order to
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`determine the proper meaning of a disputed claim term, I first look to the claim language itself,
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`the specification, and the prosecution history.
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`27.
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`I have been informed that a single claim term should be construed consistently with
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`its appearance in other places in the same claim or in other claims of the same patent, unless it is
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`clear from the specification and prosecution history that the terms have different meanings at
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`different portions of the claims.
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`28.
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`I have been informed, as a general rule, that unless a patent applicant shows an
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`intent to limit their invention, particular examples or embodiments discussed in the specification
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`are not to be read into the claims as limitations. I have also been told that the construction that
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`stays true to the claim language and most naturally aligns with the patent’s description of the
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`invention will be the correct construction.
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`29.
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`I have been informed that extrinsic evidence outside the patent and prosecution
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`history, such as expert testimony, treatises, and dictionaries, may also be considered as an aid in
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`arriving at the proper construction of a claim when a claim term is ambiguous.
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`30.
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`I understand that a patent claim is invalid as indefinite if, in light of the specification
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`and prosecution history, it fails to inform a POSITA about the scope of the invention with
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`reasonable certainty. However, I understand that reasonable certainty does not require absolute
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`precision.
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`V.
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`LEVEL OF ORDINARY SKILL IN THE ART
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`31.
`
`I have been informed that there is a concept in patent law known as a person having
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`ordinary skill in the art (“POSITA”). I have been informed that this concept refers to a person who
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`is trained in the relevant technical field of a patent without possessing extraordinary or otherwise
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`exceptional skill. Further, I have been informed that factors such as the education level of those
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`working in the field, the sophistication of the technology, the types of problems encountered in the
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`art, prior art solutions to those problems, and the speed at which innovations are made may help
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`establish the level of skill in the art.
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`32.
`
`Taking these factors into consideration, it is my opinion that a person having
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`ordinary skill in the art at the time the earliest applications for the Patents-in-suit were filed would
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`have had a bachelor’s degree in electrical, mechanical or materials engineering and two to three
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`years of experience in the design or development of semiconductor manufacturing, or the
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`equivalent. Additional graduate education could substitute for professional experience, or
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`significant experience in the field could substitute for formal education.
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`33.
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`Based on my qualifications described above, I was at least a POSITA at the time
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`the earliest application for the ’879 Patent was filed. My opinions herein are from the perspective
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`of a POSITA as of that date.
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`VI. OVERVIEW OF THE ’879 PATENT
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`34.
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`The ’879 Patent issued on March 5, 2002 and is titled “Semiconductor Device and
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`Method of Manufacturing the Same.”
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`35.
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`The ’879 Patent has four independent claims and eleven dependent claims. My
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`declaration is limited to the analysis of the independent claims. However, I reserve the right to
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`respond to other claims as may be required in the future.
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`36.
`
`Claim 1 of the ’879 Patent is for a method of manufacturing a semiconductor
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`package composed of an insulating substrate with a wiring layer and two semiconductor chips that
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`are stacked one on top of the other. (’879 Patent Ex. 1001 claim 1.)
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`37.
`
`The key invention of the ’879 Patent is the previously formed adhesion layer that
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`is adhered (i.e., attached) to the entire back surface of each semiconductor chip (i.e., the surface
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`opposite the circuit formed front surface, commonly called the active surface). The first chip is
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`attached to the substrate using the adhesion layer and the second chip is attached on top of the
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`circuit formed surface (i.e., active surface) of the first chip. Id.
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`38.
`
`This key invention of the ’879 patent eliminates the need for wire bonding the first
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`and second semiconductor chips to points on the wiring layer, far from the side surfaces of the first
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`and second semiconductor chips, considering a situation in which the excessively applied adhesive
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`agent overflows the space between the first and second semiconductor chips. (See id. at 3:19-24.)
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`This makes it possible to miniaturize the semiconductor device. (See id. at 3:25-26.)
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`39.
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`The two semiconductor chips are then wire bonded to an electrode section on the
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`substrate and sealed with a resin (i.e., encapsulated). Id.
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`40.
`
`The ’879 patent was concerned about the use of adhesive agents in the conventional
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`structure. In the conventional vertically stacked multi-chip semiconductor devices that the ’879
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`patent was concerned about, semiconductor chips are laminated, an adhesive agent (paste) potting
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`method and a method using a thermo-compression sheet are utilized for bonding the semiconductor
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`chip to the substrate, and for bonding the laminated semiconductor chips to each other.
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`(Background of the Invention, ’879 patent at 2:17-21.) Using that potting method, if the amount
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`of the adhesive agent is excessive, a large amount of adhesive agent spreads beyond the outer edge
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`of the semiconductor chip. (Id. at 2:23-25.) In Fig. 14(a) the ’879 patent, which describes the
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`conventional structure, the patent explains that an adhesive agent 87 between semiconductor chips
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`81 and 82 overflows.” (Id. at 2:23-25; see also Fig. 14(a).)
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`VII. CLAIM CONSTRUCTION
`
`41.
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`I have been asked to use the plain and ordinary meaning of the claim terms for the
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`purpose of my analysis when possible. As for the claim term “adhesion layer,” my opinion is that
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`it requires claim construction based on how it is defined in the specification. I reserve the right to
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`respond to any constructions that may later be offered by the Petitioner or adopted by the Board.
`
`A.
`42.
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`Adhesion Layer
`Claim 1 of the ’879 Patent generally requires a first/second semiconductor chip
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`having a first/second adhesion layer adhered to its back surface. ’879 Patent Ex. 1001 claim 1.
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`43.
`
`A POSITA seeing the term “adhesion layer” would recognize that there are multiple
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`methods of forming an “adhesion layer” on the back surface of the semiconductor chip.
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`44.
`
`The ’879 patent describes “the semiconductor chip 1 [] disposed with its back
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`surface facing the insulating substrate 3.” (’879 patent at 6:47-48.) “[T]he semiconductor chip 2
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`is mounted on the circuit formed surface of the first semiconductor chip 1 through a thermo-
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`compression sheet (adhesion layer) 6 ….” (Id. at 6:48-51 (emphasis added).) The “[second
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`semiconductor’s] back surface is adhered to the thermo-compression sheet 6.” (Id. at 6:51-52.)
`
`45.
`
`The specification of the ’879 Patent gives one embodiment of the “adhesion layer”
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`as a “thermo-compression sheet.” ( Id. at 6:48-52, 9:16-21, 9:29-42, 11:23-32.)
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`46.
`
`The thermo-compression sheet is adhered to the back surface of the wafer prior to
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`dicing the wafer. (Id.; 9:16-21, 9:29-42.) Therefore, after dicing the wafer the “adhesion layer”
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`is adhered to the back surface of the semiconductor chip as required by the independent claim 1.
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`47.
`
`A POSITA recognizes that the ’879 Patent’s thermo-compression sheet is a
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`previously formed thermo-compression sheet of adhesive material attached to the back surface of
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`the wafer using a combination of heat (e.g., thermo) and force (e.g., compression) that forms an
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`adhesion layer on the back surface of the wafer. The ’879 patent further distinguishes the adhesion
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`layer as being pre-formed as opposed to a liquid or semi-liquid viscous adhesive agents that are
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`coated or deposited on, which may result in overflowing or spreading out from the back surface of
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`a semiconductor chip.
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`48.
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`In describing the manufacturing method of the invention, the ’879 patent explains
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`that “In this manufacturing method … the second semiconductor chip has the insulating adhesion
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`layer adhered to its back surface in advance when being in the wafer state.” (’879 patent at 5:16-
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`17.) The ’879 patent then explains that in its manufacturing method, an “adhesive agent does not
`
`overflow the space between the first and second semiconductor chips, the second semiconductor
`
`chip can be wire-bonded to the wiring layer at a location closer to the edges of the first and second
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`semiconductor chips.” (Compare id. at 5:23-28 with id. at 2:23-48 (describing the disadvantage
`
`of using an adhesive in a conventional structure).)
`
`49.
`
`In discussing Fig. 14(a) and Fig. 14(b), the ’879 patent distinguishes between a
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`solid sheet and a liquid or semi-liquid viscous adhesive agent. (See id. at 2:23-58, Fig. 14(b).)
`
`Item 91 is a discretely placed, chip size adhesive sheet that does not overflow or underfill the back
`
`surface of the semiconductor chip while 87a is an adhesive agent that does. (Id.) This is also
`
`illustrated in Fig. 14(b).
`
`50.
`
`Claim 10 of the ’879 patent shows how the patent distinguishes between adhesion
`
`layer and adhesives. Claim 10 recites a paste applied to the wiring layer and an adhesion layer
`
`adhered to the back surface of a second semiconductor. The paste in claim 2 is the paste type die
`
`attach that I discuss below. The paste is applied to the substrate below instead of being a pre-
`
`formed layer that is adhered to the back surface of the chip that is attached to the substrate or chip.
`
`The ’879 patent also describes using this paste type die attach. (See ’879 patent at 9:26-29.)
`
`51.
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`Therefore, the term “adhesion layer” should be construed as “a pre-formed layer
`
`that is adhered.”
`
`52.
`
`[none]
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`53.
`
`Today this type of thermo-compression sheet is called a Die Attach Film (DAF) as
`
`described in the technology background section.
`
`54.
`
`In the ’879 patent, claim element 1[b] recites “a first semiconductor chip having a
`
`first adhesion layer adhered to its back surface where a circuit is not formed, said first
`
`semiconductor chip being mounted on said wiring layer through the first insulating adhesion layer”
`
`More generally the clause “a … semiconductor chip having a … adhesion layer adhered to its back
`
`surface where a circuit is not formed” appears throughout the claims. I would understand the
`
`clause “where a circuit is not formed” to modify the clause “back surface” based at least on the
`
`placement of the comma after the word “formed.” “Back surface” as modified by “where a circuit
`
`is not formed” comports with the problem the ’879 patent sought to solve—to prevent excessive
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`adhesive agent from forming a protrusion beyond the edge of the chip and interfering with the
`
`bonding pads on the substrate.
`
`VIII. DIE ATTACH TECHNOLOGY BACKGROUND
`
`55.
`
`Since the invention of semiconductor packaging the back surface of a
`
`semiconductor chip or die has been attached to a variety of substrates with some intermediate
`
`layer. Initially solders were used with a progression to various adhesives starting in the 1970s.
`
`A.
`56.
`
`Paste Type Die Attach Process
`One of the most common die attach processes is shown in Figure 1. In this process
`
`a paste or liquid die attach adhesive is dispensed on to a substrate (e.g., lead frame, ceramic or
`
`laminate substrate). The die is then placed onto the dispensed adhesive and cured typically by a
`
`thermal process.
`
`57.
`
`There are several issues with this process that needed to be addressed when moving
`
`to smaller and more complex semiconductor packaging technologies. These issues include voids
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`in the die attach adhesive interface, non-planarity of the die to the substrate, reliability and resin
`
`bleed. In particular the resin bleed or migration of the resin from under the die limited how close
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`wire bond pads could be to the edge of the die, thus increasing the package size. If the resin
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`migrates to the substrate’s wire bond pads (i.e., ’879 Patent’s electrode sections) the wire bonds
`
`would not stick.
`
`Resin bleed
`
`
`Figure 1 - Paste Type Die Attach Process
`Ex. 2003 (Materials for Advanced Packaging Book) Fig. 12.6 annotated
`
`B.
`DRAM LOC Tape Die Attach Process
`58. With the invention of Lead on Chip (LOC) packaging technology for DRAM chips,
`
`a tape-based die attach material was introduced. As shown in Figure 2 two pieces of tape were
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`used, one on each side of the die. This die attach tape was composed of a base film with an
`
`adhesive layer on each side.
`
`
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
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`Figure 2 - DRAM LOC Package with Tape Die Attach Material
`Ex. 2003 (Materials for Advanced Packaging Book) Fig. 12.7
`
`
`
`C.
`Discrete Thermo-Compression Die Attach Tape
`59. With the development of Ball Grid Array (BGA) packages and Chip Scale
`
`Packages (CSPs) the need for improved die attach materials and/or processes were required for
`
`many of the packages. Building off of the work with DRAM LOC tape adhesives, discrete die
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`attach films were developed. These discrete die attach films were placed onto the substrate and
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`then a die was placed on top of the die attach film and adhesively joined by thermo-compression.
`
`60.
`
`This type of discrete thermo-compression die attach tape is described in the
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`background section of the ’879 Patent. The inventors describe this process as requiring both the
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`accurate positioning of the thermo-compression sheet and the accurate positioning of the
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`semiconductor chip on top of the thermo-compression sheet. (’879 Patent at 3:32-37.)
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`61.
`
`The inventors of the ’879 Patent and their colleagues wrote a paper describing the
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`use of a polyimide die bonding material placed on the substrate that is non-spreading (i.e., tape).
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`
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`Page 15 of 28
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`Ex. 2001
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`

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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
`
`
`“To overcome these problems, Sharp employed an insulator adhesive made
`from a polyimide for the die bonding material. In order to improve the solder
`reflow reliability, two unique technologies in the CSP package structure were
`employed:
`(a) the creation of a through-hole, referred to as a vent hole, in the polyimide
`substrate.
`(b) the application of an insulator, which is also a die bonding material, on the
`wiring substrate to prevent it from spreading so that the vacant space between
`the polyimide substrate and the insulator is secured.”
`Ex. 2002 (Triple-Chip Stacked CSP) p.387
`D. Wafer Level Thermo-Compression Die Attach Film
`62. Wafer level die thermo-compression die attach films (DAFs) as described in the
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`’879 Patent have become common since the early 2000s. As shown in Figure 3 the wafer is placed
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`on a heat block and the Die Attach Film (DAF) is attached to the wafer using a combination of
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`heat (i.e., thermo) from the heat block and compression from the roller.
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`Roller provides “compression”
`
`Heat block provides “thermo”
`
`Figure 3 – Thermo-Compression Adhering of Die Attach Film to Wafer Backside
`Ex. 2002 (Materials for Advanced Packaging Book) Fig. 12.9 partial, annotated
`
`
`
`63.
`
`The inventors of the ’879 Patent describe one advantage of their structure as
`
`requiring the accurate placement of only the semiconductor chip as the thermo-compression film
`
`is already attached to the semiconductor chip backside. (’879 Patent at 3:37-44.)
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`
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`Page 16 of 28
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`Ex. 2001
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
`
`IX.
`
` RESPONSE TO CERTAIN STATEMENT FROM DR. SUHLING
`
`64.
`
`For claim 1, Dr. Suhling relies on U.S. Patent No. 5,323,060 (“Fogal”, Ex. 1004),
`
`U.S. Patent No. 7,166,495 (“Ball”, Ex. 1005) and International Publication WO 1996/13066
`
`(“Mostafazadeh”, Ex. 1003) alone or in combination to show obviousness. (Ex. 1002 ¶¶ 240-275.)
`
`A.
`65.
`
`Ball
`U.S. Patent No. 7,166,495 to Michael B. Ball (“Ball”) discloses a semiconductor
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`device that comprises an upper die 12 and an opposing lower die 14 which is connected to a
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`leadframe or other substrate 16. (Ball at 5:4-6, Fig. 1) The lower die 14 has a face surface 18 with
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`at least one flip chip electric connection 20 … extending from a bond pad or other terminal 22 on
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`the lower die face surface 18. (Ball at 5:7-12, Fig. 1.) Ball teaches that a back side 32 of the upper
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`die 12 is adhered to the lower die 14 with a layer of adhesive 28 applied over a lower die back side
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`30. Ball further teaches that this is an adhesive requiring a curing step, such as an epoxy, is
`
`preferred.
`
`66.
`
`Although Ball teaches several different embodiments, none of these embodiments
`
`teach a stacked semiconductor device with a lower semiconductor device having its back surface
`
`facing the substrate. All of Ball’s embodiments are of the “flip-chip” configuration for the lower
`
`semiconductor device. Ball does not disclose a second semiconductor chip whose back surface
`
`where a circuit is not formed is mounted on the back surface of said first semiconductor chip
`
`through the adhesion layer. The adhesive 28 on the back surface 32 of the second semiconductor
`
`chip 12 where a circuit is not formed does not extends to every part of the back surface 32. The
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`adhesive 28 only extends to cover a portion of the back surface 32 of the second semiconductor
`
`chip 12. Thus the second semiconductor’s 12 back surface 32 where a circuit is not formed cannot
`
`be mounted to the first semiconductor chip’s 14 through the adhesion layer since some part of the
`
`back surface 32 would not be so mounted. Thus, Ball does not disclose this limitation.
`
`
`
`Page 17 of 28
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`Ex. 2001
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`Declaration of Peter Elenius in Support of IPR2023-00073 U.S. Patent No. 6,352,879
`Katana Silicon Technologies’ Patent Owner’s Preliminary Response
`
`
`67.
`
`Dr. Suhling states; “Ball’s lower die having an adhesive backside could be used in
`
`two ways including: (1) mounting the first chip’s adhesive backside directly to a substrate in a
`
`face-up orientation, …” (Ex. 1002 ¶253.) Ball does not teach applying an adhesive to the entire
`
`backside of the die and therefore does not have an “adhesive backside.” Rather Ball teaches a
`
`standard die attach process where the adhesive is dispensed on the substrate and the die is placed
`
`in the adhesive. (Ex. 1005 2:3-5.) Dr. Suhling also states; “A POSITA would recognize that the
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`method of applying the adhesive layer in Ball is simply a design choice.” (Ex. 1000 ¶128.) Today,
`
`with more than twenty years of hind sight and experience it may be a design choice but at the time
`
`of the invention of the ’879 patent it was not a design choice even for the inventors of the ’879
`
`patent. (See ¶¶84-85)
`
`B.
`68.
`
`Fogal
`U.S. Patent No. 5,323,060 to Fogal et al. (“Fogal”) discloses a multichip module.
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`It is described as a stack 14 that “includes a first chip 18 having opposed based and bonding faces
`
`20 and 22, respectively.” (Fogal at 2:36-38.) The “base face 20 is adhered to multichip module
`
`substrate 12 by means of an adhesive, such as epoxy, thermoplastic materials, tape, tape co