`U.S. Patent No. 7,587,319
`
`Oral Argument, March 11, 2024
`
`Apple Inc. v. Zentian Limited
`Case No. IPR2023-00033
`
`Petitioner’s Demonstrative Exhibits – Not Evidence
`
`Petitioner’s DX-1
`
`IPR2023-00033
`Apple EX1045 Page 1
`
`
`
`Claim 46 and Proposed Ground I
`
`- Ground 1: Claims 46, 50, 54, 64, and 67
`- Thelen (Ex. 1030) in view of Bailey (Ex. 1031) and Chen (Ex. 1005)
`
`Claim 46:
`
`Petition (Pet.) (Paper 1), 6, 79
`
`Petitioner’s DX-2
`
`
`
`The Petition’s Mapped Combination
`
`Thelen: Speech recognizers
`organized hierarchically
`
`Bailey: Multiple recognizers
`sharing a memory
`
`Chen:
`Clustered
`processors
`with a
`shared
`memory
`
`RESULT:
`
`Storing context-related
`acoustic models efficiently
`in shared lexical memory
`
`Pet., 3, 33-37, 40-44; Schmandt Dec. (Ex. 1003), ¶ 83
`
`Petitioner’s DX-3
`
`
`
`Chen’s Clustered Processors
`Compared to ’319 Patent
`
`Chen (Ex. 1004), Fig. 4
`
`Institution Decision (Paper 10), 3,13-14; Pet., 4, 38-40, 43-45; Patent Owner Response (POR)
`(Paper 19), 4; Pet. Reply (Paper 21), 4-5
`
`Petitioner’s DX-4
`
`’319 Patent (Ex.1001), Fig. 2
`
`
`
`Motivations to Combine
`
`- Benefits
`
`Reduced
`Duplication of
`Lexical Data
`
`Lower Financial
`Cost of the
`System
`
`Increased
`Processing Power
`for a Given Cost
`
`Less Memory
`Required to
`Operate
`
`Schmandt Dec., ¶¶ 83-84; Pet., 41-44; Pet. Reply, 24-25
`
`Petitioner’s DX-5
`
`
`
`Zentian’s Unclaimed and Undescribed
`Implementation Details
`- Memory Collisions
`
`NO DISCLOSURE
`
`- Task Sharing
`
`NO DISCLOSURE
`
`- Messaging Strategy
`
`NO DISCLOSURE
`
`- Bandwidth and Latency Issues
`
`Single Sentence
`of Disclosure:
`
`Pet. Reply, 4, 13
`
`’319 Patent, 3:50-54
`
`Petitioner’s DX-6
`
`
`
`’319 Patent’s Discussion of Memory Access
`
`’319 Patent, 3:58-63
`
`Pet. Reply, 14
`
`Petitioner’s DX-7
`
`
`
`Zentian’s “Obstacles”:
`Alleged Memory Collisions
`- Chen Teaches:
`
`“Equally applicable to any type of
`parallel processing computer system”
`
`Inter-cluster memory access “does not
`have to sacrifice performance for the
`increased interconnection…provided by
`an extended shared memory model”
`
`Pet. Reply, 9, citing
`Chen, 11:33-41
`
`Tradeoffs between
`parallel processing
`performance and
`memory access
`
`Pet. Reply, 16, citing
`Chen, 5:47-53
`
`Pet., 38-40; Pet. Reply, 9, 15-16
`
`Commercially
`available
`processors
`
`Pet. Reply, 9, citing
`Chen, 10:14-35
`
`Pet. Reply, 16,
`citing Chen, 5:3-41
`
`Techniques for addressing
`memory collisions
`
`Pet. Reply, 15, citing
`Chen, 14:39–18:42
`
`Petitioner’s DX-8
`
`
`
`Zentian’s “Obstacles”:
`Alleged Reprogramming Effort
`- Chen’s Shared Memory Model
`
`Pet. Reply, 22
`
`Chen, Fig. 4 (Annotated)
`
`Pet., 39; Pet. Reply, 20-22, citing Chen, 1:56-62, 5:20-25
`
`Petitioner’s DX-9
`
`
`
`Level of Skill of a POSITA
`
`- The Parties Agree:
`
`Institution Decision, 8; Pet., 5; Pet. Reply, 5-6; POR, 5; Anderson Depo. Tr. (Ex. 1044), 9:10-12
`
`Petitioner’s DX-10
`
`Pet., 5
`
`
`
`Level of Skill of a POSITA – No Disputes
`
`- Zentian DOES NOT:
`-
`
`-
`
`
`
`Anderson Depo. Tr., 9:10-12
`
`POR, 5
`
`-
`
`
`
`Anderson Depo. Tr., 12:1-6
`
`POR, 5; Pet. Reply, 5-6, 9, citing Anderson Depo. Tr. (Ex. 1044), 9:20-10:12, 11:12-17
`
`Petitioner’s DX-11
`
`
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