Dealing with common mode current in power modules
`design and association
`
`
`F. Mérienne
`
`Laboratoire Electronique, Informatique et Image, CNRS FRE 2309
`Faculté des Sciences et Techniques, Université de Bourgogne
`BP 47870, F-21078 Dijon Cedex, France
`Phone : (33) 380395893 Fax : (33) 380395892
`
`
`and part IV will illustrate the mechanisms of common mode
`effects in a series association.
`
`
`II Chopper cell
`II.1 Description of the circuit
`The basic structure is depicted on Fig. 1a, including all
`parasitic common mode capacitors. It is composed of a power
`cell (a switch and a diode), associated with an example of
`driving circuit. During switching phase, important dV/dt will
`apply to these capacitors, being at the origin of possible
`driver disturbance, either on the phototransistor, or directly
`on the small signal transistors.
`A simplified scheme to better analyze the problem is
`proposed on Fig.1b.
`
`Ce corresponds to the more floating point (with
`respect to the base plate).
`
`Cr represents the possible path to disturb the driver.
`
`Cp is the combination of all parasitic capacitors
`between the driver ground and the base plate. To be
`noticed that in insures a kind of protection of the
`driver, since all current flowing through Cp does not
`go into Cr…
`
`
`D. Frey, JL. Schanen Member IEEE, J. Roudet
`
` Laboratoire d’Electrotechnique de Grenoble, CNRS UMR 5529
`INPG/UJF
`BP 46, F – 38402 SMH cedex, Grenoble, France.
`Phone: (33) 476826299 Fax: (33) 476826300
`David.Frey@leg.ensieg.inpg.fr
`Jean-Luc.Schanen@leg.ensieg.inpg.fr
`
`Abstract-Modern power modules will include more and more
`electronics in the same package as the power semiconductors.
`The high dV/dt generated in the module originate common
`mode currents, which can disturb the module, especially the
`driver. This paper investigates the common mode current
`generation in several cases (chopper cell, inverter arms, and
`series association) and brings layout solutions to reduce its
`effects.
`
`I Introduction
`is now well known
`that
`the
`increase of voltage
`It
`commutation speed results in non intentional capacitive
`currents, flowing through the earth and metallic base plates.
`These common mode currents originate conducted and
`radiate EMI, which are restricted by international standards
`[1]-[2]. But they can also disturb the converter itself, through
`the semiconductor driver, especially in power modules,
`where integration becomes more and more needed. Indeed,
`the integration of more electronic in the same package as the
`power switch (especially the driver), as well as the increase
`of voltage levels (and consequently dV/dt) leads to take really
`into account common mode currents in the conception or the
`association of power modules, as it will be shown in this
`paper.
`First, common mode current generation in a chopper cell will
`be investigated, and qualitative layout will be brought, in
`order to reduce its effects. Part III deals with inverter cells,
`
`
`
`
`a)
`Figure 1a) An illustration of a chopper cell b). Simplified model of the capacitive coupling
`
`b)
`
`Cr
`
`Cp
`
`Ce
`
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`
`0-7803-7420-7/02/$17.00 © 2002 IEEE
`2603
`
`Page 1 of 6
`
`Volkswagen Exhibit 1028
`
`

`

`i1
`
`ib
`
`ip
`
`Cr
`
`V
`
`Cp
`
`Ce
`
`Figure 2. Modeling of the self-perturbation process due to a
`capacitive coupling
`
`II.2 Study of driver disturbance
`During transient, the power switch is replaced by a voltage
`source (Fig. 2.). Current i1 corresponds to the polarization of
`bipolar transistor, which is reduced to base current ib, due to
`disturbance parasitic current ip.
`Based on this simple representation, it is possible to compute
`the perturbation current ip, as a function of dV/dt and
`common mode capacitances.
`
`=
`
`ip
`
`Ce
`Cr
`*
`+
`+
`Cr
`
`Cp
`
`*
`
`dV
`dt
`
`Ce
`
` (1)
`
`A criterion for well working of the driver is that the sign of ib
`must keep the same, though the presence of disturbance
`current ip.
`This is described by eq. (2):
`
`>
`
`
`
`i1
`
`Ce
`Cr
`*
`+
`+
`Cr
`
`Ce
`
`Cp
`
`*
`
`. (2)
`
`Figure 3 : Possible DBC layout for a chopper cell
`
`III Inverter cell
`
`III.1 Half bridge inverter
`The same modeling can apply for an half bridge inverter,
`taking into account the same three common mode capacitors
`(Fig. 4.), and replacing each power switch by a voltage
`source.
`The study is not as easy as for the simple chopper cell, since
`the driver 2 is submitted to voltage variation imposed by
`switch 1. Furthermore, the emitting capacitance of driver 1
`(Ce1) and the protection one for driver 2 (Cp2) are the same.
`A trade off must then be found.
`Considering that rule (2) applies for each driver leads to
`following relationships:
`
`(
`
`Cr
`
`2
`
`+
`
`+
`
`Ce
`*)1
`
`Cp
`2
`Σ
`C
`
`dV
`dt
`
`<
`
`
`
`1i
`
` and
`
`(
`
`
`
`1Cr
`
`+
`
`+
`
`Ce
`
`*)2
`
`<
`
`i
`
`2
`
`
`
`(3)
`
`dV
`dt
`
`1Cp
`
`Σ
`C
`
`dV
`dt
`
`with
`
`=Σ
`C
`
`
`
`1Cr
`
`+
`
`Cr
`
`2
`
`+
`
`
`
`1Cp
`
`+
`
`Cp
`
`2
`
`+
`
`
`
`1Ce
`
`+
`
`Ce
`
`2
`
`By neglecting the driver common mode capacitances Cr1 and
`Cr2, compared to the other ones, due to the layout, and if the
`two drivers are considered identical, Eq. (3) leads to the
`following layout rule:
`
`
`
`1Ce
`
`+
`
`Cp
`
`2
`
`=
`
`Ce
`
`2
`
`+
`
`
`
`1Cp
`
` (4)
`
`Switch2
`
`Driver2
`
`Cr2
`
`Cp2
`
`Ce2
`
`Imc2
`
`Ic
`
`Switch1
`
`Driver1
`
`Vm
`
`II.3 Qualitative layout
`To respect this condition without modifying the switching
`properties (e.g. reducing dV/dt, which would obviously
`increase commutation losses), a possible way is to decrease
`both Ce and Cr, and to increase Cp. Provided that the driver
`is fixed (e.g. i1 and Cr), the layout of Fig. 4. provides low Ce
`and high Cp, which results in a “safer” power circuit [2].
`Indeed, the major part of common mode current would be
`“recycled” in the power cell instead of going into the driver.
`This rule could be used for DBC manufacturing. In the
`example of Fig. 3, the surface of emitter track (Cp) is twice
`than the collector one (Ce). This results in capacitance in the
`same ratio. In addition, the gate track (Cr) is reduced to the
`minimum.
`Using rule (2) leads to: Ce+Cr+Cp ≈ Ce+Cp ≈ 3*Ce, thus:
`dV*Cr*
`1i >
`, with a reduced Cr. This is not difficult to
`dt
`respect…
`An extreme solution could also be to connect directly the
`power ground to the base plate, if possible. This would result
`in an infinite Cp.
`
`31
`
`Cr1
`
`Cp1
`
`Imc1
`Figure 4 : Modeling of the capacitive coupling in an
`inverter cell
`
`Ce1
`
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`
`2604
`
`Page 2 of 6
`
`

`

`
`
`
`
`
`
`DC plus
`
`DC minus
`Floating point
`
`Figure 5 : Possible DBC layout corresponding to rule (4)
`
`This means that the surface of all floating tracks must be
`equal to the one of non floating ones. This is illustrated by the
`qualitative layout of Fig. 5 [2].
`
`To be noticed in this approach that the dV/dt of each
`components are not independent, since the DC bus impose
`the total voltage. This has been taken into account in the
`calculation of Eq. (3), since the considered dV/dt for each
`driver are the same (in absolute value).
`
`Last, contrary to the chopper cell, the direct connection of
`power ground to the base plate (e.g. Cp1 infinite) would
`result in the impossibility to respect Eq. (4), and in the
`disturbance of driver. This has been verified with PSPICE
`simulations, as depicted in Fig. 6.
`
`
`
`
`III.2 Full bridge inverter
`
`An interesting case is the full bridge inverter. In this
`structure, if the two arms are switched complementary, the
`voltage variation of points A and B (Fig. 7) will be opposite.
`Consequently, to reduce common mode current emission,
`values of CA and CB should be equal, provided that dV/dt are
`the same. This lead to a symmetrical layout.
`This interesting property necessitate that the voltage slopes
`are equal. This is not so easy to reach, especially in a
`converter using discrete components. This has been
`experimentally verified (Fig. 8-b): the non synchronization of
`voltage, as well as the slope difference results in a common
`mode current generation (roughly illustrated in Fig. 8-a) [1].
`
`the
`in a single package,
`integrated
`However, when
`components dispersion can be supposed to be less important
`than in discrete packages, and voltage slopes can easier be
`equal. The driver effects on these voltage evolutions will be
`more investigated in Part IV, dealing with series association,
`where this effect has more consequences.
`
`
`E
`
`CF
`
`K3
`
`K4
`
`B
`
`K1
`
`A
`
`K2
`
`CA
`
`CB
`
`
`
`
`Figure 7. No common mode current outside the power cell if
`CA = CB…
`
`a)
`Figure 6 a) Without connection of the power ground to the base plate, b) with this connection
`(PSPICE simulated wave forms)
`
`b)
`
`
`
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`
`2605
`
`Page 3 of 6
`
`

`

`
`
`Without synchronization
`
`With synchronization
`
`a)
`Fig. 8. a) Illustration of non symmetrical slope effect on common mode current
`b) common mode current measurement with or without voltage synchronization
`
`b)
`
`Common mode current results in an increase of voltage
`variation speed of the switch located far from the base plate.
`It should be noticed that the value of parasitic capacitor must
`be compared to the one of the miller capacitor of the power
`switch, which is not very high: thus, this effect is not
`negligible. It has been confirmed experimentally, by adding
`intentional capacitors, as illustrated in Fig. 10.
`
`
`IV Series association of power components
`
`To increase the voltage capability, several switches can be
`associated in series. In this configuration, common mode
`effects are very critical, since dV/dt (with respect to the base
`plate) are cumulated [3]. Fig. 9. illustrates the basic case of
`the series association of
`two IGBTs. The reception
`capacitances Cr have here been split into two parts: one
`corresponding to the driver tracks (Cr1b and Cr2b) and the
`other one due to insulation circuit (Cr1a and Cr2a)
`
`IV.1 Direct effects of common mode capacitances
`
`As described in the previous sections, common mode currents
`can disturb the driving circuits, but even if it is not the case,
`they can modify the voltage variation speed, as it will be
`shown in this part. This dV/dt difference can lead to serious
`voltage unbalance after switching [4].
`The voltage variation speed difference can be expressed as a
`function of common mode capacitances, and IGBT intrinsic
`+
`dVds
`C
`dVds
`CK
`2
`
`ar 2
`
`br2
`∆
`=
`⋅
`⋅
`(5)
`capacitances:
`dt
`Cgd
`dt
`2
`K is a coefficient corresponding to the driver characteristics
`(see Appendix)
`
`L2
`
`Ce2
`
`Cr2a
`
`MOSFET 2
`driver
`
`Load
`L , R
`
`Switch 2
`
`L1
`
`Cr1a
`
`MOSFET 1
`driver
`
`Cr2b
`Switch 1
`
`Ce1
`
`Cp2
`
`Cr1b
`
`Cp1
`
`
`Figure 9. Series association of two transistors.
`
`MOSFET 1 turn off for several
`common mode capacities value
`
`
`
`
`
`MOS 1 0pF
`MOS 1 220pF
`MOS 1 470pF
`MOS 1 1000pF
`
`
`
`MOSFET 2 turn off for several common
`mode capacities value
`
`90
`
`80
`
`70
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`Vd
`s(
`V)
`
`MOS 2 0PF
`MOS 2 220pF
`MOS 2 470pF
`MOS 2 1000pF
`
`90
`
`80
`
`70
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`Vds (V)
`
`0
`1E-07
`
`1.2E-07 1.4E-07 1.6E-07 1.8E-07
`
`2E-07
`Time (s)
`
`2.2E-07 2.4E-07 2.6E-07 2.8E-07
`
`3E-07
`
`0
`0.0000001
`-10
`
`
`Figure 10. Effect of common mode capacitance in a series association.
`
`
`1.2E-07
`
`1.4E-07
`
`1.6E-07
`
`1.8E-07
`
`0.0000002
`
`2.2E-07
`
`2.4E-07
`
`2.6E-07
`
`2.8E-07
`
`0.0000003
`
`Time (s)
`
`
`
`2606
`
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`
`Page 4 of 6
`
`

`

`located closed to the power cell. Then, the case of series
`association is studied, where it is shown that common mode
`current can lead to voltage unbalance, due to acceleration of
`the transistor located “high” in the association. A vertical
`disposal of the modules should thus
`be preferred. It is also shown that classical ways to reduce
`common mode current (choke inductor) can lead in this case
`to worst results than the initial problem.
`
`
` VI References
`
`
`[1] JC Crebier, L.Jourdan, R.Popescu, JP.Ferrieux "Common
`Mode Disturbance Reduction of PFC Full Bridge Rectifiers",
`PESC'00, pp922-927, Vol 2
`[2] Y.Nishimura, T.Shimizu, G.Kimura, S.Igarashi "Series
`Connection Type Common-mode Current Reduction Circuit",
`IECON'99, pp278-283, Vol l
` [3] L.Bredenkamp, J-J.Nel, D.J. Mulder "Transient Voltage
`Sharing in Series Coupled High Voltage Switch", Pulse
`Power Conference Proc., San Diego, Ca, June 1991
`[4] D. Frey, P. O. Jeannin, J. L. Schanen, P. Muszicki - J.
`Saiz, M. Mermet "Optimization and Integration of an Active
`Clamping Circuit for IGBT Series Association" IAS 01,
`october 01, Chicago
`[5] Guidini, R.; Chatroux, D.; Guyon, Y.; Lafore D.
`"Semiconductor power MOSFETs devices in series", Power
`Electronics and Applications, 1993., Fifth European
`Conference on , 1993 Page(s): 425 -430 vol.2
`
`4
`
`33
`
`.5
`
`22
`
`.5
`
`11
`
`.5
`
`00
`
`.5
`
`I (A)
`
`-0.5
`
`-1
`800
`
`
`
`Vds2
`
`Vds1
`
`I
`
`100
`
`200
`
`300
`
`400
`t (ns)
`
`500
`
`600
`
`700
`
`160
`
`140
`
`120
`
`100
`
`80
`
`60
`
`40
`
`20
`
`0
`
`-20
`
`-40
`
`0
`
`Vds1 et Vds2 (V)
`
`
`
`One of the possible way to reduce this effect is to decrease
`common mode capacitances for the switches located “high”
`in the association.
`In the case of using discrete power modules or components, a
`vertical disposition leads naturally to this property. This is
`quite well known [5] but must be kept in mind for future
`developments of integrated modules: if the series association
`is considered inside a single package, the DBC layout must
`take into account this constraint.
`
`IV.2 Indirect effect
`
`To reduce common mode current effects, one well known
`way lies in the use of common mode filter: a choke inductor.
`However, this solution can lead to worst results ! Indeed,
`these filters do not suppress the common mode capacitors,
`but increase their charge duration. On Fig. 9., the inductor L2
`avoids a quick charge of parasitic capacitor Cr2a: but this
`capacitor is in parallel with the power switch 1, and will
`modify its voltage after commutation, as shown in Fig. 11.
`Therefore, a voltage unbalance is still engendered, and is
`even bigger than without L2…
`
`V Conclusion
`
`This paper investigate some possible effects of common
`mode currents in the generic case of chopper and inverter
`cells. Some interesting rules are derived from a theoretical
`analysis, which can be used for DBC layout in power
`modules, to avoid a possible disturbance of the driver unit,
`
`
`
`
`+15V
`
`Insulated
`DC/DC
`converter
`
`Cr2b
`
`Coss MOS2
`
`Coss MOS1
`
`E
`
`
`
`Fig. 11. Effect of a choke inductor on voltage unbalance in a series association.
`
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`
`2607
`
`Page 5 of 6
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`

`

`Appendix
`
`
`The following computation is achieved for two switches in
`series, but can be generalised to more components
`Vc1
`
`Ic1
`
`Ic2
`
`Vc2
`
`Vc3
`
`V1
`
`V2
`
`Ut corresponds to a rough representation of the driver (+15V
`, -5V), Ipert is the disturbance current (for instance a
`common mode current) directly injected in the gate.
`Circuit equations are:
`−
`Zge
`Ut
`Vgsth
`=
`+
`ig
`ipert
`*
`+
`+
`Rg
`Zge
`)Rg
`(
`Zge
`Or written in a different manner:
`
`dVds
`dt
`
`
`
`=
`
`*Cgd
`
`Ig/Cgd
`
`dVds
`dt
`
`−=
`
`Zge
`+
`Zge
`Rg
`
`*
`
`ipert
`Cgd
`
`−
`
`−
`Ut
`Vgsth
`+
`Rg
`Zge
`Cgd
`(*
`
`)
`
`Disturbance term
`If we now use the preceding relationships in this one, this
`leads to:
`
`
`
`
`1dVds
`dt
`dVds
`dt
`
`2
`
`=
`
`=
`
`−
`
`*2ic
`1Zge
`+
`)1Zge
`1Rg(*1Cgd
`2Zge
`*3ic
`+
`)2Zge
`2Rg(*2Cgd
`
`−
`1Ut
`
`1Vgsth
`+
`(
`1Zge
`1Cgd
`*)1Rg
`−
`Vgsth
`2
`2Ut
`−
`+
`2Cgd
`*)2Rg
`2Zge
`
`(
`
`
`And replacing ic2 and ic3 with their expressions:
`
`
`−
`
` (1)
`
`=
`
`=
`
`+
`
`Ic3
`
`Starting from this equivalent circuit, following relationships
`can be written:
`1dV
`1Ic
`1Ic
`=
`dt
`1C
`2C
`2Ic
`3Ic
`2dV
`−
` (2)
`dt
`2C
`3C
`+
`+
`=
`1Ic
`2Ic
`3Ic
`0
` (3)
`Ic2 and Ic3 can then be expressed:
`2dV*3C
`1dV*1C
`−
`dt
`dt
`
`=
`*2C2Ic
`+
`+
`3C2C1C
`−
`3C
`1dV*1C(*
`2dV*)2C1C(
`
`+
`3Ic
`)
`+
`+
`3C2C1C
`dt
`dt
`Using the approximation that C3>>C1 and C3>>C2 leads to:
`2dV*2C2Icr ≈
`
`dt
`1dV*1C(
`dt
`
`−=
`
`+
`
`2dV*)2C1C(
`+
`dt
`
`)
`
`
`
`3Icr
`
`Let us study the effect of these currents when injected
`directly on the gate.
`
`
`
`
`
`
`
`
`
`*2C
`
`
`
`1dVds
`dt
`
`=
`
`2
`
`dVds
`dt
`
`=
`
`2Ut
`+
`2Zge
`
`−
`
`(
`
`2
`
`*
`+
`
`1Zge
`
`−
`
`+
`
`*)
`
`2Zge
`
`
`
`dVds
`−
`
`1Vgsth
`1Ut
`dt
`+
`1Rg(*1Cgd
`1Cgd
`*)1Rg
`)1Zge
`(
`1Zge
`2dV*)2C1C(
`1dV*1C(
`−
`+
`dt
`dt
`+
`)2Zge
`2Rg(*2Cgd
`−
`2
`Vgsth
`2Cgd
`*)2Rg
`
`ipert
`
`Zge
`
`Rg
`
`Cgd
`
`MOS
`model
`
`Ut
`
`Vgs
`
`Vgd
`
`
`Common mode capacitance between the driver of the "low"
`IGBT and the ground is usually big. It will thus be neglected.
`As a result, this driver will not be disturbed.
`If we suppose two perfectly identical drivers, a voltage slope
`unbalance will appear, due to common mode disturbance,
`which can be expressed as:
`
`∆
`
`dVds
`dt
`
`=
`
`*2C
`1Zge
`+
`)1Zge
`1Rge
`(*1Cgd
`
`*
`
`2
`
`dVds
`dt
`
`
`
`Vds
`
`
`
`
`
`
`
`
`
`2608
`
`
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`Page 6 of 6
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