archive.org
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`
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`seconds (1997/01/26 at 04:58:28). The date indicated by an extended URL applies
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`
`Page 1 of 28
`
`Volkswagen Exhibit 1036
`
`

`

` archive.org
`
`
`
`
`
`
`
`
`
`6. Attached hereto as Exhibit B are true and accurate copies of the Internet Archive's
`records of the archived files for the URLs and the dates specified in the attached
`coversheet of each file.
`
`7. I declare under penalty of perjury that the foregoing is true and correct.
`
`
`
`
`DATE: ________________________
`
`
`________________________
`Nathaniel E Frank-White
`
`August 31, 2022
`
`Page 2 of 28
`
`

`

`
`
`
`
`
`EXHIBIT B
`
`EXHIBIT B
`
`Page 3 of 28
`
`Page 3 of 28
`
`

`

`https://web.archive.org/web/20061211200334/http:/datasheets.maxim-ic.com/en/ds/MAX5088-MAX5089.pdf
`
`Page 4 of 28
`
`

`

`sa50
`
`MAAAI
`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`680SXVIN/880SXVIN
`
`Features
`General Description
`The MAX5088/MAX5089 high-frequency, DC-DC con-
`@ 4.5V to 5.5V or 5.5V to 23V Input Voltage Range
`¢ Output Voltage Adjustable Downto 0.6V
`verters with an integrated n-channel power MOSFET
`provide up to 2A of load current. The MAX5088
`@ 2A Output Current
`includes an internal power MOSFETto enable the
`# Synchronous Rectifier Driver Output (MAX5089)
`design of a nonsynchronous buck topology power sup-
`for Higher Efficiency
`ply. The MAX5089is for the design of a synchronous
`buck topology power supply. These devices operate=@ Resistor-Programmable Switching Frequency
`from a 4.5V to 5.5V or 5.5V to 23V input voltage and a
`from 200kHzto 2.2MHz
`200KHz to 2.2MHz resistor-programmable switching
`frequency. The voltage-mode architecture with a peak
`# External Synchronization and Enable (On/Off)
`:
`nam
`:
`:
`Inputs
`5
`switch current-limit scheme provides stable operation
`up to a 2.2MHz switching frequency. The MAX5088=® Clock Output for Driving Second Converter 180
`includes a clock output for driving a second DC-DC
`Out-Of-Phase (MAX5089)
`converter 180° out-of-phase and a power-on-reset
`¢ Integrated 150mQ High-Side n-Channel Power
`(RESET) output. The MAX5089includes a power-good
`MOSFET
`output and a synchronousrectifier driver to drive an
`# Power-On Reset Output (MAX5088)/Power-Good
`external low-side MOSFET in the buck converter config-
`Output (MAX5089)
`put
`(
`)
`uration for high efficiency.
`The MAX5088/MAX5089
`tact
`inst
`'
`¢ Short-Circuit Protection
`e
`protect against overcurren
`conditions by utilizing a peak currentlimit as well as
`® Thermal-Shutdown Protection
`overtemperature shutdown providing a veryreliable
`¢ Thermally Enhanced 16-Pin TQFN Package
`and compact power sourcefor point-of-load regulation
`Dissipates 2.7W
`applications. Additional features include synchroniza-
`tion, internal digital soft-start, and an enable input. The TTC
`MAX5088/MAX5089 are available in a thermally
`enhanced, space-saving 16-pin TQFN (5mm x 5mm)
`package and operate over the -40°C to +125°C tem-
`perature range
`
`
`
`Ordering Information
`PIN-
`PKG
`PACKAGE
`CODE
`TEMP RANGE
`-40°C to+125°C 16 TQFN
`T1655-2
`-40°C to+125°C 16 TQFN
`T1655-2
`
`PART
`MAX5088ATE+
`MAXS5089ATE+
`
`Applications
`
`xDSL Modem PowerSupply
`Automotive Radio Power Supply
`Servers and Networks
`
`IP Phones/WLANAccessPoints
`
`+Denotes lead-free package.
`
`Pin Configurations
`
`TOP VIEW
`
`5mm x 5mm
`
`Selector Guide
`
`PART
`
`CONFIGURATION
`
`FEATURES
`
`Nonsynchronous
`
`RESET Output,
`
`
`
`PGOODOutput,
`
`MAX5089ATE|Synchronous Buck Synchronous FET
`Driver
`
`Pin Configurations continued at end of data sheet.
`
`THIN QFN
`
`MAXIAA
`
`Maxim Integrated Products
`
`1
`
`Forpricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
`1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
`Page 5 of
`28
`
`

`

`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`ABSOLUTE MAXIMUM RATINGS
`V+ to PGND 200... ceeececceccccceccceesscesceessseesecessseeseeesseeees-0.3V to +25V
`BST/VDD, DRAIN to SGND....0........ecece-0.3V to +30V
`SGNDto PGND..0...0..0cccccceccececesceeeeeeeseeseeeeeeseees-0.3V to +0.3V
`BST/VDD to SOURCE..........cccccecccesseeseeseesceeeeeeeeeees-0.3V to +6V
`SOURCEto SGND..........ccceceeeccccecsceseessceseeseeeseeeee-0.6V to +25V
`SOURCE or DRAIN Maximum Peak Current...............5A for ims
`VL to SGND.................-0.3V to the lower of +6V and (V+ + 0.3V)
`SYNC, EN, DL, CKO, OSC, COMP,
`FB to SGND...... occ eeeececccesccecceseeessesseeseenee-0.3V to (VL + 0.3V)
`BYPASS, CKO, OSC, COMP,FB, EN, SYNC, RESET,
`PGOOD Maximum Input Current........0...000:ceeeeeeeee +50mA
`
`*As per JEDEC51 Standard (multilayer board).
`
`RESET, PGOODto SGND....0...cee cece-0.3V to +6V
`BYPASSto SGND...........ccccccccccceceeseessesseeseeseeeseeees-0.3V to +2.2V
`V_ and BYPASS Short-Circuit Duration to SGND......Continuous
`Continuous PowerDissipation* (Ta = +70°C)
`16-Pin TQFN (derate 33mW/°C above +70°C)..........2666mW
`Package ThermalResistance(junction to case)............ 1.7°C/W
`Operating Temperature Range...-40°C to +125°C
`Junction Temperature Range............::..ceeeee-65°C to +150°C
`Storage Temperature Range............:.:eceeeeee-65°C to +150°C
`Lead Temperature (soldering, 10s) ........0..0..c:csceeeeeeeeee +300°C
`
`Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damageto the device. These are stress ratings only, and functional
`operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
`absolute maximum rating conditions for extended periods mayaffect devicereliability.
`
`ELECTRICAL CHARACTERISTICS
`
`MAX5088/MAX5089
`
`-40°C to +125°C, unless otherwise noted.Circuits of Figures 5 and 6. Typical
`
`(V+ = VL = 5V or V+ = 5.5V to 23V, VEN = 5V, TA= Ty =
`values are at Ta = Ty = +25°C.) (Note 1)
`
`
`PARAMETER sympoL_| CONDITIONS|MIN MAX|UNITS|TYP
`
`SYSTEM SPECIFICATIONS
`Input Voltage Range aOe
`V+OperatingSupplyCurrent —Rosc=10kQ,noswitching
`1.8
`2.5
`Ve=MtT
`V+ = 12V, VFB = 0.8V
`
`.
`
`: A
`
`V+ Standby Supply Current
`
`Efficienc'*
`
`V+ = 12V, Ven = OV, PGOOD (MAX5089),
`RESET, CKO unconnected (MAX5088),
`Rosc = 10kQ
`
`Nonsynchronous (MAX5088),
`fsw = 1.25MHz, V+ = 12V, lout = 1.5A,
`Vout = 3.3V
`Synchronous (MAX5089),
`fsw = 300kHz, V+ = 12V, lout = 1.5A,
`VouT = 3.3V
`
`1
`
`1.4
`
`mA
`
`Vi REGULATOR(VL)/BYPASS OUTPUT (BYPASS)
`Vi Undervoltage Lockout
`Vi falling
`
`VL Undervoltage Lockout pw
`
`VL Output Voltage
`BYPASS Output Voltage
`
`.
`BYPASSLoad Regulation
`
`V+ = 5.5Vto 23V,Iv = 0 to 40mA
`V+ =V_=5.2V
`
`IBYPASS steps from 0 to 50uA,
`V+ =Vi=5.2V
`
`50
`1.98
`
`0
`
`52
`2
`
`1.2
`
`55
`2.02
`
`10
`
`mV
`
`
`
`MAXIM
`
`Page 6 of 28
`
`

`

`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`ELECTRICAL CHARACTERISTICS(continued)
`(V+ = VL = 5V or V+ = 5.5Vto 23V,VEN = SV, Ta = Ty = -40°C to +125°C, unless otherwise noted. Circuits of Figures 5 and 6. Typical
`values are at Ta = Ty = +25°C.) (Note 1)
`
`
`SOFT-START
`
`PARAMETER SYMBOL|CONDITIONS|~MIN TYP MAX
`
`
`
`Digital Soft-StartPeriod P| Internal6-bitDAC
`
`periods
`[SotStanSepsiPSiS|
`ERROR AMPLIFIER (FB and COMP)
`[FBtoCOMPTransconductance|gu[SSSVCS
`
`FFBinputBiasCurent[kp[On
`
`
`
`
`[FBinputVotiageSetPoint[|Vea|———=—SCSCS~SSOHOO.GOTDGGE_V_|
`COMPSink-and-Source Current
`
`Capability|tcfofmw]|
`
`680SXVIN/880SXVIN
`
`fsw = 2.2MHz
`
`INTERNAL MOSFETs
`
`On-Resistance n-Channel Power
`
`VEN = OV, VDRAIN = 23V,
`
`Minimum Output Current
`Current Limit
`
`VouT = 3.3V, V+ = 12V (Note 2)
`Pour2 2885
`
`SYNCHRONOUSRECTIFIER DRIVER (DL) (MAX5089 Only)
`[OnResistancenMOS[Ronn [Isnk=0.1A——S—~—~—S.SSC‘SC‘CC
`
`|On-ResistancepMOS|Ronpip_|Isounce=O.1A|tt|
`
`[PeakSinkCurrent|sinkfo
`
`
`[PeakSourceCurent[insounce|SCSSSCCOC~*dYSC(CACS?
`OSCILLATOR (OSC)/SYNCHRONIZATION (SYNC)/CLOCK OUTPUT (CKO) (MAX5088 Only)
`
`[ClockOutputHighLevel|Veo [Wi=52V,Isounce=SmA|354|
`
`2400
`
`[GeekOupttowte——[Voxon w=tensaPo2100
`
`
`
`
`SwitchingFrequency =VL=5.Rose=i [95912950 kHz
`[MinimumControllableOn-Time|tonminfoaa
`
`1130
`
`1250
`
`1380
`
`Maximum Duty Cycle
`
`MAXIM
`
`
`
`3
`
`Page 7 of 28
`
`

`

`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`ELECTRICAL CHARACTERISTICS(continued)
`(V+ = VL = 5V or V+ = 5.5Vto 23V,VEN = SV, Ta = Ty = -40°C to +125°C, unless otherwise noted. Circuits of Figures 5 and 6. Typical
`values are at Ta = Ty = +25°C.) (Note 1)
`
`
`
`
`
`
`
`PARAMETER MAX|UNITSSYMBOL MIN TYP
`
`
`
`MAX5088/MAXS089
`
`SYNC Frequency Range
`
`Sync Input to SOURCERising-
`_
`_
`
`
`
`Edge PhaseDelay (Note 4) SYNCPHASE|Rosc = 10k, fsync = 1.2MHz 65 degrees
`
`
`
`Clock Output Phase Delay With
`Respect to SOURCE Waveform
`(Note 5)
`SYNC High Threshold|VsyncH[|
`SYNC Low Threshold
`
`Rosc = 10kQ, SYNC = GND
`(MAX5088only)
`
`EN, RESET (MAX5088)/PGOOD (MAX5089)
`vn
`IL
`
`EN Threshold
`
`>
`
`90
`
`90
`
`925
`
`925
`
`95
`
`95
`
`; o|
`
`8 z
`
`VeB = VouT
`
`VrB = VouT
`
`SINK = 3mA
`
`V+ = V_ = 5.2V, VRESET or
`VPGOOD= 6V, VFB = 0.8V
`
`t
`
`FD
`
`L K
`
`Temperaturerising
`
`+170
`
`°
`
`QO
`
`°sis
`
`EN Input Bias Current
`
`RESETThreshold (Note 6)
`
`PGOODThreshold (Note 6)
`FB to RESET or FB to PEOOD
`Propagation Delay
`RESETActive Timeout Period
`
`RESET, PGOOD OutputVoltage
`
`RESET, PGOOD Output Leakage
`Current
`
`THERMAL SHUTDOWN
`
`Thermal Shutdown
`
`Note 1: 100% tested at +125°C. Limits over temperature are guaranteed by design.
`Note 2: Output current may belimited by the powerdissipation of the package. See the PowerDissipation section in the Applications
`Information section.
`Note 3: SYNCinput frequencyis equalto the switching frequency.
`Note 4: From the SYNCrising edge to SOURCErising edge.
`
`Note 5: From the rising edge of the SOURCE waveform tothe rising edge of the CKO waveform.
`Note 6: RESET goeshigh 200msafter VouT crossesthis threshold, P@OOD goeshigh after VouT crossesthis threshold.
`
`4
`
`Page 8 of 28
`
`MAXKUM
`
`

`

`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`Typical Operating Characteristics
`(V+ = VL = 5.2V, Ta = +25°C, Figures 5 and 6, unless otherwise noted.)
`
`MAX5088 BUCK EFFICIENCY vs. OUTPUT
`CURRENT (Vin = 5V, fsw = 2.2MHz)
`
`MAX5088 BUCK EFFICIENCY vs. OUTPUT
`CURRENT (Vin = 12V, fsw = 2.2MHz)
`
`MAX5088 BUCK EFFICIENCY vs. OUTPUT
`CURRENT (VIN = 16V,fsw = 2.2MHz)
`
`
`
`
`
`
`
`EFFICIENCY(%)
`
`EFFICIENCY(%)
`
` EFFICIENCY(%)
`
`
`
`
`
`
`
`
`
`
`
`680SXVIN/880SXVIN
`
`
`
`
`
`
`
`0 2000+2500500 1000 1500 2000 2500 0 500 1000 +1500 0 500 1000 1500 2000 2500
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`OUTPUT CURRENT (mA)
`OUTPUT CURRENT (mA)
`OUTPUT CURRENT (mA)
`
`MAX5089 SYNCHRONOUS EFFICIENCY vs. OUTPUT
`CURRENT (Vin = 12V, fsw = 2.2MHz, L = 4.7:H)
`80
`1
`70
`
`
`
`
`
`
`0
`
`500
`
`1500
`1000
`OUTPUT CURRENT (mA)
`
`2000
`
`2500
`
`Vi OUTPUT VOLTAGE
`vs. SWITCHING FREQUENCY
`
`
`
`
`
`z°
`>
`z 55
`oO
`i 50
`45
`40
`35
`30
`
`5.190
`5.185
`
`5.180
`5.475
`
`s
`= 5.170
`5.165
`5.160
`
`5.155
`
`5.150
`
`MAX5089 SYNCHRONOUS
`EFFICIENCY vs. OUTPUT CURRENT
`(Vin = 12V, fsw = 330kHz, L = 15yH)
`
`
`
`«
`
`
`
`
`
`0
`
`500
`
`1500
`1000
`OUTPUT CURRENT (mA)
`
`2000
`
`2500
`
`95
`90
`85
`
`zm
`>
`zg”
`oO
`= 70
`6
`60
`55
`50
`
`MAX5089 OUTPUT VOLTAGE vs. OUTPUT
`CURRENT (Vin = 12V, Vout = 3.3V, fsw = 2.2M
`.
`
`
`
`
`
`
`
`_
`
`=w
`
`=
`Ss
`5
`
`= =
`
`0
`
`MAXI
`
`2000
`
`1500
`1000
`500
`«©6600—Ss«*1100.-—='s«1600—S«2100
`OUTPUT CURRENT (mA)
`SWITCHING FREQUENCY(kHz)
`5
`
`100
`
`Page 9 of 28
`
`

`

`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`Typical Operating Characteristics (continued)
`(V+ = VL =5.2V, Ta = +25°C, Figures 5 and6, unless otherwise noted.)
`
`MAX5089 V_ DROPOUT VOLTAGE
`vs. SWITCHING FREQUENCY
`
`SWITCHING FREQUENCY
`SWITCHING FREQUENCY
`vs. TEMPERATURE
`2350
`10,000
`
`
`
`
`
`s
`=
`=
`3
`& 1000
`a
`=
`
`
`
`
`
`
`2100
`1850
`
`= 1600
`=
`& 1350
`> 1100
`B
`= 950
`600
`350
`
`0.350
`= 030
`3
`0250
`S
`5 0200
`S 0.150
`=”
`> 0.100
`0.050
`
`MAX5088/MAXS089
`
`
`
`
`
`
`
` 0.400
`
`
`
`
`100mV/div
`
`
`100©600.«ss1100.-«Sss“1600-~—200 0 10 2 30 40 50 60 70 -40 10 60 110
`
`100
`100
`0
`
`
`
`
`
`SWITCHING FREQUENCY(kHz)
`RESISTANCE(ka)
`TEMPERATURE(°C)
`
`
`
`
`
`MAX5089 LINE-TRANSIENT RESPONSE
`(lout = 1A, VIN STEP = 14V TO 21V)
`‘MAXS088/89toc!
`
`MAX5089 LOAD-TRANSIENT RESPONSE
`(lout = 0.2A TO 1A)
`(5068/89
`
`100ys/div
`
`MAX5089 LOAD-TRANSIENT RESPONSE
`‘MAXS088/89toct3
`(lout = 0.5A TO 2A)
`
`MAX5089 SOFT-START AND SHUTDOWN
`(NO LOAD)
`
`5V/div
`
`200mV/div
`
`200mV/div
`
`1A/div
`
`oA
`
`SOO
`0A
`
`1V/div
`
`ov
`
`SV/div
`ov
`
`Vout
`
`\
`
`our
`
`
`
`6
`
`MAXIMA
`
`Page 10 of 28
`
`ims/div
`
`

`

`680SXVIN/880SXVIN
`
`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`Typical Operating Characteristics (continued)
`(V+ = VL =5.2V, Ta = +25°C, Figures 5 and6, unless otherwise noted.)
`
`MAX5089 SOFT-START AND SHUTDOWN
`(lout = 2A)
`5088/89 tol
`
`Vin STARTUP WAVEFORM
`(EN CONNECTED TO V1)
`SDB8/88
`
`RESET TIMEOUT
`
`;
`
`1V/div
`
`wv
`
`¢ 5V/div
`ov
`
`ims/div
`
`4ms/div
`
`Vex.
`Swidiv
`Vout
`2Vidiv
`
`VIN
`
`VpgooD
`SVidiv
`
`Ve
`or
`
`VRESET
`
`Vin
`10V/div
`
`’
`
`40ms/div
`
`MAX5088 EXTERNALLY SYNCHRONIZED
`SWITCHING WAVEFORM
`
`SHUTDOWN CURRENT
`vs. TEMPERATURE
`
`MAXS068/89 toc17
`
`10V/div
`
`.
`2Vidiv
`
`5V/div
`
`
` SHUTDOWN
`ee
`
`
`
`CURRENT(1A) S8
`
`
`
`350
`
`300
`
`-40
`
`60
`10
`TEMPERATURE(°C)
`
`110
`
`CURRENT LIMIT
`vs. TEMPERATURE
`
`
`
`=
`e
`
`=
`=
`=
`=
`3
`
`5V/div
`ov
`
`5V/div
`ov
`
`10V/div
`ov
`
`500mV/div
`
`100ns/div
`
`SWITCHING SUPPLY CURRENT(Isw)
`vs. TEMPERATURE
`
`
`
`Vsource
`
`Vout
`
`=52
`
`a
`©
`x
`3
`an
`2
`a
`
`S=n
`
`50
`
`-25
`
`75
`2 50
`0
`TEMPERATURE(°C)
`
`100
`
`125
`
`-40
`
`60
`10
`TEMPERATURE(°C)
`
`110
`
`MAXUM
`
`
`
`7
`
`Page 11 of 28
`
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`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`Pin Description
`
`DRAIN
`
`Internal Power MOSFET Drain Connection. Use the MOSFET asa high-side switch and connect DRAIN to the
`input supply.
`
`‘
`
`3
`
`5
`
`COMP
`
`OSC
`
`Transconductance Error Amplifier Output. Connect a compensation network from COMP to SGNDorfrom
`COMPto FB to SGND(see the Compensation section).
`|4[FB|FeedbackInput. Connecta resistive divider from the output to FB to SGNDto setthe outputvoltage.
`Switching Frequency Set Input. Connecta resistor Rosc from OSC to SGNDto set the switching frequency.
`Whenusing external synchronization, program Rosc sothat (0.2 x fgsync) $ fsw s (1.2 x fsync). Rosc isstill
`required when external synchronization is used.
`|6|BYPASS|Reference Bypass Connection. Bypass to SGND with a 0.22uF or greater ceramic capacitor.
`Input Supply Voltage. V+ can range from 5.5V to 23V. Connect V+ and V\_ togetherfor 4.5V to 5.5V input
`operation. Bypass V+ to SGND with a minimum of 0.1yF ceramic capacitor.
`
`MAX5088/MAX5089
`
`Internal Regulator Output. Bypass VL to SGND with a 4.7yF ceramic capacitor and to PGNDwith a 0. 1pF
`ceramic capacitor. Connect V+ to Vi for 4.5V to 5.5V operation.
`Clock Output (MAX5088 Only). CKO is an output with the same frequency as the converter’s switching
`frequency and 115° out-of-phase. CKO is used to synchronize the MAX5088 to other MAX5088/MAX5089s.
`
`Low-Side SynchronousRectifier Driver (MAX5089 Only). DL sources 0.7A and sinks 1A to quickly turn on and
`i
`off the external synchronousrectifier MOSFET.
`
`CK
`
`DL
`
`SGND_|Signal Ground
`
`PowerGround. Connecttherectifier diode’s anode,the input capacitor negative terminal, the output capacitor
`negative terminal, and V_ bypass capacitor negative terminal to PGND.
`Internal Power MOSFET Source Connection. Connect SOURCEto the switched side of the inductor as shownin
`
`12|SOURCE| ~.
`Figure5.
`External Synchronization Input. Connect SYNCto an external logic-level clock to synchronize the MAX5088/
`MAX5089. Connect SYNC to SGND whennot used.
`
`SYNC
`
`13
`
`Open-Drain Active-Low Reset Output (MAX5088 Only). RESET remains low while the converter’s outputis
`RESET|below 92.5% of VouT’s nominalset point. When VouT rises above 92.5% ofits nominal set point, RESET goes
`high after the reset timeout period of 200ms(typ).
`
`PGOOD Open-Drain Power-Good Output (MAX5089 Only). PGOOD remains low while the output is below 92.5% ofits
`nominalset point.
`
`Internal MOSFET Driver Supply Input. Connect BST/VDDto an external ceramic capacitor and diode (see
`BSTNDD Figure5).
`Enable Input. A logic-low turns off the converter. A logic-high turns on the device. Connect ENto V,_ for an
`always-on application.
`
`—|—— ExposedPad.ConnecttoSGND.SolderEPtoSGNDtoenhancethermaldissipation.
`
`8
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`Page 12 of 28
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`MAXKUM
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`

`

`680SXVIN/880SXVIN
`
`
`
`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`
`
`Figure 1. MAX5088 Block Diagram
`
`MAXIM
`
`
`
`9
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`Page 13 of 28
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`Integrated High-Side Switch
`
`
`
`MAX5088/MAXS089 2.2MHz, 2A Buck Converters with an
`
`
`
`Figure 2. MAX5089 Block Diagram
`
`10
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`Page 14 of 28
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`MAK
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`

`

`680SXVIN/880SXVIN
`
`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`Detailed Description
`
`PWM Controller
`The MAX5088/MAX5089 use a pulse-width modulation
`(PWM) voltage-mode control scheme. The MAX5088 is
`a nonsynchronous converter and uses an external low-
`forward-drop Schottky diodeforrectification. The
`MAX50839is a synchronous converter and drives a low-
`side, low-gate-charge MOSFETfor higherefficiency.
`The controller generates the clock signal from an inter-
`nal oscillator or the SYNC input when driven by an
`external clock. An internal transconductance error
`amplifier produces an integrated error voltage at
`COMP,providing high DC accuracy. The voltage at
`COMPsets the duty cycle using a PWM comparator
`and an internal 1Vp-_p voltage ramp. At each rising
`edge of the clock, the converter’s high-side n-channel
`MOSFETturns on and remains on until either the
`appropriate or maximum duty cycle is reached or the
`maximum currentlimit for the switch is detected.
`
`MAX5088
`During each high-side MOSFET on-time (Figure 5), the
`inductor current ramps up. During the second half of
`the switching cycle, the high-side MOSFET turnsoff and
`forward biases the Schottky rectifier (D2 in Figure 5).
`During this time, the SOURCEvoltage is clamped to
`0.5V below ground. The inductor releases the stored
`energy as its current ramps down,and provides current
`to the output. During the MOSFET off-time, when the
`Schottky rectifier is conducting, the bootstrap capacitor
`(C10 in Figure 5) is recharged from the VL output. At
`light loads, the MAX5088 goesin to discontinuous con-
`duction modeoperation whenthe inductor current com-
`pletely discharges before the next switching cycle
`commences. When the MAX5088operatesin discontin-
`uous conduction, the bootstrap capacitor can become
`undercharged.To preventthis, an internal low-side 30Q
`switch (see NSin Figure 1) turns on, during the off-time,
`once every 4 clock cycles. This ensures that the nega-
`tive terminal of the bootstrap capacitor is pulled to
`PGND often enoughto allow it to fully charge to VL,
`ensuring the internal power switch properly turns on.
`The operation of the bootstrap capacitor wake-up
`switch causes a small increase in the output voltagerip-
`ple at light loads. Under overload conditions, when the
`inductor current exceeds the peak current limit of the
`internal switch, the high-side MOSFET turnsoff quickly
`andwaits until the next clock cycle.
`
`MAX5089
`The MAX50839is intended for synchronous buck opera-
`tion only. During the high-side MOSFET on-time, the
`inductor current ramps up. When the MOSFET turnsoff,
`the inductor reverses polarity and forward biases the
`Schottky rectifier in parallel with the low-side synchro-
`nous MOSFET. The SOURCEvoltage is clamped to
`0.5V below ground until the break-before-make time
`(tBBM) of 25nsis over. After t8BM, the synchronousrec-
`tifier MOSFET turns on. The inductor releases the
`stored energy as its current ramps down, and contin-
`ues providing current to the output. The bootstrap
`capacitor is also recharged from the VL output when
`the MOSFET turnsoff. The synchronousrectifier keeps
`the circuit in continuous conduction mode operation
`evenatlight load. Under overload conditions, when the
`inductor current exceeds the peak currentlimit of the
`internal switch, the high-side MOSFETturns off and
`waits until the next clock cycle.
`The MAX5089,with the synchronousrectifier driver out-
`put (DL), has an adaptive break-before-make circuit to
`avoid cross conduction between the internal power
`MOSFET andthe external synchronousrectifier MOSFET.
`Whenthe synchronousrectifier MOSFET is turning off,
`the internal high-side power MOSFET is kept off until
`VpbLfalls below 0.97V. Similarly, DL does not go high
`until the internal power MOSFET gate voltagefalls
`below 1.24V.
`
`Input Voltage (V+)/Internal Linear
`Regulator (VL)
`All internal control circuitry operates from an internally
`regulated nominal voltage of 5.2V (VL). At higher input
`voltages (V+) of 5.5V to 23V, VL is regulated to 5.2V. At
`5.5V or below, the internal linear regulator operates in
`dropout mode, where V_ follows V+. Depending on the
`load on VL, the dropout voltage can be high enough to
`reduce VL to below the undervoltage lockout (UVLO)
`threshold.
`
`For input voltages of lower than 5.5V, connect V+ and
`VL together. The load on VLis proportional to the
`switching frequency of the converter. See the VL
`Output Voltage vs. Switching Frequency graph in the
`Typical Operating Characteristics. For an input voltage
`higher than 5.5V, use the internal regulator.
`Bypass V+ to SGND with a low-ESR 0.1uF or greater
`ceramic capacitor placed as close as possible to the
`MAX5088/MAX5089. Current spikes from VL disturb the
`internal circuitry powered by VL. Bypass VL with a low-
`ESR 0.1pF ceramic capacitor to PGND and a low-ESR
`4.7uF ceramic capacitor to SGND.
`
`MAXKLM
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`Page 15 of 28
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`

`MAX5088/MAX5089
`
`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`Enable
`EN is an active-high input that turns the MAX5088/
`MAX5089 on andoff. EN is a TTL logic input with 2.0V
`and 0.8V logic-high andlow levels, respectively. When
`EN is asserted high, the internal digital soft-start cycle
`slowly ramps up the internal reference and provides a
`soft-start at the output. This hysteresis provides immuni-
`ty to the glitches during logic turn-on of the converter.
`Voltage variation at EN can interrupt the soft-start
`sequence and can cause a latch-up. Ensure that EN
`remains high for at least 5ms onceit is asserted. Force
`
`EN low to turn off the internal power MOSFET and cause
`RESET to pull low (MAX5088) or cause PGOODto pull
`low (MAX5089). Connect EN to VL when not used.
`
`Soft-Start/Soft-Stop
`The MAX5088/MAX5089 include undervoltage lockout
`(UVLO) with hysteresis to prevent chattering during
`startup. The UVLO circuit holds the MAX5088/MAX5089
`off until V+ reaches 4.5V and turns the devicesoff
`when V+ falls below 4.3V. The MAX5088/MAX5089 also
`offer a soft-start feature, which reduces surge currents
`and glitches on the input during turn-on. During turn-on
`when the UVLOthreshold is reached or EN goes from
`low to high, the digital soft-start ramps up the reference
`(VBYPASS) in 64 steps. During a turn-off (by pulling EN
`or V+ low), the reference is reduced to zero slowly. The
`soft-start and soft-stop periods (tss) are 4096 cycles of
`the internal oscillator. To calculate the soft-start/soft-
`stop period usethefollowing equation:
`
`tss
`
`_ 4096
`fsw
`
`fsw is the switching frequency of the converter.
`
`Oscillator/Synchronization
`(SYNC)/Clock Output (CLKOUT)
`The clock frequency (or switching frequency) is gener-
`ated internally and is adjustable through an external
`resistor connected from OSC to SGND.Therelationship
`between Rosc andfswis:
`
`Rosc
`
`_ 125x108Q/s
`fsw
`
`The adjustment range for fsw is from 200kHz to
`2.2MHz.
`
`Connecta logic-level clock between 200kKHz to 2.2MHz
`at SYNC to externally synchronize the MAX5088/
`MAX5089’s oscillator (see Figure 7). The MAX5088/
`MAX5089 synchronizeto the rising edge of the SYNC
`clock. The rising edge of the SYNC clock correspondsto
`
`the turn-on edgeofthe internal n-channel power MOSFET
`with a fixed propagation delay. When operating the
`MAX5088/MAX5089 with an external SYNC clock, Rosc
`must be installed. Program the internal switching fre-
`quency so that (0.2 x fsyNc) < fsw < (1.2 x fsyNc). The
`minimum pulse width for fSyNC is 100ns. Connect SYNC
`to SGNDif synchronization is not used.
`The CKO output (MAX5088 only) is a logic-level clock
`with the same frequency as fsw and with 115° phase
`shift with respect to SYNC clock. Two MAX5088s can
`be connected in a master/slave configuration for two-
`phase (180°) interleaved operation. The CKO output of
`the master drives the SYNC input of the slave to form a
`dual-phase converter. To achieve the 180° out-of-phase
`operation, program theinternal switching frequency of
`both converters close to each other by using the same
`Rosc value. When synchronizing the master-slave con-
`figuration using external clock, program the internal
`switching frequency using ROSC close to the external
`clock frequency (fSYNC) for 180° ripple phase operation
`(see Figure 7). Any difference in the internal switching
`frequency and fSYNC changesthe phase delay. If both
`master and slave converters use the same power
`source, and share input bypass capacitors, the effec-
`tive switching frequencyat the input is twice the switch-
`ing frequencyof the individual converter. Higher ripple
`frequency at the input capacitor means a lower RMS
`ripple current into the capacitor.
`
`CurrentLimit
`The MAX5088/MAX5089 protect against output over-
`load and short-circuit conditions when operated in a
`buck configuration. An internal current-sensing stage
`develops a voltage proportional to the instantaneous
`switch current. When the switch current reaches 2.8A
`(typ) the power MOSFETturns off and remainsoff until
`the next on cycle.
`During a severe overload or short-circuit condition when
`the output voltage is pulled to ground the discharging
`slope of the inductor is VDs (the voltage across the syn-
`chronous FET), or VF (the voltage acrossthe rectifying
`diode) divided by L. The short off-time does not allow
`the current to properly ramp downin the inductor, caus-
`ing a dangerous current runaway and possibly destruc-
`tion of the device. To prevent this, the MAX5088/
`MAX5089include a frequency foldback feature. When
`the currentlimit is detected the frequencyis reducedto
`1/4th of the programmedswitching frequency. When the
`output voltage falls below 1/3rd of its nominal set point
`(VFB = 0.2V) the converter is turned off and soft-start
`cycle is initiated. This reduces the RMS current sourced
`by the converter during the fault condition.
`
`
`
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`Page 16 of 28
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`

`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`the device on again whenthe die temperature reduces
`by +25°C. During thermal shutdown,the internal power
`
`MOSFET shuts off, DL pulls to SGND, Vi shuts down,
`RESET (MAX5088)/PGOOD (MAX5089)pulls low, and
`soft-start resets.
`
`Applications Information
`
`Setting the Switching Frequency
`The controller generates the switching frequency (fsw)
`through the internal oscillator or the signal at SYNC
`(fSYNC), when driven by an external oscillator. The
`switching frequency is equal to fsw or fsyNc.
`A resistor, ROSC, from OSC to SGNDsets the internal
`oscillator. The relationship between fsw and ROSCis:
`_ 125x108
`fsw
`
`Rosc
`
`At high input-to-output differential, and high switching
`frequency, the on-time drops to the order of 100ns.
`Even though the MAX5088/MAX5089 can control the
`on-time as low as 100ns,the internal current-limit circuit
`may not detect the overcurrent within this time. In that
`case,the output current during the fault may exceed the
`current limit specified in the Electrical Characteristics
`table. The MAX5088/MAX5089 maystill be protected
`against the output short-circuit fault through the
`overtemperature shutdown. However, the output cur-
`rent may be ashigh as 5.5A.If the minimum on-time for
`a given frequency and duty cycle is less than 200ns,
`choosethe inductor with a saturation current of greater
`than 5.5A.
`
`Power-on Reset (RESET)
`(MAX5088 Only)
`RESET is an active-low open-drain outputthat pulls low
`
`when VOUTfalls below 92.5% of its nominal set point.
`RESET goes high impedance when VouT rises above
`92.5% of its nominal set point, the soft-start period is
`complete, and the 200ms(typ) timeout period has
`elapsed. Connect a pullup resistor from RESET to a
`logic voltage or to VL. The internal open-drain MOSFET
`
`at RESET can sink 3mA while providing a TTL-compati-
`ble logic-low signal. Connect RESET to SGNDorleave
`unconnected whennot used.
`
`680SXVIN/880SXVIN
`
`where fsSw is in Hertz, and ROSC is in ohms. For exam-
`ple, a 1.25MHz switching frequency is set with Rosc =
`10kQ. Higher frequencies allow designs with lower
`inductor values and less output capacitance.
`Consequently, peak currents and I¢R losses are lower
`at higher switching frequencies, but core losses, gate-
`charge currents, and switching losses increase.
`Rising clock edges on SYNCareinterpreted as a syn-
`chronization input.If the SYNC signalis lost, the internal
`Power-Good (PGOOD)
`oscillator takes control of the switching rate, returning
`(MAX5089 Only)
`the switching frequency to that set by Rosc. This main-
`PGOODis an open-drain, active-high output that pulls
`tains output regulation even with intermittent SYNC sig-
`low when Vout is below 92.5% of its nominal set point
`nals. When using an external synchronization signal, set
`and goes high impedance when VOUT goes above
`Roscsothat (0.2 x fSYNC) < fsw < (1.2 x fSYNC).
`92.5% its nominal set point. Connect a pullup resistor
`from PGOODtoalogic voltage or to V_. PGOODcansink
`Buck Converter
`up to 3mA while still providing a TTL-compatible logic-low
`Use the internal n-channel power MOSFET asa high-
`output. Pulling EN low forces PGOOD low. Connect
`side switch to configure the MAX5088/MAX5089 as a
`PGOODto SGNDorleave unconnected when not used.
`buck converter. In this configuration, SOURCEis con-
`nected to the inductor, DRAIN is connected to the
`input, and BST/VDD connects to the cathode of the
`bootstrap diode and capacitor. Figures 5 and 6 show
`the typical application circuits for MAX5088/MAX5089,
`respectively, in a buck configuration.
`
`Thermal-Overload Protection
`During a continuous output short-circuit or overload
`condition, the power dissipation in the MAX5088/
`MAX5089 can exceedits limit. The MAX5088/MAX5089
`provide an internal thermal shutdownto turn off the
`device when the die temperature reaches +170°C. A
`thermal sensor monitors the die temperature and turns
`
`MAXIM
`
`
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`

`MAX5088/MAX5089
`
`2.2MHz, 2A Buck Converters with an
`Integrated High-Side Switch
`
`Effective Input Voltage Range
`The MAX5088/MAX5089 can operate with input sup-
`plies ranging from 4.5V to 5.5V or 5.5V to 23V. The
`input voltage range (V+) can be