119)
`United States Patent
`[1th=.33,980,992
`[45] Sept. 14, 1976
`Levy et al.
`
`[54] MULTI-MICROPROCESSING UNIT ON A
`SINGLE SEMICONDUCTOR CHIP
`
`Primary Examiner—Mark E. Nusbaum
`Attorney, Agent, or Firm—Mervyn L. Young
`
`[75]
`
`Inventors: Bernardo Navarre Levy, Ann
`Arbor, Mich.; David Chin-Chung
`Lee, San Diego, Calif.
`
`[73] Assignee:
`
`Burroughs Corporation, Detroit,
`Mich.
`
`[22]
`
`Filed:
`
`Nov. 26, 1974
`
`[21] Appl. No.: 527,358
`
`ABSTRACT
`[57]
`This disclosure relates to a multimicroprocessor unit
`which is adapted for implementation in a single MOS
`semiconductor chip, which unit includes a plurality of
`sets of registers where each set represents a different
`processing capability. The unit further includes com-
`mon elements which are shared by the different sets of
`registers in a time multiplex manner. The shared ele-
`ments include two scratch pad memories, an arithme-
`tic logic unit, and a control unit which incorporates a
`composite read only memory from which control sig-
`nals are fetched to initiate the respective data trans-
`fers and arithmetic operations. This control memory
`acts as a decoder for encoded microinstructions re-
`trieved from outside of the multi-processor unit.
`In
`this sense, the present invention employs both vertical
`and horizontal microprogramming as those terms are
`3,597,641 B/LOT TL—AYTOS cecccccccseeesecesteeaes 340/172.5
`
`.. 340/173 R
`3,641,511
`2/1972
` Cricchi et al. .
`conventionally defined. The different sets of dedicated
`
`we. 340/172.5
`3,757,306
`9/1973
` Boone..........
`registers are formed of 4-bit shift registers so as to per-
`
`
`we 340/172.5
`3,758,761
`9/1973
` Henrion.........
`mit a four-way time slicing among the processing
`3,786,436 1/1974=Zelinski et al... 340/172.5
`
`capabilities.
`
`[52] U.S. Ch cc cccecenssenecceneceee 340/172.5
`
`Int. Ch. GO6F 9/16; GO6F 9/18
`[St]
`Field of Search... 340/172.5; 445/1
`[58]
`
`[56]
`
`References Cited.
`UNITED STATES PATENTS
`
`10 Claims, 14 Drawing Figures
`
`12 BIT ROM
`ADDRESS
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`FROM ROM
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`16 BIT RAM
`ADDRESS
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`larien
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` LOGIC
`
`Google Exhibit 1026
`Google Exhibit 1026
`Google v. Valtrus
`Googlev. Valtrus
`
`

`

`U.S. Patent
`
`Sept. 14,1976
`
`Sheet 1of 10
`
`3,980,992
`
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`U.S. Patent
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`Sept. 14,1976
`
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`U.S. Patent
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`Sept. 14,1976
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`Sheet 3 of 10
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`U.S. Patent—sept. 14,1976 Sheet 4 of 10 3,980,992
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`U.S. Patent
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`Sept. 14,1976
`
`Sheet 5 of 10
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`3,980,992
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`U.S. Patent
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`Sept. 14, 1976
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`Sheet 6 of 10
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`3,980,992
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`U.S. Patent
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`Sept. 14, 1976
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`Sheet 8 of 10
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`U.S. Patent
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`Sept. 14,1976
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`USS.
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`Patent
`
`Sept. 14,1976
`
`Sheet 10 of 10
`
`3,980,992
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`1
`
`3,980,992
`
`MULTI-MICROPROCESSING UNIT ON A SINGLE
`SEMICONDUCTOR CHIP
`
`2
`macroinstruction operation code required two or more
`clock times, then the operation code could be incre-
`mented by a counter so as to access the sequence of
`such microinstructions.
`BACKGROUND OF THE INVENTION
`As the size of the microprogram processor became
`1. Field of the Invention
`more complex, the length of the microinstruction be-
`This invention relates to a microprogram multipro-
`came longer so as to accommodate the extra control
`cessing system andin particular to such a multiprocess-
`bits required. This, in turn, required that the microin-
`ing system which resides in a single semiconductor
`struction memory within the processor had to be larger
`chip.
`and, therefore, more expensive. In order to reduce the
`2. Description of the Prior Art
`size of the microinstruction memory in more complex
`Advancesin the field of integrated circuits have led
`processors, the microinstructions were encoded asdis-
`to an increase in the numberoftransistor gates which a
`tinct from being a series of unpacked or uncodedbits.
`circuit chip can accommodate from a very few up to
`This, in turn, required that a microinstruction decoder
`hundreds and even in excess of a thousand gates. Such
`be provided which was less complex than the macroin-
`advance have made it possible to begin considering
`struction decoder replaced by the microinstruction
`placing an entire small data processor onasingle inte-
`memory. Thus, there are really two types of microin-
`grated circuit chip. This,
`in turn, provides the eco-
`structions, one of which is an unpackedseries of bits
`nomic advantage of mass production in that, once the
`and one of which is a packed or encodedseries ofbits.
`circuit masks for fabrication of the chip have been
`The concept of microprogramming has allowed the
`designed, the entire processor can be automatically
`data processor to be programmed at a very basic level
`manufactured much more cheaply than when a number
`and thus provides moreflexibility for the implementa-
`of such chips are required to accommodate the proces-
`tion or interpretation of many higher level program
`sor, and certainly more cheaply than when a processor
`languages. However, the original concept of micropro-
`is formed of discrete components. A particular exam-
`gramming was devised in order to simplify the engi-
`ple of a small processor being placed onasingle inte-
`neering design and manufacture of data processors.
`grated circuit chip is illustrated in the Faber Patent
`The trend in design of data processors, particularly for
`Application No. 307,863, filed Nov. 20, 1972, now
`mini computers and micro processors, has been to
`U.S. Pat. No. 3,878,514, which application is assigned
`implement
`the processor in a few. or as indicated
`to the assignee of the present application.
`above, even one, MOSintegrated circuit chips which
`Smaller sized data processing system have many and
`processor employes microinstruction memories. How-
`are finding many more applications, not only as data
`ever, the size of the data processor in the range of the
`concentrators, process controllers, and the like, but
`mini computerfield is still limited by the number of
`also as small data processing systems for many business
`transistor gates that can be placed on the MOSinte-
`and technical applications.
`In many instances, data
`grated circuit chip. Thus, larger size computersstill
`processing requirements of a particular business will be
`must employ an extra number of integrated circuit
`a mix of accounting and billing tasks and also other
`chips with a consequential increase in manufacturing
`processes which require larger computational capabili-
`cost of the system since the plurality of different chips
`ties. To meet this situation, intelligent terminals are
`have to be designed and fabricated. In some systems,
`provided which not only allow for time sharing of a
`increased data through-put can be achieved where a
`larger computer but which are also capable of perform-
`plurality of small processors, each on an individual
`ing specific processing routines. Terminal processors
`semiconductor chip, are coupled together in a multi-
`can also perform various pre-processing tasks such as
`processing mode. However, even then, data transfer
`editing, formatting of data, etc.
`between the chips takes an extra numberofcycle times
`A particular architectural concept that has allowed
`and the resultant system is not as fast as if a larger
`for more flexibility in computer design andparticularly
`processor could be fabricated on a single chip.
`in regard to the design of mini computers and micro
`It is, then, an object of the present invention to pro-
`computers has been the concept of microprogramming
`vide an improved data processing system on a single
`or the employment of microinstructions to implement
`integrated circuit chip, which system has increased
`or
`interpret macroinstructions and instructions of
`operating capabilities with a minimized manufacturing
`cost;
`higher level programming languages. Originally, micro-
`instructions were considered to be just those sets of
`it is still another object of the present invention to
`control bits required to activate various gates in a pro-
`provide a multiprocessing microprogrammed system
`cessor as might be required to carry out data transfer
`on a single integrated circuit chip; and
`from one register to another and through the arithmetic
`it is a further object of the present invention to pro-
`and logic unit of the processor. These bits were stored
`vide a multiprocessing microprogrammed system with
`in a small memory within the processor at locations
`a plurality of processing capabilities sharing common
`which were addressed by the operation code of a mac-
`elements of the system.
`roinstruction. In this sense, the concept of micropro-
`gramming was that of replacing the macroinstruction
`decoder by a table look-up memory.
`Asinitially defined, the microinstruction was a set of
`unpacked bits, each of which represented a control
`signal required to activate a gate, the set of control
`signals representing all gates required for activation to
`perform the function during one clock time as required
`by the macroinstruction operation code which was
`used to address the microinstruction memory. If the
`
`In order to accommodate more than one processing
`capability on a single MOSintegrated circuit chip hav-
`ing a limited number of transistor gates, the present
`invention is directed toward plural sets of registers,
`eachset representing a different processing capability,
`which registers share a commonlogic unit, control unit,
`and buses. The control unit includes a microprogram
`memory which is shared by the respective sets of pro-
`
`5
`
`20
`
`30
`
`35
`
`40
`
`45
`
`35
`
`60
`
`65
`
`SUMMARYOF THE INVENTION
`
`

`

`3,980,992
`
`cessor registers and controls data transfer between
`individual ones of the registers in each particular set
`and with the logic unit. Such data transfers are under
`control of a clock with the respective sets of processor
`registers being accessed in a sequential time slice or
`multiplexing type mode with the respective sets of reg-
`isters being activated by the clock in a successive man-
`ner.
`A particular advantage of the present invention hav-
`ing a plurality of concurrent microprocessing capabili-
`ties is that processing capabilities have free communi-
`cation with each other at different levels. One level of
`communication is through the interconnections pro-
`vided between the processing capabilities the inte-
`grated circuit chip. Communication may also be ob-
`tained through the local scratch pad memory whichis
`shared by the respective processing capabilities, and
`the respective processors can also communicate
`through main memory. Furthermore, an additional
`advantageis provided by the sharing of the same micro-
`program memorywith all processing capabilities.
`A feature, then, of the present invention resides in a
`multi-microprocessing system having a plurality of sets
`of registers, each set representing an individual pro-
`cessing capability, and a common logic unit, micro
`program control memory, buses, and scratch pad mem-
`ory shared by the respective processor registers.
`DESCRIPTION OF THE DRAWINGS
`
`The above objects, advantages, and features of the
`present invention will become more readily apparent
`from the following specification when taken in con-
`junction with the drawings wherein:
`FIG. 1 is a representation of a system employing four
`multiprocessing units of the present invention;
`FIG. 2 is a functional representation of the units of
`the multiprocessing unit of the present invention;
`FIG. 3 is a schematic diagram ofthe interfaces which
`connect to the multiprocessing unit of the present in-
`vention;
`FIG. 4 illustrates the relation of FIGS. 4A and 4B;
`FIGS. 4A and 4B are detailed schematic diagrams of
`the circuitry of the present invention;
`illustrate the
`FIGS. 5A, 5B, and 5C, respectively,
`organization of the A and B scratch pad memories;
`FIG. 6 is a schematic diagram of the arithmetic logic
`unit of the present invention;
`FIG. 7 is a schematic diagram of a set of shift regis-
`ters as employed with the present invention;
`FIG. 8 represents tables illustrating the function per-
`formed by the various microinstructions employed by
`the present invention,
`FIG. 9 is a schematic diagram of the control unit of
`the present invention; and
`FIG. 10 is a set of wave formsillustrating the time
`multiplexing of common elements among the various
`processing capabilities of the present invention.
`GENERAL DESCRIPTION OF THE [INVENTION
`The organization of the system employed in the pre-
`sent inventionis illustrated in FIG. 1 wherein a plurality
`of MOSintegrated circuit chips are coupled in a config-
`uration to form a flexible multiprocessing system. The
`system of FIG. 1 includes a plurality of multiprocessing
`units (MPU) 11, which are coupled to random access
`memory (RAM) 13 whichis provided for the storage of
`data and other information. Each MPU 11 is micropro-
`grammedand to this end is coupled to a respective read
`
`5
`
`30
`
`35
`
`40
`
`45
`
`30
`
`60
`
`65
`
`4
`only memory (ROM) 12. As indicated in FIG. lla
`variety of peripheral devices may be employed by the
`system under control of the various MPU’s which de-
`vices include disk memory 15, printer 16, cathode ray
`tube display 17, cassette drive 18, and data communi-
`cation unit 19.
`Before the detail circuitry of the MPUis described, a
`description will first be given of the functional units
`employed by each processing capability in the multi-
`processing system during that time slice when the indi-
`vidual processing capability has access to the shared
`resources in the system. A functional diagram of the
`processor with its unique and shared resourcesis illus-
`trated in FIG. 2. The shared resources include the B
`scratch pad memory 31 and A scratch pad memory 32,
`the arithmetic logic unit (ALU) 33, control logic 40,
`and F register 41, The resources with which each pro-
`cessor is separately provided include X register 35,
`microprogram counter (PC) register 36, page (PR)
`register 37, and prepage (PPR) register 38, I register
`43, N register 44, K register 34, and Y register 42.
`The unique registers of the processor will now be
`described in relation to FIG. 2. In order for these spe-
`cial purpose registers to be dedicated to specific pro-
`cessing capabilities, they are formed out of 4-bit shift
`registers so as to permit four-way time slicing among
`the processing capabilities.
`X register 35 is an 8-bit instruction register used to
`hold microinstructions during instruction decode and
`execution time. PC register 36 is an 8-bit micropro-
`gram counter register. This register holds the byte-
`within-page address of the next microinstruction to be
`executed. PR register 37 is a 4-bit microprogram
`counter page register. This register holds the page ad-
`dress of the next microinstruction to be executed.
`PPR register 38 is a 4-bit prepage register. A jump
`out-of-page operation requires two instructions: a load
`page register instruction and a jumpinstruction. PPR
`register 38 is used to hold the new page number while
`the jump instruction is being fetched. The contents of
`the PPR register are loaded into the PR register only if
`the next instruction results in a jump. In all other cases,
`the load page register instruction behaves as a no oper-
`ation. Thus, a conditional jump out-of-page operation
`remains in the same page if the condition is not satis-
`fied.
`I register 43 is a 4-bit register used to address the A
`scratch pad memory.N register 44 is a 2-bit register to
`address one of four pagesin the B scratch pad memory.
`It is used in conjunction with part of the instruction to
`address a register in the B scratch pad memory. This
`register is also used to load | register 43.
`K register 34 is a 1-bit register which is set or cleared
`only during add instructions. It may be used as an input
`to the ALU and canbetested by jump-on-carry instruc-
`tion. Y register 42 is a 4-bit state machineregister. This
`register is used to store the state of each processing
`capability during the time the other processing capabil-
`ities are executing. This is necessary since several in-
`structions require more than one clock for execution.
`The shared elements will now be described. ALU 33
`is a 4-bit arithmetic and logic unit capable of perform-
`ing binary addition, and bit-by-bit logical AND, OR,
`and EXCLUSIVE OR operations. Each operation is
`performed during a one clock time slice where byte
`Operations require two passes through the ALU. A
`scratch pad memory 32 contains 16 registers, each
`register being 8-bits in width, which registers can be
`
`

`

`3,980,992
`
`20
`
`25
`
`30
`
`35
`
`5
`processing capabilities two and three. It is this sharing
`used as general purpose registers or for special pur-
`that allows data to be passed between processing capa-
`poses. The sixteen registets are divided into four pages
`bilities without requiring a changein the value of N. It
`of four registers each. When used for special purposes,
`should be noted that since each processor can change
`the A registers are used in conjunction with B registers.
`the value ofits N register, it can communicate to other
`The special purposes for which the registers can be
`used are discussed below.
`processors through any of the A orBregisters. By using
`the shared registers (byte zero, two, and 14), communi-
`B scratch pad memory 31 contains 24 registers of 8
`cation is accomplished without need to temporarily
`bits each or it may be considered as 48 registers of 4
`changethesetting of N. In partitioning the B scratch
`bits each, which registers may be used as general pur-
`pad memory between processors, a shared register can
`pose storage registers, or in conjunction with A regis-
`be assigned only to one processor unless it is used for
`ters 32 as special purpose registers. The special pur-
`communication.
`poses for which these registers may be used are de-
`scribed below,
`As indicated above, one of the advantages of the
`present invention is that the four processors can share
`single copies of microprograms, either subroutines or
`full programs, and can be run concurrently. This is
`accomplished by first setting different values in the N
`registers for each of the processors and then having
`each processor jump to the same location in the read
`only memory. Programs written this way, however,
`cannot use any shared B register.
`The special purposes for which the elements of A and
`B scratch pad memories are used to store 16-bit ran-
`dom access memory addresses, microprogram subrou-
`tine addresses, and microprogram memory read ad-
`dresses. The elements of both scratch pad memories
`are concatenatedfor these purposes. For example, four
`pages of the A scratch pad memory and four pages of
`the B scratch pad memory can be grouped together,
`page zero of A with page zero of B, page one of A with
`page one of B, and so forth. Groups of pages for only
`one such group are shown in FIG. SC since all the
`groups of pages function in an identical manner.
`Asillustrated in FIG. 5C, each group of pages has
`four random access memory read/write address regis-
`ters. The first three of these, as indicated by R/WO,
`R/W1, R/W2, concatenate the following registers: B8
`and AO, B10 and Al, and B12 and A2, so as to form
`three 16-bit random access memoryregisters for read-
`ing and writing data into the random access memory. In
`each case, the B byte is the mostsignificant part of the
`address. The fourth address register,
`indicated by
`R/W3, concatenates A3 with all ones to form a ‘“‘di-
`rect” addressing page in the random access memory,
`the upper most page.
`Microprogram memory (ROM) addresses are all 12
`bits long and are formed by concatenation of an 8-bit A
`register and the lower four bits (an even numbered
`digit address) of a B register. Three such ROM address
`registers are included in each pair of A and B pages.
`One of these concatenates digit B2 with A1 to form the
`ROM address register. This combination is used to
`translate data. A table of codes is stored in the ROM
`and translation is performed simply by placing the
`input code in B2 and Al and reading the ROM.
`The other two 12-bit ROM address registers are used
`to store return addresses after a microprogram subrou-
`tine jump instruction is executed. The return page
`numberis stored in the B digit registers and the address
`within a page is stored in the A registers in the combi-
`nation A2 along with B4 and A3 along with B6.It is
`obvious that two levels of subroutines can be handled
`very satisfactorily.
`A description of the interfaces between the multipro-
`cessing unit of the present invention and the periphery
`of the system in which it resides will now be described
`with reference to FIG. 3. As showntherein, the various
`interfaces include data bus 20 which is 8-bits wide,
`
`logic 40 includes a composite read only
`Control
`memory and control logic which sequences operations
`of the system at the control signal level. F register 41 is
`a single flip-flop which is intended as a flag. It can be
`used by one processing capability or to communicate
`between processing capabilities.
`FIG. SA illustrates the organization of A registers 32
`and FIG. 5B illustrates the organization of B registers
`31. Each processing capability is capable of accessing
`each of the 16 A registers or 24 B registers. However,
`to prevent one processing capability from destroying
`data of another processing capability, it is necessary to
`partition the A and B registers so that each processing
`capability has its own unique set. This partitioning
`should be done before any of the processing capabili-
`ties are microprogrammed.
`Exactly how the partitioning should be done, of
`course, depends upon the tasks each processing capa-
`bility is to perform. In general, the partition of allocat-
`ing one page per processing capability reduces coding
`when the four processing capabilities are to execute
`similar tasks. In cases where one or two of the process-
`ing capabilities are to execute more complicated tasks
`than the others, it may be desirable to unevenly parti-
`tion the registers to the complex tasks. This is espe-
`cially true if by allocating more scratch pad locations to
`the tasks, fewer accesses to the random access memory
`are necessary.
`The B scratch pad memory, like the A scratch pad
`memory, consists of four pages. Generally, each pro-
`cessor is allocated one page of B registers. The page
`number which is to be used by a processoris stored in
`its 2-bit N register. Addressing within a page is done in
`two ways: by byte and by digit. Byte addresses are the
`even numbers zero through 14. Digit addresses are the
`numbers zero through 15. These addresses access the
`same data: byte zero is the same register as digits zero
`and one; byte two is the same as digits two and three;
`and so forth.
`As can be seen from FIG. 5B, the addressing space of
`the B scratch pad memory consists of 32 bytes or 64
`digits. For two reasons, however, this done not match
`the physical size of the B scratch pad memory. Thereis
`not enough space on the integrated circuit chip for 32
`bytes and inter-processing capability communications
`is enhanced bysharing physical registers. FIG. 5B illus-
`trates how the registers are shared. As shown therein,
`each rectangle, regardless of size, represents one physi-
`cal 8-bit register.
`If it is assumed that each of the four processing capa-
`bilities uses a different value for N (B scratch pad page)
`thenit is apparent that byte zero and 14 are shared by
`all processing capabilities and that one copy of byte
`two register is shared between processing capability
`zero and one and the other copy is shared between
`
`40
`
`45
`
`50
`
`35
`
`60
`
`65
`
`

`

`3,980,992
`
`7
`It will be
`lines.
`address bus 21 and various control
`remembered from the description of the system in FIG.
`2 that a 16-bit address is required to address random
`access memory 13 while a 12-bit address is required to
`address read only memory 12. A 4-bit address is re-
`quired for the input/output decoder I4A which in turn
`selects a peripheral device either by way of output logic
`14B or input logic 14C, depending upon whether the
`data transmission to the peripheryis called for to be an
`output transmission or an input transmission, respec-
`tively. Input transmission to data bus 20 is by way of
`transmission gates 28 when an input/output signal
`is
`transmitted from the multiprocessing unit and there is
`not a write signal present at the same time.
`System instruction and data transfer from random
`access memory 13 occurs by way of data bus 20 when
`there is no write signal but there is a memorysignal and
`a 16-bit address is presented to the random access
`memory 13. Microinstruction transfer from read only
`memory 12 occurs when there is no memory signal
`present, no input/output signal present and the 12-bit
`address is transmitted to the read only memory 12.
`DETAILED DESCRIPTION OF THE INVENTION
`
`A detailed description of the present invention will
`now be provided with reference to FIGS. 4A and 4B,
`whichare to be viewed together according to the rela-
`tion illustrated in FIG. 4. The functional units in FIGS.
`4A and 4B were generally described in relation to FIG.
`2. It will be remembered from discussion of FIG. 2 that
`the present invention comprisespluralsets of registers,
`each set of which is unique and representative of an
`individual processing capability and also shared ele-
`ments which are commonlyavailable to the unique sets
`of registers in a time multiplex manner so that in any
`given clock time, one of the processors thus formed is
`capable of functioning.
`In FIG. 4A, B scratch pad memory 31 comprises 24
`registers each of which are 8-bits wide, while A scratch
`pad memory 32 includes 16 registers each of which is
`8-bits wide. ALU 33 is a 4-bit arithmetic logic unit
`while K register 34 is a 4-bit register which is accessed
`a bit at a time. It will be remembered that the K register
`is one of the registers that is unique to each processing
`capability. Thus, there can be up to four carry bits in
`the K registers, one such bit for each processing capa-
`bility. PR register 37 includes four registers of 4-bits
`each. Again,
`it will be remembered that there is a
`unique PR register for each processing capability.
`Address register 50 includes eight registers of 4-bits
`each which registers are used to transmit the upper
`8-bit addresses to the random access memory. The
`reason for this organization of the address register 50 is
`that the data paths to and from address register 50
`comprise two buses each of which is 4-bits wide.
`Register 54 is an 8-bit register to supply data to A
`scratch pad memory 32. N register 44 includes four
`registers of 2-bits each. It will be remembered that the
`unique 2-bit N register is provided for each processing
`capability in the system.
`In FIG. 4B, X register 35 and PC register 36 both
`include four registers of 8-bits each, each particular
`register being assigned to a particular processing capa-
`bility. Similarly, | register 43 and Y register 42 contain
`four registers of 4-bits each with each register being
`assigned a particular processor.
`The heart of the control logic 40 is a composite read
`only memory which may be a 51 by 29 MOSdevice
`
`55
`
`60
`
`65
`
`matrix that can be reprogrammedto change the control
`signal sets which, in turn, are employed to decode mi-
`croinstructions received in a particular processing ca-
`pability’s X register 35 from external read only memory
`12 (see FIG. 3). F register 41 is a 1-bit flip-flop register
`that was described in relation to FIG. 2.
`Asillustrated in FIG. 4B, the signals required for
`memory access and input/output operations are gener-
`ated directly by the composite read only memory and
`by the status of the respective Y registers 42 which
`store the state of each processing capability during the
`time that the other processing capabilities are execut-
`ing. The signals which initiate a function of the arith-
`metic logic unit and data transfers between registers
`are also generated directly by the composite read only
`memory.
`FIG. 6 is a schematic diagram of the arithmetic logic
`unit (ALU) 33 of FIGS. 2 and 4A. The ALUis a four-
`bit adder that performs the functions AND, EXCLU-
`SIVE OR, and ADD.Asillustrated in FIG. 6, the ALU
`is formed of 4 stages to provide the ALU outputsignals
`SO, $1, $2, and S3 plus a carry signal KI. Each of the
`stages is powered bya set of voltage sources VDD. The
`inputsignals to the ALUare the data sets a0, al, a2, a3,
`and b0, b1, b2, b3 plus an initial carry signal KO. The
`control signals ALU1, ALU2, and ALU3 are received
`from control logic 40 of FIGS. 2 and 4B. Controlsignal
`ALU3 causes the ALU to perform the AND function.
`Control signal ALU2 causes the ALU to perform the
`EXCLUSIVE OR function. Control
`signal ALU3
`causes the ALU to perform the EXCLUSIVE ORfunc-
`tion with the carry signal KO and the EXCLUSIVE OR
`productof the a and b input signals. Thus, the combina-
`tion of control signals ALU2 and ALU3 causes the
`ALU to perform the ADD function on the respective
`input signals.
`,
`As has been indicated above, the respective unique
`registers of FIGS. 2, 4A, and 4Bare four-bit shift regis-
`ters so as to accommodate four-way timeslicing or time
`sharing of the common elements of the system,
`i.e.,
`ALU 33,control logic 40 and so forth as was discussed
`in relation to FIG. 2. An example of such shift registers
`is provided by FIG. 7 which is a schematic diagram of
`Y registers 42 and also K registers 34 of FIGS. 2, 4A,
`and 4B. These registers may be considered as four
`four-bit shift registers YO, Y1, Y2, and Y3 (plus the K
`shift register) or they may be considered as four paral-
`lel registers YTO, YT1, YT3, and YT4 through which
`data is sequenced in synchronization with the time
`slicing or sharing of the common elements ofthe sys-
`tem by the four (albeit virtual) processing capabilities
`formed by the system.
`Eachbit position of the respective registers is formed
`of two cells which are sequentially driven by phase
`clock signals Q1 and Q2, respectively. As illustrated in
`FIG. 7, a typical cell is formed of FET (field effect
`transistor) gates 42a and 42b and inverter amplifiers
`42and 42d which are just individual transistors in the
`integrated circuit chip. During clock phase Q1, gate
`42a of register YTO (and also registers YT1, YT2, and
`YT3) is activated to receive an input signal YTO. Dur-
`ing clock phase Q2, gate 42bis activated to receive that
`signal from gate 42a whichis then free to receive a new
`input signal during the next clock phase Q1.
`FIG. 9 is a schematic diagram of the control matrix of
`control logic 40 of FIGS. 2 and 4B. This matrix is em-
`ployed to decode the respective microinstructions
`when they reside in X register 35 of FIGS. 2 and 4B.
`
`

`

`3,980,992
`
`9
`This matrix may be reprogrammed by connecting and
`disconnecting the various ‘nodes of the matrix so that it
`is equivalent to a control memory and maybe replaced
`by such.
`The relation between these respective controlsignals
`to be generated and the respective microinstructions
`residing in the X register during execution is illustrated
`in detail in FIG. 8. The table in FIG. 8 will not be dis-
`cussed in detail; however, the functions as indicated
`therein will now be discussed for each microinstruction
`in the instruction set. In the following discussion, alpha-
`betic letters in the microins