a2) United States Patent
`US 7,085,705 B2
`(0) Patent No.:
`Aug. 1, 2006
`(45) Date of Patent:
`Traut
`
`US007085705B2
`
`(54) SYSTEM AND METHOD FOR THE LOGICAL
`SUBSTITUTION OF PROCESSOR CONTROL
`IN AN EMULATED COMPUTING
`ENVIRONMENT
`Inventor: Eric P. Traut, San Carlos, CA (US)
`Assi
`: Mi
`ft C
`tion,
`Redmond, WA
`Assignee
`(US)OS
`OEPOEAOD SERMON
`
`(75)
`73)
`(73)
`
`5,757,386 A
`5/1998 Celi, Jr et al. oc. 345/507
`5,790,825 A
`8/1998
`
`5,815,686 A
`9/1998 Earl et al. we 395/500
`5,831,607 A
`11/1998 Brooks oo... eee 345/333
`5,860,147 A
`1/1999 Gochman etal. ........... 711/207
`5,940,872 A
`8/1999 Hammondet al.
`......... 711/207
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`12/1992
`42 17 444 Al
`DE
`7/1992
`0524773 Al
`EP
`Subject to any disclaimer, the term ofthis
`(*) Notice:
`
`
`patent is extended or adjusted under 35 0 645 701 A2=9/1994EP
`US.C. 154(b) by 1408 days.
`FR
`2 587 519
`3/1987
`WO
`WO 98/57262
`12/1998
`
`(21) Appl. No.: 09/747,492
`
`OTHER PUBLICATIONS
`
`Filed:
`
`“Processor Instruction Sets,” The PC Guide, version date
`Dec. 18, 2000, http://www.pcguide.com/ref/cpu/arch/int/in-
`st_chtml.
`
`Dec. 21, 2000
`.
`ss
`Prior Publication Data
`US 2002/0099532 Al Jul. 25, 2002
`Int. Cl.
`GO6F 9/455
`
`(2006.01)
`
`(22)
`
`(65)
`
`(51)
`
`(56)
`
`
`
`(Continued)
`Primary Examiner—Albert W.Paladini
`(74) Attorney, Agent, or Firm—Woodcock Washburn LLP
`(57)
`ABSTRACT
`.
`.
`.
`(52) U.S. Ch. eects 703/23; 703/26; 710/104
`(58) Field of Classification Search 0.0... 703/23,|11 an emulated computing environment, a method is pro-
`703/26. 27: 718/1. 102: 710/104. 22: 711 N73
`vided for logically decoupling the host operating system
`See application file for complete search history.
`from the processor of the computer system with respect to
`certain processor settings of the processor. A hypervisor of
`References Cited
`the emulation program replaces some of the processor
`settings of the processor with processor settings associated
`with software routines or data structures provided by the
`U.S. PATENT DOCUMENTS
`4,779,188 A
`10/1988 Gumett al. weceeceeen 364/200
`guest operating system. The replaced processorsettings are
`10/1989 Blume, Jr. nec 364/900
`4,875,186 A
`written to memory. During this period, when the processor
`
`1/1994 O’Brien et al. .......... 395/500
`5,278,973 A
`calls a software routine or accesses a data structure associ-
`
`4/1994 Kanal oes 709/301
`5,301,277 A
`ated with the replaced processorsetting, the processor will
`11/1994 Otte et al. seers 345/501
`5,367,628 A
`call or access a software routine or access a data structure
`
`4too: Ned “at rertrrtrrrseees aay700
`oegee ‘
`associated with the guest operating system, bypassing the
`
`seresseeerees
`wes
`OUTOY SF
`Ae
`host
`ti
`r
`d
`communicating
`directly
`with th
`10/1995 Thomassen ....ss.ssssee0 395/500
`5,460,644 A
`ost operalne system “Whe
`hehee ing cirechly Wai
`Me
`
`3/1996 Takano wieseessesesssssseeees 345/509
`5,502,809 A
`—-«-Suest Operating system.
`When the
`host operating system 1s
`7/1996 Bright et al. vu... 702/122
`5,541,862 A *
`to be recoupled to the processor, the processorsettings that
`5,640,562 A
`6/1997 Wold et al. cece 395/652
`_~‘have been saved to memory are rewritten to the appropriate
`5,666,521 A
`9/1997 Marisetty .....cccceees 345/525
`registers of the processor.
`5,742,797 A
`4/1998 Celi, Jr ct al. we. 345/507
`5,752,275 A
`5/1998 Hammond.
`..........0000 711/207
`
`(GuaatApplication Program
`
`
`‘Guest Ogerating System [ei
`
`Guest Computer System
`
`22 Claims, 3 Drawing Sheets
`
`
`
`
`
`
`
`Emulation Program
`
`
`“6
`
`oo
`
`
`Host Operating System
`
`a2
`a
`
`[a
`Host Hardware
`to
`
`7
`
` Google Exhibit 1017
`
`Google Exhibit 1017
`Google v. Valtrus
`Google v. Valtrus
`
`

`

`US 7,085,705 B2
`
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`USS. Appl. No. 09/617,624, “System and Method for Emu-
`lating the Operation of a Video Graphics Adapter’, Carroll,
`6,014,170 A
`1/2000 Pont et al. oo... 348/232
`et al., filed Jul. 17, 2000.
`
`
`6,026,476 A 2/2000ROSENwe.eee 711/206
`
`5/2000 Weber ........cccceeseceeeees 713/1
`6,067,618 A
`PCT International Search Report in International Applica-
`6,298,370 Bl * 10/2001 Tang etal.... 718/102
`tion No. PCT/US 01/22276, Internationalfiling date Jul. 16,
`6,668,287 Bl * 12/2003 Boyle et al... 710/22
`2001, mail date Jul. 3, 2002.
`OTHER PUBLICATIONS
`Traut B, “Building the Virtual PC,” Byte, McGraw-Hill Inc.,
`vol. 22, No. 11, pp. 51-52, Nov. 1, 1997.
`“Intel386 DX Microprocessor,” Intel, pp. 32-58, Dec. 31,
`1995.
`
`i-xvill;
`“M68060 User’s Manual,” Motorola, 1994, pp.
`Section 4, Memory Management Unit, pp. 4-1 to 4-30,
`http://e-www.motorola.com/brdata/PDFDB/MICROPRO-
`CESSORS/32_BIT/68K-COLDFIRE/M680X0/
`MC68060UM.pdf.
`“MPC750, RISC Microprocessor User’s Manual,”
`Motorola, Aug. 97, Contents, pp.
`iii-xvi; Chapter 5,
`Memory Management, pp. 5—1 to 5-34; Glossary, pp. Glos-
`sary—1 to Glossary—13, http://e-www.motorola.com/brdata/
`PDFDB/MICROPROCESSORS/32_BIT/POWERPC/
`MPC7XX/MPC750UM. pdf.
`PCT International Search Report in International Applica-
`tion No. PCt?US 01/22277, Internationalfiling date Jul. 16,
`2001, mail date Feb. 7, 2002.
`USS. Appl. No. 09/617,669, “System and Method for Dis-
`playing Current Images of Virtual Machine Environments”,
`Traut, et al., filed Jul. 17, 2000.
`
`“MacIntosh and Technology: Changing Chips in the Middle
`of the Stream, or Apple Takes a Risc,” URL:www.btech.co/
`changingchips.html, paragraphs ’00061-’00071, retrieved
`Dec. 10, 2001.
`“M68040 User’s Manual,” Motorola, Inc., Chapter 3, copy-
`right 1990, revised 1992, 1993.
`Osisek DLet al., “ESA/390 Interpretive-Execution Archi-
`tecture, Foundation for VM/ESA,” IMB Systems Journal,
`vol. 30, No. 1, pp. 34-51, 1991.
`Shang Rong Tsai et al., On the Architectural Support for
`Logical Machine Systems, Microprocessing and Micropro-
`gramming, vol. 22, No. 2, pp. 81-96, Feb. 1988.
`
`* cited by examiner
`
`

`

`U.S. Patent
`
`Aug. 1, 2006
`
`Sheet 1 of 3
`
`US 7,085,705 B2
`
`
`
`
`
`Guest Apptication Program
`
`Guest Operating System
`
`Guest Computer System
`
`Emulation Program
`
`44
`
`Host Operating System
`
`Host Hardware
`
`10
`
`Figure 1
`
`

`

`U.S. Patent
`
`Aug. 1, 2006
`
`Sheet 2 of 3
`
`US 7,085,705 B2
`
`Hypervisor Reads In Processor Settings from Processor
`
`
`
`Hypervisor Saves Processor Settings to Memory
`
`
`
`Hypervisor Loads Into Processor Registers
`the Processor Settings of the Guest Operating System
`
`
`
`Hypervisor Loads Into Processor Registers the Processor
`Settings of the Host Operating System from Memory
`
`28
`
`30
`
`Figure 2
`
`

`

`U.S. Patent
`
`Aug. 1, 2006
`
`Sheet 3 of 3
`
`US 7,085,705 B2
`
` —
`
`
`
`Guest Application Program
`
`Guest Operating System
`
`
`
`
`Guest Computer System
`
`
`
`
`
`Emulation Program
`
`Hypervisor
`22
`
`—
`
`Host Operating System
`
`—
`
`Host Hardware
`
`Figure 3
`
`

`

`US 7,085,705 B2
`
`1
`SYSTEM AND METHOD FOR THE LOGICAL
`SUBSTITUTION OF PROCESSOR CONTROL
`IN AN EMULATED COMPUTING
`ENVIRONMENT
`
`TECHNICAL FIELD OF THE INVENTION
`
`The present invention relates in general to the field of
`computer system emulation and, more particularly,
`to a
`method for transparently decoupling the host operating
`system from the processor of the computer system in favor
`of control by the processor by the guest operating system.
`BACKGROUND OF THE INVENTION
`
`Computers include general purpose central processing
`units (CPUs) that are designed to execute a specific set of
`system instructions. A group of processors that have similar
`architecture or design specifications may be considered to be
`members of the same processor family. Examples of current
`processor families include the Motorola 680x0 processor
`family, manufactured by Motorola, Inc. of Phoenix, Ariz.;
`the Intel 80x86 processor family, manufactured by Intel
`Corporation of Sunnyvale, Calif.; and the PowerPC proces-
`sor family, which is manufactured by Motorola, Inc. and
`used in computers manufactured by Apple Computer,Inc. of
`Cupertino, Calif. Although a group of processors may be in
`the same family because of their similar architecture and
`design considerations, processors may vary widely within a
`family according to their clock speed and other performance
`parameters.
`Each family of microprocessors executes instructions that
`are unique to the processor family. The collective set of
`instructions that a processor or family of processors can
`execute is knownas the processor’s instruction set. As an
`example, the instruction set used by the Intel 80x86 proces-
`sor family is incompatible with the instruction set used by
`the PowerPC processor family. The Intel 80x86 instruction
`set
`is based on the Complex Instruction Set Computer
`(CISC) format. The Motorola PowerPC instruction set is
`based on the Reduced Instruction Set Computer (RISC)
`format. CISC processors use a large numberofinstructions,
`some of which can perform rather complicated functions,
`but which require generally many clock cycles to execute.
`RISC processors use a smaller numberof available instruc-
`tions to perform a simpler set of functions that are executed
`at a much higherrate.
`The uniqueness of the processor family among computer
`systems also typically results in incompatibility among the
`other elements of hardware architecture of the computer
`systems. A computer system manufactured with a processor
`from the Intel 80x86 processor family will have a hardware
`architecture that is different from the hardware architecture
`of a computer system manufactured with a processor from
`the PowerPCprocessor family. Because of the uniqueness of
`the processor instruction set and a computer system’s hard-
`ware architecture, application software programsare typi-
`cally written to run on a particular computer system running
`a particular operating system.
`to maximize its
`A computer manufacturer will want
`market share by having more rather than fewer applications
`run on the microprocessor family associated with the com-
`puter manufacturer’s product line. To expand the number of
`operating systems and application programs that can run on
`a computer system, a field of technology has developed in
`which a given computer having one type of CPU,called a
`host, will include an emulator program that allows the host
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`computer to emulate the instructions of an unrelated type of
`CPU,called a guest. Thus, the host computer will execute an
`application that will cause one or more host instructions to
`be called in response to a given guest instruction. Thus, the
`host computer can both run software designed for its own
`hardware architecture and software written for computers
`having an unrelated hardware architecture. As a more spe-
`cific example, a computer system manufactured by Apple
`Computer, for example, may run operating systems and
`program written for PC-based computer systems. It may also
`be possible to use an emulator program to operate concur-
`rently on a single CPU multiple incompatible operating
`systems. In this arrangement, although each operating sys-
`tem is incompatible with the other, an emulator program can
`host one of the two operating systems, allowing the other-
`wise incompatible operating systems to run concurrently on
`the same computer system.
`When a guest computer system is emulated on a host
`computer system, the guest computer system is said to be a
`virtual machine, as the host computer system exists only as
`a software representation of the operation of the hardware
`architecture of the guest computer system. The terms emu-
`lator and virtual machine are sometimes used interchange-
`ably to denote the ability to mimic or emulate the hardware
`architecture of an entire computer system. As an example,
`the Virtual PC software created by Connectix Corporation of
`San Mateo, Calif. emulates an entire computer that includes
`an Intel 80x86 Pentium processor and various motherboard
`components and cards. The operation of these componentsis
`emulated in the virtual machine that is being run on the host
`machine. An emulator program executing on the operating
`system software and hardware architecture of the host
`computer, such as a computer system having a PowerPC
`processor, mimics the operation ofthe entire guest computer
`system. The emulator program acts as the interchange
`between the hardware architecture of the host machine and
`the instructions transmitted by the software running within
`the emulated environment.
`
`A hypervisor is a control program that exists near the
`kernel level of a host operating system and operates to allow
`one or more secondary operating systems, other than the
`host operating system, to use the hardware of the computer
`system, including the processor of the computer system. A
`hypervisor of an operating system emulates the operating
`environment of the secondary operating system so that the
`secondary operating system believesthat it is operating in its
`customary hardware and/or operating system environment
`and that it is in logical control of the computer system, when
`it may in fact be operating in another hardware and/or
`operating system environmentandthe host operating system
`may be in logical control of the computer system. Many
`operating systems function such that the operating system
`must operate as though it is in exclusive logical control of
`the hardware of the computer system. For multiple operating
`system to function simultaneously on a single computer
`system, the hypervisor of each operating system must func-
`tion to mask the presence of the other operating systems
`such that each operating system functions as though it has
`exclusive control over the entire computer system.
`If it is desired to emulate the entire hardware architecture
`of the guest system,it is often useful or desirable to make
`maximum use of the hardware in the host computer system,
`including, for example, the memory management unit, the
`context switching hardware, the exception handling vectors,
`the interrupt routine pointers, and the floating point units of
`the host processor, and the memory of the host computer
`system. This hardware, however,
`is normally under the
`
`

`

`US 7,085,705 B2
`
`3
`control of the host operating system and is shielded from
`access by user-level or application software. An exceptionis
`an event occurring in the computer system that cannot be
`resolved by the processor. An interrupt is a request sent to
`the processor to temporarily interrupt the current instruction
`stream to perform some other operation
`One option to avoid this difficulty is to employ an
`emulation program that does not attempt to use the lower
`level hardware of the host computer system. This sort of
`approach is often in the case of emulation program that
`resides as an application program and runs on the host
`operating system. These application emulation programs, of
`course, are subject to the performance penalties of being an
`application program that runs on the host operating system
`of a host computer system. Further, these application emu-
`lation programs only gain access to the hardware features
`that are exposedto the application emulation program by the
`host operating system. As an example, an emulation pro-
`gram that runsas an application on the host operating system
`can include an exception handler. The difficulty is that the
`exception handler of the emulation program is separated
`from the processor of the host computer system by several
`software layers, creating a latency between the timethat the
`host processor issues and exception and the time that the
`exception is identified to the exception handler of the
`emulation program. Another option is for the emulation
`program to share the hardware with the host operating
`system, assuming that support for the sharing of computer
`system by an emulation program can be written into the
`hypervisor of the host operating system.
`
`SUMMARY OF THE INVENTION
`
`The present invention concerns a technique for logically
`decoupling a host operating system from a processor of the
`computer system. According to the method of the present
`invention, a hypervisor of an emulation program reads in a
`set of the processor settings of the processor. These proces-
`sor settings are saved by the hypervisor to main memory.
`The hypervisor replaces these processor settings with a set
`of processor settings associated with software routines or
`data structures provided by the guest operating system.
`These software routines or data structures may include
`exception and interrupt handler routines and page tables. As
`a result of the substitution of processor settings, the host
`operating system is decoupled from processor controlin that
`at least some of the processor settings of the processor are
`associated with software routines or data structures provided
`by the guest operating system, and are no longer associated
`with software routines or data structures provided by the
`host operating system. To recouple the host operating system
`to the processor, the hypervisor reads in the saved processor
`settings from memory and writes these processorsettings to
`the appropriate registers of the processor.
`The logical decoupling and recouping method disclosed
`herein is advantageous in that it allows the guest operating
`system to be more closely aligned with the processor for
`some functionality that can be provided by the guest oper-
`ating system. In this manner, exception handlercalls, inter-
`rupt handler calls, and memory managementcalls need not
`be passed from the processor to the host operating system
`before being passed to the guest operating system. Rather,
`these calls from the processorare passeddirectly to the guest
`operating system via the hypervisor of the emulation pro-
`gram.
`The methoddisclosed herein is also advantageousin that
`the hypervisor or decoupling tool of the emulation program
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`need not have access to the source code of the host operating
`system. Rather, the hypervisor decouples the host operating
`system from the processor in a mannerthat is transparent to
`the host operating system, which has no awareness thatit has
`been decoupled or recoupled to the processor.
`The method disclosed herein is also advantageous in that
`even if the host operating system is decoupled from the
`processor with respect to some functionality normally pro-
`vided by the host operating system,
`the host operating
`system remains coupledto the host processor for the remain-
`der of the functionality of the host processor. During this
`period, the host operating system continues to manage much
`of the hardware functionality of the computer system, allow-
`ing the guest operating system to route a print request
`through the host operating system.
`Other technical advantages of the present invention will
`be readily apparent
`to one skilled in the art from the
`following figures, descriptions, and claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A more complete understanding of the present invention
`and advantages thereof may be acquired by referring to the
`following description taken in conjunction with the accom-
`panying drawings, in which like reference numbers indicate
`like features, and wherein:
`FIG. 1 is a diagram of the logical relationship of the
`elements of an emulated computer system running in a host
`computer system;
`FIG. 2 is a flow diagram of the method for logically
`coupling a hypervisor of an emulation program to the
`processor of a computer system; and
`FIG. 3 is a diagram of the logical relationship of the
`elements of an emulated computer system in which a
`hypervisor is logically coupled to the processor of the
`computer system.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`Thepresent invention provides an emulation environment
`that allows the emulation software access to the lowerlevel
`hardware components of the host computer system. The
`invention involves an emulation program that includes a
`hypervisor that is transparent to the host operating system.
`The hypervisor of the emulation program logically discon-
`nects or decouples the operating system from exclusive
`control of the host computer system for brief periods, during
`which time the hypervisor of the emulation program is
`placed in control of the hardware of the host computer
`system,allowing the emulation program to be logically near,
`for brief periods, certain hardware features of the host
`computer system.
`The processorstate of the processor is a snapshotofall of
`the processorsettingsat a single pointin time. Thesesettings
`include both data that the processor is manipulating as well
`as the program counter, pointers, and other operationalflags
`used by the processor. Because the data being manipulated
`by the processor and many other processor settings may
`change with each processor cycle, the processor state may
`likewise change with each processor cycle, and may change
`as often as many millions of times per second.
`One subset of the processor state is the user state. Taken
`together, the data being manipulated by the processor and
`the processor’s program counter comprise the user state of
`the processor. The user state is so named because the values
`that comprise the user state can be manipulated by an
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`US 7,085,705 B2
`
`5
`application-level program. The remainder of the processor
`settings of the processor state comprise the supervisor state
`or privileged state of the processor. The values of the
`supervisor state can only be modified by softwarethat is part
`of the operating system of the computer system. Thesettings
`of the supervisor state or privileged state of the processor
`state cannot be accessed by an application-level program.
`The separation of processor settings between a userstate,
`which is accessible by application-level programs, and a
`supervisor state, which is not accessible by application-level
`programs, allows the operating system to remain functional
`even if the application level program crashes or causes a
`fatal error.
`
`The settings of the supervisor of privileged state of the
`processor generally fall into one of several categories. One
`category of the supervisor state of the processor is the
`processor’s mode flags, which include the settings that
`instruct the processor to operate according to one of several
`modesto support certain computationalsituations, exception
`behavior, support for legacy programs, or the selective use
`of newer features of the processor. Another category of
`settings of the processorstate are those settings that control
`external hardware access. Processors often support several
`operational settings for communication between the proces-
`sor and hardware external to the processor, such as caches,
`memory, and other input and output devices. Because these
`operationalsettings, including the communication speed and
`bandwidth, for example, can only be modified by privileged
`or supervisorlevel code, they are consideredto be part of the
`supervisor state of the processor.
`Another category of settings of the privileged state of the
`processor are the exception andinterrupt routine pointers.
`Whenthe processor encounters an exception or is asked for
`an interrupt, the processor stops execution at the current
`program counter address and begins execution at a prede-
`termined exception routine address. The location of these
`exception routines are identified through the use of excep-
`tion routine pointers. For some processors, the exception
`routines are located at hard-coded memory addresses. On
`most processors, however, their locations are programmable
`and the value of the locations are consideredto be part of the
`supervisor state of the processor.
`A set of data structure pointers make up another category
`of the privileged state of the processor. Because some data
`structures of the processorstate are too large to be stored in
`the processor,
`these data structure are stored in main
`memory and a pointer to the data structure is stored at the
`processor. An example of this sort of large data structure is
`the processor’s page tables. These tables define for the
`processor the logical-to-physical
`translation of memory
`addresses that are necessary for the conversion of virtual
`memory accesses to physical memory locations. Both the
`page table and the pointer to the page table, which is stored
`at the processor, are considered to be part of the supervisor
`state of the processor. Another example ofa data structure of
`the processor’s supervisor state that
`is stored in main
`memory is an exception routine pointer table. Rather than
`storing the pointer for each exception routine at
`the
`processor, a single pointer stored at the processor can point
`to a table of exception routine pointers. The exception
`pointer or vector table will
`include a listing of address
`pointers to the exception handlers accessible by the proces-
`sor. Both the exception routine pointer that is stored at the
`processor and the exception routine pointer table are con-
`sidered part of the supervisorstate.
`The host operating system typically establishes for the
`processor the vectors or pointers to the exception and
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`interrupt handler routines. If, for example, the processor is
`instructed to process a set of commandsthat will cause the
`processor to divide by zero,
`the processor will call the
`exception handler routine that handles the divide-by-zero
`exception. In doing so, the processor may call an exception
`handler routine that is pointed to by a vector stored at the
`processor. Alternatively, the processor may scan the excep-
`tion vector table for the correct exception handler for the
`exception condition and then call
`the exception handler
`using the exception vector or pointer associated with the
`applicable exception handler.
`Whenthe host operating system is in logical control of the
`host processor, the host operating system defines for the host
`processor the exception vectors and all other vectors that
`will be needed by and are supported by the host processor.
`Should the processor encounter an exception condition or
`need to access another routine that is referenced by a vector,
`such as the page table routines and the page table vector, the
`processor executes the host operating system’s exception
`handler.
`
`In the case of an emulated computer system, an emulation
`program provides an emulated operating environmentin the
`host computer system. Shownin FIG. 1 is a diagram of the
`logical layers of the hardware and software architecture for
`an emulated operating environment in a computer system
`10. An emulation program 14 runs on a host operating
`system that executes on the host computer system hardware
`or processor 11. Emulation program 14 emulates a guest
`computer system 16, including a guest operating system 18.
`Guest application programs are able to execute on guest
`operating system 18. In the emulated operating environment
`of FIG. 1, because of the operation of emulation program 14,
`guest application 20 can run on the computer system 10 even
`though guest application 20 is designed to run on an oper-
`ating system that is generally incompatible with host oper-
`ating system 12 and host computer system hardware 11. In
`the architecture of FIG. 1, guest operating system 18 is
`separation from the host computer system hardware 11
`across several logical and software layers, including the host
`operating system 12. This logical separation introduces
`latency and performance difficulties in those instances in
`which the guest operating system attempts to communicate
`directly with the host computer system hardware 11.
`In the example of FIG. 1, host operating system 12 is in
`exclusive operating control of the host computer system
`hardware 11, including the processor of the host computer
`system. The host operating system will have established for
`the processor of the host computer system a numberof the
`settings of the processor state. For example, the host oper-
`ating system 12 may haveestablished a set of exception
`handler vectors, whether located in a vector table or in the
`registers of the host processor, a set of interrupt handlers,
`and a page table vector. Thus, when the processor makes
`exception handler calls, interrupt handler calls, or memory
`managementcalls, the processor settings for these calls is
`provided on an exclusivebasis by the host operating system.
`Because ofthe host operating system establishedthe settings
`of the supervisororprivileged state of the processor, the host
`operating system is said to be in logical control of the
`processor of the host computer system.
`According to the emulation technique of the present
`invention, the emulation program itself includes a hypervi-
`sor that is able to logically disconnect or decouple the host
`operating system from exclusive control of the processor
`and other host computer system hardware 11. The hypervi-
`sor of emulation program 14 accomplishes the logical dis-
`connection step by reading in and saving to a memory
`
`

`

`US 7,085,705 B2
`
`7
`location the vectors and other address pointers that are used
`by the host processor. A flow diagram of the steps taken by
`the hypervisor to logically disconnect the host operating
`system from the exclusive control of the host computer
`system and to logically connect or couple the hypervisor of
`the emulation program to the host computer system are
`shown in FIG. 2. When the hypervisor of the emulation
`program wants to assert control over at least some of the
`processorsettings of the processor, the hypervisor at step 24
`reads in someor all of the settings of the supervisor or
`privileged state of the processor. According to one embodi-
`ment of the invention, the processor reads in the address
`pointers from the applicable registers of the processor,
`including the exception vectors or the pointer to the excep-
`tion vector table, the interrupt pointers or the pointer to the
`interrupt routine table, and the pointer to the page table. At
`step 26,
`the hypervisor saves these processor settings,
`together with an identification of their associated storage
`location on the host processor, to memory. The hypervisor
`next substitutes at step 28 the user-level processor state of
`the guest operating system andthe privileged-level state of
`the hypervisor of the emulation program. As a result, the
`processor settings of the host processor are replace with a
`combination of the user-level processor state of the guest
`operating system and the privileged-level state associated
`with the hypervisor of the emulation program. In doing so,
`the hypervisor stores in the appropriate registers of the
`processor the vectors and other address pointers to the
`exception handlers, interrupt routines, and page maps of the
`hypervisor of the emulation program andthe guest operating
`system.
`Because the processor settings that are substituted by the
`hypervisor of the emulation program are supervisor or
`privileged level settings, the hypervisor of the emulation
`program has logical control of the processor for all of the
`substituted processor settings. In this manner, the emulated
`computer system is logically in control of the hardware
`functionality of the host computer system for the function-
`ality governed by the substituted processor settings. A dia-
`gram ofthe logical relationship of the emulation program 14
`following substitution of the processor settings is shown in
`FIG. 3. Hypervisor 22 in FIG. 3 is shown as being a
`component of emulation program 14, which is shown as
`having a logical communication link to the processor and
`host hardware 11.
`
`As an example of the emulation program’s logical control
`of host hardware 11, if an exception were to occur during
`this period, the processor would call an exception handler
`provided by hypervisor of the emulation program. Similarly,
`if the processor is called on to translate a virtual memory
`address to a physical memory address, the processor will
`access the page table associated with the guest operating
`system. Thus, many settings of the processor states have
`been replaced so that
`the processor is calling upon or
`accessing software or data structures provided directly by
`the guest operating system. This allows the guest operating
`system to logically align itself more closely with the pro-
`cessor of the computer system, and eliminates the latency
`caused by separating the guest operating system from the
`processor of the computer system across the host operating
`system.In the case of an exception, the exception handler of
`the hypervisor may handle the exception itself or the excep-
`tion handler of the hypervisor may invoke the exception
`handler of the guest operating system, allowing the guest
`operating system to directly handle the exception without
`the necessity of having the exception call pass through the
`host operating system software layer.
`
`35
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`40
`
`45
`
`50
`
`8
`As shown in FIG. 3, host operating system 12 is not
`permanently disconnected form the hardware of the host
`computer system. The logical control asserted by the hyper-
`visor over a set of processor settings does not result in
`hypervisor 22 assuming responsibility over all the hardware
`interaction in the computer system. During th