United States Patent
`
`
`Castrucci
`
`(15) 3,702,464
`£451 Nov. 7, 1972
`
`(541 INFORMATION CARD
`References Cited
`
`[56]
`
`[72]Inventor: Paul P. Castrucci, Poughkeepsie,
`UNITED ST ATES PATENTS
`N.Y.
`3,604,900
`9/1971
`Kalt .................... 235/61.12 N
`
`
`
`
`[ 7 3] Assignee: International Business Machines
`4/1966
`3,245,051
`
`
`Robb .................... 340/173 SP
`
`Corpontion, Armonk, N.Y.
`3,258,644
`6/1966
`
`
`
`Rajchman .......... 340/174 MA
`3,548,254
`12/1970
`
`
`Pahlavan ............ 340/174 MA
`[22]Filed:May 4, 1971
`3,637,994
`1/1972
`
`
`
`Ellingboe ............ 235/61.12 N
`[21]Appl.No.: 140,174
`
`
`M. Urynowicz, Jr.
`Primary Examiner-Stanley
`
`Attorney-Hanifin and Jancin and Henry Powers
`[52]U.S. Cl .. 340/173 SP, 235/61.12
`N, 235/61.12 C
`
`[51] Int.CI . ... G06k 19/00,Gllc
`
`11/36,Gllc17/00
`[57]
`ABSTRACT
`I 58] Field of Search .... 340/174 SP, 174 MA, 173 SP,
`
`
`
`
`340/149 A; 235/61.12 R, 61.12 M, 61.12 C,
`An information card for credit and accounting system
`
`
`
`61.12 N; 307/303
`
`having a monolithic or solid state memory for storage
`
`
`
`of information responsive to computer controlled
`systems.
`
`
`1 Claim, 12 DrawlnJ Figures
`
`6
`
`IPR2022-01239
`Apple EX1019 Page 1
`
`

`

`D NOV 7 1972
`PATENTE
`3,702,464
`SHEET 1 OF 4
`
`I
`
`6
`
`t_15
`
`FIG. 2
`
`4
`
`9
`
`3
`
`FIG. 1
`
`Q Q QQ Q
`
`7
`
`8
`
`FIG. 3
`
`INVENTOR
`
`PAUL P. CASTRUCCI
`
`BY
`
`ATTORNEY
`
`IPR2022-01239
`Apple EX1019 Page 2
`
`

`

`PATENTED
`NOY 7 1972
`
`3,702,464
`
`SHEET 2 Of 4
`
`Bo
`
`w
`
`30
`
`50
`
`44
`
`48
`
`FIG. 5
`
`FIG. 6
`
`FIG. 7
`
`44
`
`FIG. 8
`
`IPR2022-01239
`Apple EX1019 Page 3
`
`

`

`PATENTED
`NOY 7 1972
`
`3,702,464
`
`SHEET 3 Of 4
`
`...---38
`
`/
`
`32
`
`....---42
`
`36
`
`r-, I I
`L_J I
`' I I
`
`30
`
`34
`
`FIG. 9
`
`54h
`
`-50h
`
`52 h
`
`52g
`
`r1
`I I
`I I
`I I
`LJ
`
`72
`
`r1
`I
`I I
`I I
`I I
`LJ
`
`80
`
`70
`
`'/ii
`r 7
`I'
`I I I
`I I
`I I
`LJ
`
`56f
`
`56e
`
`54 f
`
`54e
`-50e . \
`
`52 f
`
`52e
`
`r7
`I I
`I I
`I
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`
`72
`82
`
`r,
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`I I
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`84
`70
`
`86/f
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`I
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`,7
`I I
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`u
`
`52a
`
`52b
`
`52d
`r50d
`
`54a
`
`54b
`
`54c
`
`I
`56b'
`
`56c
`
`56d
`
`FIG. 9A
`
`IPR2022-01239
`Apple EX1019 Page 4
`
`

`

`PATENTEO
`NOY 7
`1972
`
`3,702,464
`
`SHEET " Of 4
`
`87
`
`SENSE
`AMP
`
`----
`
`81
`
`WORD DRIVE
`
`WORD DRIVE
`
`WORD DRIVE
`
`WORD DRIVE
`
`I 81
`
`WORD DRIVE
`
`89
`
`Ic
`
`
`
`-
`VB
`
`-- - -
`
`FIG. 10
`
`REGIONAL
`STATION
`
`�--- CPU
`
`CENTRAL
`STATION
`CONSOLE
`
`FIG. 11
`
`89
`
`91
`
`D
`E
`
`D
`E
`
`IPR2022-01239
`Apple EX1019 Page 5
`
`

`

`3,702,464
`
`1
`2
`INFORMATION CARD
`No. 3,245,051 No.
`No. 3,191,151,
`3,028,659,
`3,445,823.
`and No.
`No. 3,423,646
`3,384,879,
`FIELD OF THE INVENTION
`are not only
`cards of this invention
`The information
`but can also be used
`information,
`capable of containing
`cards, and more
`to information
`relates
`This invention
`data bank utilizing
`con­
`data at a central
`to manipulate
`to an information card for use as credit 5
`particularly
`ventional computer communication systems
`as in­
`cards and the like.
`cards, accounting
`the credit rating of an in­
`above. For example,
`dicated
`DESCRIPTION OF THE PRIOR ART
`data
`from the central
`could be transmitted
`dividual
`and result in additional
`in-
`cards have found wide spread use in bank through the terminal
`Information
`lO formation being placed in the card, which information
`Heretofore,
`sales, bank and other varied transactions.
`code the card with the in-
`in these cards has been em- could, as an illustration,
`contained
`information
`The credit risk would then be per-
`credit risk.
`. dividual's
`and incorporation
`bodied in the form of embossments
`in the data card. Typically,
`if the
`recorded
`as well as optically dif-manently
`magnetic material,.
`of codeable
`for purposes of encoding inform a-15 data bank issued a poor credit risk, the information
`ferential
`material,
`chip and void the credit
`in the memory
`and could be placed
`and financial
`of the holder,
`tion as to the identity
`This same kind of
`with the card for any subsequent transactions.
`In conjunction
`business record of the holder.
`cards which were
`cards (such as credit cards), process could be used in cancelling
`use of such information
`holder ultimate
`lost or stolen and give the individual
`have been advanced to facilitate
`various innovations
`use of such cards and also to expedite control 20 security.
`further
`thereof for purposes of security and recordal
`of Credit cards which would have large monetary
`with a personal
`Among the more sig-values or risks could be constructed
`therewith.
`associated
`transactions
`associated with such informa-security code. In this manner, in addition
`to standard
`developments
`nificant
`code informa-
`security
`computers for credit and personal information,
`tion cards are systems utilizing
`or via 25 tion could also be entered
`and stored in the monolithic
`either on-site
`and control thereof,
`processing
`the card, one
`processing memory of the card. In order to activate
`systems at a remote central
`communication
`and punch a matching
`conventional would insert it in a terminal
`utilizing
`Typical of such systems,
`station.
`code via a keyboard entry of a self contained
`are those described in the fol-security
`configurations,
`computer
`transmission
`computer
`or one in a conventional
`3,353,006 station
`3,245,697,
`lowing U.S. Pat. Nos.: 3,022,381,
`30 system as for example,
`see U.S. Pat. No. 3,245,697.
`If
`and 3,513,298.
`a cen­
`the card would activate
`the code data matched,
`SUMMARY OF THE INVENTION
`the transaction.
`tral data bank and validate
`card of this
`the information
`with this inven- In another application,
`in accordance
`It has been discovered
`could also be used as
`a form of modern travel
`ac-35 invention
`cards, for use as credit,
`tion that novel information
`al could purchase
`an individu
`cards and the like, in computer check. In this application,
`count cards, identity
`value,
`from a bank, a card which had a fixed monetary
`by incorporating
`systems can be fabricated
`controlled
`of such systems within such cards for control-at which time the .memory in the card would be loaded
`elements
`personal and monetary data. As
`in response to such with the individual's
`therein
`information·
`lably entering
`utilized
`his card, the value
`cards can be 40 the individual
`Such information
`computer systems.
`of his
`account,
`from a central
`or solid purchases would be deducted
`therein monolithic
`formed by incorporating
`in his card
`computer and· the balance of the value remaining
`state memories such as employed in various
`from the data bank. In
`would be updated electrically
`configurations.
`memories com- this fashion,
`such monolithic
`Broadly speaking,
`could spend his card; with
`the individual
`automatically
`credited
`in a semiconductor
`prise a matrix of solid state switches
`45 the value of his transactions
`of binary from the individual's
`state for placement
`chip, having an alterable
`data bank,
`at the central
`account,
`to electrical activation.
`in response
`therein
`information
`furnishing the purchased
`to the business establishment
`this memory may comprise a items or services
`In one embodiment
`to the individual.
`to pro-
`it is an object of this invention
`diode Accordingly,
`back-to-back
`matrix of solid state monolithic
`card, for use as a credit card,
`a data point so vide a novel information
`pairs wherein each pair of diodes represent
`Ser. No. an account card and the like.
`U.S. application
`in copending
`as disclosed
`858,053 filed Sept. 15, 1969, now U.S. Pat. No. Anotherobjectofthisinvention
`istoprovidea novel
`with data
`card adapted for and compatible
`information
`and assigned to the assignee of this applica-
`3,641,516
`card would, as fabricated,
`tion. Such an information
`processing unit.
`is to provide a
`i.e. all 5S A further object of this invention
`contain a memory devoid of any information,
`could be inserted into a suita-novel information
`zeros. The card, on issue,
`or solid
`a monolithic
`card containing
`signals to state memory adapted for communication
`electrical
`which would multiplex
`ble terminal
`with com-
`systems.
`puter processing
`the proper matrix in the memory chip. The electrical
`is to provide a
`at the selected m11trix position would A still further object of this invention
`energy arriving
`elements ( e.g. the back-60 novel information
`electrical
`alter the associated
`memory hav-
`card with a monolithic
`to-back diode pair) in such a way as to produce a per- ing its information
`to computer
`content responsive
`i.e. transforms
`�ro co,itrolled processing
`state,
`manent change of electrical
`systems.
`and ad-
`load The foregoing and other objects, features
`one could electrically
`into a one. In this fashion,
`card. 65
`into the memory of the information
`will become more apparent
`vantages of this invention
`information
`which could be adapted from the following
`of elements
`Other matrixes
`description
`of the
`more particular
`memories of the information
`cards invention,
`into the monolithic
`with the accompanying
`in conjunction
`in U.S. Pat. No. drawings.
`are those illustrated
`of this invention,
`
`IPR2022-01239
`Apple EX1019 Page 6
`
`

`

`3,702,464
`
`O • -
`
`3
`4
`BRIEF DESCRIPTION OF THE DRAWINGS In its broad aspect, the monolithic memory compre-
`
`
`
`
`
`as in FIG.may be configured, FIG. 1 is a perspective view of an embodiment of this hended in this invention
`B0 • • -B,. and W
`S, as a grid of crossed conductors
`
`
`
`
`
`
`
`invention having portions broken away to illustrate the W,., each electrically isolated from each other with bi-
`
`
`
`
`
`
`solid state switching interior construction of the embodiment. 5 lateral elements 11 positioned and
`
`FIG. 2 is a fragmentary view of a portion of the em-
`
`
`
`cross-connected at the cross-over points, for activation
`
`bodiment of FIG. 1.
`
`
`
`of the elements to electrical passive and active states
`
`FIGS. 3 and 4 are fragmentary views illustrating
`
`
`binary coding to the conventional details in the fabrication of the embodiment of FIG. 1. corresponding
`
`
`
`
`
`system as more particularly described below. Informa-
`
`
`
`FIG. 5 is a schematic drawing of the monolithic or 10 tion may be optionally
`
`stored in this manner by forming
`
`
`
`
`
`
`and inactive solid state memory comprehended for incorporation in a matrix of active elements in a required
`the embodiment of FIG. 1 for storage of it)formation
`
`manner.
`therein.
`
`
`The conductor strips 9 and terminals 10 in conjunc-
`
`
`
`
`a FIG. 6 is a schematic drawing of a specific memory tion with cover layer 3 may conveniently constitute
`formed in a semiconducto
`matrix
`r device
`or chip com-15 printed
`board which may be formed by conven-
`circuit
`
`
`
`
`prehended for use in the information cards of this in-tional techniques from a conductor clad sheet of
`
`vention.
`
`
`
`dielectric material, as for example, Mylar.
`
`
`
`
`FIG. 7 is_ a sche�atic of a portion of_ the_ memor;: of The opposite ends of the conductor strips 9 ter-
`FIG. � for illustrating the mode of stonng information
`
`
`20 minate
`
`at a contact area 12, of outer board 3 in a pat-
`therem.
`
`tern for mating with contacts 8 of the monolithic
`.
`.
`.
`Fl�. 8 1s an exaggerate
`� view of a cross section of_a memory chip 7.
`
`
`
`
`
`
`specific example of a semiconductor cell employed m For assembly of information card 7 the memory chip
`the memory of FIG. 6 and_7• .
`7 may be superimposed as shown in FIG. 3, on the con-
`.
`FIGS. 9 and 9A are plam views of the basic structure
`
`
`8,25 tact area 12 of cover sheet 3, for mating of contacts
`of FIG· 8. .
`
`
`. of chip 7, with the corresponding portions of conductor
`. .
`.
`FI�. 10 1s? partial
`
`
`
`hereto by any con-schematic and partial block d!a• strips 9, and appropriately secured
`
`
`
`
`
`
`manner as by solder-reflow gram lllustratmg the use of fuseable cell as part of wnte venient of the contacts 8.
`once read ?nly memo�y.
`
`
`
`After connection of chip 7 to the conductor strips 9 of
`.
`FIG: l l 1s a �lock d1agra� o_f a typ_ical system
`for use 30 cover sheet 3, the chip may be secured
`and safeguarded
`
`of the information card of this mvenuon.
`
`by means of a guard or inner sheet 2 which receives the
`
`
`
`
`to encompass 13 dimensioned an aperture DESCRIPTION OF THE PREFERRED chip within
`
`
`the chip which typically will have dimensions of 152
`EMBODIMENTS
`
`
`mil length X 152 mil width x 15 mil thickness. The
`the information
`As shown in the drawings,
`card 1 of 35 inner and outer layers
`2 and 3 may be suitably
`in-
`
`
`
`
`
`this invention, as seen in FIG. 1, is a multilayer as-tegrated in any conventional manner, as by adhesives.
`
`
`sembly of suitable sheet material such as plastic,
`
`
`Further protection of memory chip 7 can be obtained
`
`
`
`
`
`wherein an inner layer 2 is interposed between outer or by use of resilient potting material 14, such as Dow
`
`
`
`
`Sylgard and RTV which is commercially cover layers 3 and 4. Each of layers 2 and 4 are shown Corning's
`with cover layer 3 hav-40 available
`with each other,
`in coextension
`from the General
`Corporation
`Electric
`and
`
`
`
`ing an additional extension to form a tongue or tab por- the Stauffer Company deposited in the free area or gap
`
`
`tion 5. In one form the card 1 may be formed of a 15 in aperture 13 defined between the chip 7, inner
`
`
`laminated array of suitably rigid plastic sheets, such as sheet 2, cover sheet 3 and the other outer or cover
`
`
`dimensions
`Mylar, whose physical
`are held in suffi-45 sheet 4 which is superimposed
`on and integrated to
`
`
`
`and the like. Use of the ciently close tolerance to facilitate insertion in a socket inner sheet 2 by adhesives
`
`
`
`
`
`
`
`
`system. To assist of a card reader in a computer in the potting material 13, also enables use of flexible plastic
`
`
`
`
`alignment of the card in the reader, one corner of the materials such as polyvinyl chloride in the fabrication
`
`
`
`
`potting materi-card 1, at the tab portion 5, may be bevelled as at 6. of this card. In this manner the resilient
`
`
`within card 1, is a monolithic or solid state 50 al will permit flexure
`
`of the card so as to accommodate
`Embedded
`
`
`
`
`memory 7, suitably formed in a semiconductor chip or displacement of the chip and prevent breaking of its
`
`
`
`
`
`strips 9. Alterna-substrate as more particularly described below, for in-electrical connection with conductor
`
`
`
`
`
`
`sertion of personal and monetary data of the holder. tively, with use of flexible plastic materials in the card,
`
`
`
`
`
`
`Optionally and although not required, the card may the flexible inner plastic sheet 2 may be provided with a
`information
`by 55 rigid inset sufficiently
`with supplemental
`however
`be provided
`dimensioned
`to contain
`an aper-
`
`
`
`suitable indicia on a face thereof indicating the account ture for receiving the memory chip 7. As will be ap-
`
`
`
`
`
`
`
`
`customer and issuing institution at which the card may predated, with use of flexible materials, such as ther-
`
`
`
`
`for the inner and outer sheets be honored. The memory 7, contains a matrix of solid moplastics of the cards,
`
`
`
`
`
`
`
`
`state electrical switching elements formed within a integration of the sheets may simply be effected by
`
`
`semiconductor substrate terminating in contacts 8 60 heating
`to the necessary temperatures.
`
`
`
`
`illustrative embodiment which are electrically connected within card 1, to a plu- One specific of a monolithic
`
`
`
`
`
`
`
`
`
`rality of conductor strips 9 extending within the card memory which may be used in the information cards of
`
`is shown in FIG. 6. This particular infor-with termination thereof at the exposed terminals 10 this invention
`
`
`
`
`
`
`is a mo�olithic 10 are 65 mation storage element
`
`
`carried on the tab portion 5. _These terminals
`
`writ_e once read
`mated with suitable contacts m the socket of a card only store (ROS) memory haVJng cells which are pre-
`
`
`
`
`
`
`
`are defined by as shown, alterable. These cells reader to establish communication with a computer dictably
`
`
`
`
`monolithically formed back-to-back diode pairs which
`processing system.
`
`IPR2022-01239
`Apple EX1019 Page 7
`
`

`

`3,702,464
`have unequal breakdown voltages with a metal contact the millisec
`ond range. This has been done by forcing a
`
`
`
`reverse diode via a current genera-directly connected to the region of semiconductor current through the
`
`forming the common part of said .back-to-back pair of tor and allowing the voltage to be assumed by the
`diode. The voltage will go from the breakdown voltage
`
`monolithic diodes.
`
`A twelve cell or twelve bit back-to-back diode matrix 5 of approximately
`7 or 8 volts down to less than one volt
`
`onds. Visual inspection of is illustrated in FIG. 6 for the purpose of illustrating the in a matter of millisec
`
`
`relationship of a cell to an ROS memory. The matrix photomicrographs of a fused junction show a metallic
`four bit lines Bu- B3, three work lines W o-W 2, looking connection extending between the metal lands.
`comprises
`
`and twelve cells, each connected between one bit line It is believed that the current applied to the diode
`and one work line. The cells are identified herein by the 10 heats the diode in the area
`
`of the junction to the eutec-
`
`
`onductor causing lines they are connected to, e.g. the cell containing tic temperature of the metal-semic
`as cell Bo WO or cell, COO. atomic alloying of the metal and semiconductor.
`diodes D1 and D1 is identified
`The incorporation of an alterable
`cell in a semicon-
`diodes prevent conduction
`The back-to-back
`
`
`show between the word and bit Jines provided the applied ductor chip is illustrated in FIGS. 8 and 9,·which
`breakdown voltage of the 15 the side and top views respectively
`of the same cell.
`is below the reverse
`voltage
`48 has an n + "subcol-·reverse biased diodes. Such a reverse biased diode can A p-semiconductor substrate
`
`
`
`
`
`
`the two which is underneath be shorted by applying a relatively low level current lector" region 46 therein
`
`thereto. The phenomenon, called fusing, can be selec-di� es of the eel�. The suix: ollector is not re9uired
`but,
`to the cells by applying a fusing voltage 20 as �s �ell known � �e art, rmpr�ves the device charac-
`
`tively applied
`
`layer 50 1s formed on the p-sub-or current between or to one word line and one bit line. tenst1cs. An n-ep1taxial
`
`(inter-Assuming cell 12 is selected for fusing and the polarity strate 48, and the cell is electrically isol�ted
`
`
`
`of the applied signal is such that diode D14 is reverse nally) _from �ther �lemen� on the same c�1p by a sur-
`bias ed, diode D14 will fuse and thus a highly conduc- roundmg p + 180�atio� re_gion 44. T�o � regions, 38 and
`
`between W 1 and 82 in the for-25 42, formed by d�usion mt? the epitaxial
`layer 50, fo?Jl
`tive path will be provided
`
`
`back-to-back diodes by virtue of the _P-n boundanes
`
`ward direction of non-fused diode D13.
`the reve_rse
`The Cl2 can now be said to represent one state created. For the purpose of dec�easmg
`
`bre�down v?ltage
`0� on� of the diodes and n + region
`
`which is opposite to the state it previously occupied.
`
`
`layer 50 betw7en the two P The two states can be detected in a conventional matrix 48 !s formed m the epitaxial
`
`n by applying a voltage or current to one line 30 regio�s 38 and 42, �nd touches P re�ion 38. The
`applicatio
`to the P r
`es�lts
`connected to the cell and sensing the change in current !ouchmg of th
`+ r
` nak
`gion 40
`gion 3
`1
`or voltage in the other line connected to the cell. A m � r�verse re. own vo tage at t e p-n arner
`· f th t d "b d th h th bTt f which 1s substantially
`
`less than the reverse breakdown
`ma!nx O _e ype escri e us as e capa 1 1 Y
`
`
`O voltage of the p-n barrier formed by either of the p re-
`acting as wnte once read only store.
`• 38 42 d th ·tax ·al · 50
`this may be seen by assuming that the 35 gions • . an e epi 1 . re�ion • . .
`Typically
`
`The semiconductor matenal 1s preferably sd1con but
`.
`.
`polanty of the applied currents and voltages are such th
`
`al be •t bl •n b
`• d b
`that the even numbered diodes are the reverse biased O ers may . so _su! a e, as WI . e rec?gmze . Y
`d h odd b d d' d th ,, d those of ordinary skill
`
`m the art. An insulating coating
`d. d
`10 es an t e num ere 10 es are e ,orwar 30 h
`d' d 014. 11 Cl2
`, sue . as s1 icon 1ox1 e covers the surface of the
`T d" ·d
`b. d d' d Th h
`1ase 1� es. e � 0� across 10-es m ce 40 chip and holes are made therethr
`ough for the purpose
`and D24 in c�!l 2� md,1,c�te that cells �2.and C23 �ave of allowing metal conductors to contact the semicon-
`
`
`
`at appropriate alrea�y �een wntten mto. Ass_ume It is now_d�s,red ductor material positions. Metal 34,
`to wn�e mto cell Cl�. As descnbed abo�e th1s is �c- forming a bit line, contacts the p region 38; metal 36,
`quantity forming a word line, contacts the p region 42; metal 32
`by applying the proper electn_cal
`complish�d
`between Imes W 1 and 83 to fuse reverse
`dmde Dl6• It 45 contacts then-type conductivity
`region, specifically
`the
`
`�an _be seen 1!1at an �temate pa� between YI 1 and Ba n + region 40. The metal is preferably aluminum but
`
`1s: diode 13, hne B2, diode �22, line W2 and_ dmde J?23. may be other metals such as aluminum-copper or gold.
`
`
`
`
`ng suitable Cons�quently, the reverse b�as voltage applie� to diode In selecti semiconductor material and metal,
`
`
`
`criteria used in the selecti021 is the same as that applied to the target diode 016 other than the standard
`on
`except for the small forward voltage drops of diodes 50 process for making integrated
`an additional
`circuits,
`D13 and_D23. .
`
`
`criteria here appears to be that the eutectic tempera-
`.
`.
`
`on of diode 021 1s overcome by ture of the metal-semiconductor be below the melting
`Undesired alterati
`making the diodes in the cell so that the diodes to. be
`point of either the metal or the semiconductor.
`
`fused have lower breakdown voltages than those which The metal 32 is defined herein as a free metal free
`are not to be fused. For example a seven volt break-55 metal contact,
`or free metal land. The designati�n
`"-
`
`down voltage for the even numbered diodes of FIG. 7 free" connoting that the metal applied to the N+ region
`
`and a 20 volt breakdown voltage for the odd numbered is not connected to other circuit elements in the chip.
`diodes of FIG. 7 insure that in the above described For example the bit line 34 is to be connected to a
`
`
`situation, diode D16 alone would be fused. When suffi- group of diodes and to sense amplifiers and other cir-
`on, is ap-60 cuits;
`cient power, by current or voltage applicati
`the word line 36 is to be connected to a group of
`
`plied to a selected diode for a sufficient period of time, diodes and to word drive and possibly other circuits.
`
`
`a metal semiconductor alloy forms substantially at the Tlie fusing current/voltage is applied to the bit and
`
`
`surface of the semiconductor material, but below the word lines. The free metal 32 serves the purpose of
`
`typical oxide covering layer, and connects the metal 65 providing a terminal for the aluminum-silicon
`alloy
`
`
`
`lands on both sides of the junction thereby shorting the connection formed during the fusing process, and also,
`
`
`junction. Currents substantially below 200 ma have presumably, as a supplier of aluminum atoms for for-
`been used to "fuse" diodes in this manner at times in mation of the aluminum silicon alloy,
`
` br
`+8
`
`s
`
`6
`
`he
`
`de
`
`be
`
`IPR2022-01239
`Apple EX1019 Page 8
`
`

`

`n
`
`n
`
`P diffusion
`N+ diffusion
`P+ diffusion
`N epitaxial
`N+ subcollector
`
`1019 Boron atoms/cc
`I 011 Pholphorous atoms/cc
`I 0"1 Boron atoms/cc
`IO" Arsenic atoms/cc
`I 011 Arsenic atoms/cc
`
`3,702,464
`8
`7
`
`In FIG. 9 the p and n+ and n epitaxial regions are
`ments formed on a chip is shown in FIG. 10 for a 16 by
`16 line matrix.
`
`delineated by dashed lines. The solid squares on the
`
`
`The matrix comprises 16 word or horizontal lines
`
`metal 32, 34, and 36 designate the contact holes
`
`
`
`through the oxide coating 30 directly under the metal.
`
`
`
`and 16 bit or vertical lines. A cell connection exists at
`
`
`between the con­In a specific example, the distance
`
`5 each word line-bit line cross point, but they are not il­
`
`
`tact hole metallization for the n+ region 40 and p re­
`lustrated
`
`in order not to clutter the drawing. Each word
`
`gion 38 is 0.25 mils and the dopant concentration of
`
`line is connected to a word drive circuit 81 which
`
`
`
`the conductivity regions are substantially as follows:
`
`
`
`operates when gated on to connect the respective word
`
`
`
`line to a ground or relatively positive potential. One
`
`10 word line is selected by a four bit binary code which is
`
`
`applied from an external source to the decode device
`
`
`
`83.The latter device gates on the word driver con­
`
`nected to the addressed line.
`Each of the 16 bit lines in the group is connected to a
`
`A device having the characteristics described was 15
`
`
`
`
`sense amplifier circuit 87 at one end thereof, and to
`
`found to fuse (in this case go from 8 volts to less than 1 one of the respective gates 89 at the other end thereof.
`
`
`
`
`volt) in about l to l O milliseconds under an appliedA particular bit line is selected by an externally applied
`
`
`
`
`address which is applied current of l 00 milliamperes, the current being appliedfour bit binary to a decode cir-
`
`by a constant current generator. An aluminum silico
`of decode circuit
`91 gates on the
`alloy connector connects metal lands 34 and 32 20 cuit 91. The output
`
`gate 89 which is connected to the addressed bit line
`
`
`
`
`
`connecting beneath the oxide coating 30 and shorts the p-n+ junc- thereby the addressed bit line to the ter-
`
`tion. It should be noted that the diode is not destroyedminals-
`V 8 and le-
`in the sense that a p-n or p-n+ junction no longer exists.In order to fuse the reverse
`diode at the intersectio
`
`
`
`
`However, since it is shorted it no longer serves as a bar-
`
`rier for current flow between the word and bit lines. 25 of bit line x and word line y, the addresses x and y are
`
`
`
`91 and 83to the decode circuits respectively An example of a portion of an integrated monolithicapplied
`
`
`
`which generatesmatrix comprising multiple cells and their respectiveand a constant current generator
`
`
`
`
`!0 _termin� le. _As illustrated, !he
`
`in FIG. 9A. The top view l� a is connected
`interconnections is illustrated
`pos i�iv� current
`flow Is i� the d1rect1o
`n from wo�� line
`of the illustrated
`portion of the monolithic
`matrix
`shows only eight cells S0a-S0g but it will be apparentto bit line._ The revers� diode fuses thereb� providi
`
`ng�
`30
`
`
`work lme y and bit_con�ect1on between that many more cells can be accommodated by the�on-b!ockmg
`
`
`
`line x in one duecti?n. .
`
`
`
`same layout scheme. The cells SOa-S0g are identical to
`and athe cell shown in FIGS. 8 and 9. The subscripts a-g are Fo_r read out, a bit and ':'ord linear': addre_ssed
`
`
`
`
`
`
`
`
`
`to ter-applied voltage is low level negative used to represent the identical features of the cells SOa relatively
`
`
`will 35 ?1i�al-Vs. The signal sensed
`by the sense �mplifier 86
`S0g respectively,
`and thus the description
`through
`
`the a�dressed cell cont�ns a fuse oromit the subscript and describe the cells collectively by md1cates w�ether
`
`
`
`
`
`
`
`
`as a bmary one orwhich can be interpreted the reference numerals alone. The cell S0a comprisesno-fuse,
`n connections 52a, 54a, and 56a which are zero..
`metallizatio
`.
`.
`to the p,n+ and p regions. The 40 !he particular
`
`arrangement �hown �n FIG. 10 1s not
`
`connected respectively
`
`
`
`
`
`suggest th_e�-nts w1�l r�addy Other arranget?e"reverse" diode or fuseable diode is formed by thecnt1cal.
`
`n S4a and selves to those of ordinary skill in the art and it 1s
`
`
`semiconductor regions to which metallizatio
`
`S6a are connected. The drawing also shows word line d_eemed unne�e� to sh?w fu�ther arrangeme
`
`n�
`
`
`or horizontal line metallization 80, 82, 84, 86. Each bit since _the applicatio
`n of the invention to ROS usage 1s
`sufficiently
`clear.
`
`
`line metallization is connected to a column of cells and 45
`
`for utilizing the information cards ofeach word line metallization is connected to a row of A typical system
`
`
`
`to cells S0bthis inv�nti�n is il�ustrated
`in F!G-11. In ?rocessi
`�g a
`
`
`cells. For example bit line 80 is connected
`
`
`
`m ainvolvmg the card, it may be inserted and S0g (and also to other cells in the same column-not transaction
`
`
`
`
`
`withn provided at a local statioshown) by metallization S6b and S6g. Word line 70, for socket of a card reader
`is connected to cells SOa, S0b, SOc and 52d, 50 conventional peripheral
`which typically
`�quipment
`in-
`example,
`
`
`
`
`may also be pro-a console and which usually respectively. An underpass connection interconnectseludes
`
`
`
`
`
`
`for enteringboard and a keyboard the word line metallization on opposite sides of the bitvided with a display
`
`
`
`
`n and activating the necessaryof the transactiolines. This allows a single layer of metallization for bitdetails
`
`
`
`
`
`
`If desired, an integral computerand word lines despite the crossover characteristic of computer operations.
`
`interconnections are known in 55 processing unit may be self-contained
`at the local sta-
`Underpass
`the layout.
`
`
`
`
`
`mayon appropriate activation the art and usually comprise a region of semiconductortion which alternatively
`
`
`
`be tied over transmission lines to a regional and/or a
`
`
`
`material doped to be relatively highly conductive.
`
`processing station, the latter two of which may
`
`
`Metallization contacts the doped region at oppositecentral
`
`
`also serve to centralize records. For convenience, the
`ends thereof.
`60 local station
`may also be tied directly
`
`As will be appreciated by any one of ordinary skill in
`to the central sta-
`
`
`
`
`unit may per-In any event, the selected computer the art, the monolithic or integrated structure will also tion.
`
`
`
`
`to process this transac-include driving, sensing and decoding circuits on theform the necessary operations
`
`
`
`
`
`
`
`
`suchindicate the results thereof and appropriately same chip. As these types of circuits are well known in tion,
`
`
`
`
`
`as the credit limits, transaction limitations, validity of
`
`
`the art and further since the specific form of these cir-
`
`
`
`
`may be shown on like. These results cuits is not a part of the present invention they will notthe card, and the
`65
`
`
`
`and em-board, typed out via the keyboard, be illustrated in detail herein. A partial schematic, par-the display
`
`
`
`
`
`
`
`
`and also the cardto update the central records tial block diagram of the circuit arrangement of the ele-ployed
`
`
`IPR2022-01239
`Apple EX1019 Page 9
`
`

`

`3,702,464
`
`10
`9
`via the card reader. If everything is in order, the
`
`. mined connection pattern matrix between selected
`
`
`transaction may be completed, with neces.,ary record­
`
`ones of said first terminals and said second ter­
`
`
`
`ing thereof within the processing system. Concurrently,
`minals;
`
`
`
`the keyboard, or printer if any, at the local station may
`a.wherein said access means comprises a plurality
`
`
`
`
`be activated to print-out a record of the transaction, 5
`
`
`of conductors extending within said card from a
`
`
`such as receipts, for the card holder, the establishment
`
`surface thereof to corresponding first and
`and/or the card issuer.
`
`second terminals of said memory device,
`While this invention has been particularly described
`
`
`
`b.wherein said circuit means comprises a diode
`
`
`
`with reference to the preferred embodiment thereof, it
`
`
`
`circuit selectively activated to active and inac­
`
`
`will be understood by those skilled in the art that the 10
`
`
`tive states in response to said access means, and
`
`foregoing and other changes in form and detail may be
`c.wherein
`
`made therein without departing from the spirit and
`i. said diode circuit comprises back to back
`
`
`scope of the invention.
`
`diode pairs connected between each of a cor­
`What is claimed is:
`
`responding one of . said first terminals and
`
`I. An identification device comprising:
`
`each of said second terminals to define open
`A. a card means;
`
`circuits therebetween and with the PN junc­
`B.an integrated programmable semiconductor
`
`
`tions of said diodes capable of permanent
`memory device disposed within said card in spaced
`
`destruction for short circuit thereof in
`
`
`
`
`relationship to the peripheral surfaces thereof and
`
`response to a reverse breakdown voltage
`comprising
`20
`
`across either of said junction in said diode
`
`a. a plurality of first access terminals,
`pairs and wherein
`
`
`b.a plurality of second access terminals, and
`ii.said access means is adapted to selectively
`
`
`
`c. a plurality of circuit means for connection of a
`apply a reverse breakdown voltage across
`
`corresponding one of each of said first terminals
`
`predetermined ones of said diode pairs to
`
`to each of said second terminals.
`25
`
`
`
`esta