`data in the semiconductor
`manufacturing environment
`
`Kenneth Tobin, Thomas Karnowski, Fred Lakhani
`
`Kenneth W. Tobin Jr., Thomas P. Karnowski, Fred Lakhani, "Integrated
`applications of inspection data in the semiconductor manufacturing
`environment," Proc. SPIE 4275, Metrology-based Control for Micro-
`Manufacturing, (5 June 2001); doi: 10.1117/12.429361
`Event: Photonics West 2001 - LASE, 2001, San Jose, CA, United States
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`Integrated applications of inspection data in the semiconductor
`manufacturing environment
`Kenneth W. Tobjn*, Thomas P. Karnowski', Fred Lakhani"
`
`aOak Ridge National Laboratory, Oak Ridge, Tennessee
`bjtemationa1 SEMATECH, Austin, Texas
`
`ABSTRACT
`
`As integrated circuit fabrication processes continue to increase in complexity, it has been determined that data collection,
`retention, and retrieval rates will continue to increase at an alarming rate. At future technology nodes, the time required to
`source manufacturing problems must at least remain constant to maintain anticipated productivity as suggested in the
`International Technology Roadmap for Semiconductors (ITRS). Strategies and software methods for integrated yield
`management have been identified as critical for maintaining this productivity. Integrated yield management must use circuit
`design, visible defect, parametric, and functional test data to recognize process trends and excursions so that yield-detracting
`mechanisms can be rapidly identified and corrected. This will require the intelligent merging of the various data sources that
`are collected and maintained throughout the fabrication environment. The availability of multiple data sources and the
`evolution of automated analysis techniques are providing mechanisms to convert basic defect, parametric, and electrical data
`into useful prediction and control information. Oak Ridge National Laboratory and International SEMATECH have been
`working to develop new strategies and capabilities in integrated yield management based on technologies such as Automatic
`Defect Classification (ADC), Spatial Signature Analysis (SSA), and Automated Image Retrieval (AIR). In this paper we will
`discuss a survey of these image-based technologies and their application to the ITRS issues that are driving the need for
`integration and data reduction.
`
`Keywords : semiconductor manufacturing, integrated yield management, automatic defect classification, spatial signature
`analysis, content-based image retrieval
`
`1. INTRODUCTION
`Semiconductor manufacturers invest billions of dollars in process equipment, and they are interested in obtaining as rapid a
`return on their investment as can be achieved. Rapid yield learning is thus becoming an increasingly important source of
`competitive advantage in the complex environment of semiconductor device fabrication. The sooner an integrated circuit
`the sooner the
`device
`yields,
`manufacturer can generate a revenue
`stream.
`rapid
`Conversely,
`identification of the source of yield
`loss can restore a revenue stream and
`prevent the destruction of material in
`process [1]. The 1999 International
`for
`Roadmap
`Technology
`Semiconductors (ITRS) states that:
`the face of this increased complexity,
`strategies and software methods for
`integrated yield management (IYM)
`have been identified as critical for
`maintaining productivity [2]. Figure
`1 represents this statement as a
`function of two critical parameters
`that are highlighted in the ITRS:
`critical particle size, and defect
`sourcing complexity. Critical particle
`size refers to the minimum size of
`
`,
`,
`
`' E
`
`__ 60
`°- - 40
`
`1 0 0
`
`8 0
`
`20
`
`1 80
`
`70
`50
`1 00
`1 30
`Technology Node (nm)
`
`35
`
`5000
`
`4 0 0 0
`
`3 0 0 0
`
`2000
`
`1 000
`
`0
`
`><
`
`E
`
`Figure 1 — Graphical representation of the "needle in the haystack" regarding
`the detection of small defects on complex semiconductor devices.
`
`*KWT (Correspondence): Email: tobinkwjr@oml.gov; WWW: http://www-ismv.ic.ornl.gov; Telephone: (865) 574-8521; Fax: (865)
`5746-8380.
`
`Metrology-based Control for Micro-Manufacturing, Kenneth W. Tobin, Jr., Fred Lakhani, Editors,
`Proceedings of SPIE Vol. 4275 (2001) © 2001 SPIE · 0277-786X/01/$15.00
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`
`particles that can cause eectrica1 faults in an integrated circuit, whereas the complexity factor is the product of the number of
`transistors in a micro-processor by the number of process steps required to manufacture the device. These two parameters
`work against each other as manufacturers strive to meet future productivity goals in the industry. The challenge has been
`described as looking for a "needle in a haystack" [3J.
`
`Figure 2 demonstrates the current financial impact of the need to develop higher accuracy metrology capabilities and to
`reduce metrology information rapidly for the purpose of making accurate assessments and predictions of the causes of yield
`loss. Revenue spending for test and metrology (the bulk of which is wafer inspection) approached $1OB in 2000 and is
`projected to increase. This corresponds to an increase in defect inspection expenditures for equipment, software, and support
`from around 1% of revenues in the early 1990's to over 3% in 2000. The issues driving these trends are the direct result of
`decreasing line widths (and therefore increased sensitivity to smaller particles), increasing device complexities, and
`increasing wafer dimensions.
`
`To address
`these
`complex
`manufacturing issues, the Image
`Science and Machine Vision
`(ISMV) Group of the Oak Ridge
`National Laboratory (ORNL),
`and the Yield Management Tools
`(YMT) Program of International
`SEMATECH (ISMT) have been
`developing new technologies for
`analysis of
`the
`automating
`defects found in semiconductors.
`In this paper we will survey our
`work in this area over the past
`decade covering the topics of
`Automatic Defect Classification
`(ADC),
`Signature
`Spatial
`(SSA), Automated
`Analysis
`Image Retrieval (AIR), and the
`integration of these methods in
`the manufacturing environment,
`both as independent methods and
`in support of each other in the
`process of data reduction and
`yield learning.
`
`12.0%
`
`10.0%
`
`Cl)
`
`.E
`9-
`o
`(C-
`0)
`
`C)
`C.)
`
`Q
`
`8.0%
`
`6.0%
`
`4.0%
`
`2.0%
`
`$60,000
`
`$50,000
`
`$40,000
`
`$30,000
`
`$2O,000
`
`$10,000
`
`c.
`C
`C)
`>
`w
`
`Cl)
`.D
`.E
`
`0.0%
`1974 1978 1982 1986 1990 1994 1998 2002
`Figure 2 — Semiconductor industry expenditures of revenues for various
`components of manufacturing. Note the increase in spending on test and
`metrology and in particular, defect inspection.
`
`$0
`
`2. YIELD MANAGEMENT
`Semiconductor device yield can be defined as the ratio of functioning chips shipped versus the total number of chips
`manufactured. Yield management can be defined as the management and analysis of data and information from
`semiconductor process and inspection equipment for the purpose of rapid yield learning coupled with the identification and
`isolation of the sources of yield loss. The worldwide semiconductor market experienced chip sales of $144 billion in I 999
`increasing to $234 billion in 2002 [4]. Small improvements in semiconductor device yield of tenths of a percent can save the
`industry hundreds of millions of dollars annually in lost products, product re-work, energy consumption, and by the reduction
`of waste streams.
`
`It is in the area of yield management that ORNL and ISMT have been developing technologies that are impacting the
`manufacturers ability to rapidly isolate yield loss mechanisms and learn about yield issues for predictive and management
`purposes. Figure 3 depicts a simplified fabrication flow diagram. This diagram of production (including front-end and back-
`end processing), data management, and yield analysis, in Fig. 3a-d respectively, encapsulates the major components of the
`manufacturing environment where process and product data are generated, maintained, and accessed for yield management.
`
`For our discussion we will focus on data that is generated from the wafer product itself, i.e., as opposed to process
`information such as tool condition data, temperature, pressure, etc. Figure 3a and 3b shows the process area in the fab where
`bare wafers enter the process, are printed and tested in-line, producing integrated circuits ready for packaging and sale.
`Metrology and defect data that are generated from the wafer are maintained in a variety of databases within the data
`
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`management system (DMS). Wafer defect, parametric, and electrical measurement data are typically maintained in a small
`group of databases (DBs) that are accessed as a virtual repository to facilitate data correlation between what is sensed on the
`wafer in terms of defectivity (e.g., optical or laser scanned images), parametric data (e.g., line widths and film thickness),
`electrical function (e.g., binmap and bitmap), and device yield. This data is accessed and analyzed by the failure analysis
`laboratory during off-line review and by the yield management team - i.e., engineers whose job is to improve current and
`future yield through yield learning and process improvement. During failure analysis, the wafer can undergo additional
`physical testing off-line to gain a better understanding of pattern, particle, or parametric fault mechanisms by high-resolution
`optical imaging, scanning electron microscopy (SEM), focused ion beam (FIB) cross-section analysis, atomic force
`microscopy (AFM), etc. (Fig. 3d). This image-based information augments the product-based DB therefore providing a
`historical record for current and future learning and yield prediction. It is the accumulation and manipulation of this in-line
`and off-line image data that is the basis for our work in yield management automation and the subject of the remainder of this
`paper. Further discussion of the semiconductor fabrication DMS architecture, function, and future needs can be found in
`references [5, 6].
`
`Figure 3 — Stylized representation of the three major components of the semiconductor fabrication
`environment: (a) and (b) front-end and back-end processing, (c) data management, and (d) yield
`analysis.
`
`3. WAFER DATA ANALYSIS AUTOMATION
`It has been estimated that up to 80% of yield loss in the mature production of high volume integrated circuits can be
`attributed to visually detectable random, process-induced defects (PIDs) such as particulates in process equipment [7, 8].
`Yield learning can therefore be closely associated with the process of defect detection and reduction. In this section we will
`review our work in the automatic analysis of defect
`image data from in-line inspection and off-line
`review spanning the topics of ADC for individual
`defect classification, SSA for the classification of
`populations of defects, and AIR for the management
`of very large image repositories. Fig. 4 gives an
`example of the level of information reduction that is
`to be achieved in yield management through
`automation. This flow diagram is based on ITRS
`specifications for inspection equipment at the
`current technology node (i.e., 180 nm features) and
`
`pixeisIhr
`Figure 4 — Typical information reduction target based on
`ITRS specifications for yield learning.
`
`1:r1
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`200 mm diameter wafers at 1 50 wafers per hour per tool. In essence, the need is to reduce on the order of 1 O!5 data samples
`per hour to around one dozen potential process sources. ADC, SSA, and AIR provide automation capabilities that support
`this goal.
`
`1. Automatic Defect Classification
`ADC was initially developed in the early '90s to automate the manual classification of defects during off-line optical
`microscopy review [9, 10, 11]. Since this time, ADC technologies have been extended to include optical in-line defect
`analysis and SEM off-line review [12]. For in-line ADC, a defect may be classified "on-the-fly", i.e., during the initial wafer
`scan of the inspection tool, or during a re-visit of the defect after the initial wafer scan, usually at higher resolution. During
`in-line detection the defect is segmented from the image using a die-to-die comparison or a method as shown in Fig. 5 [13,
`8]. This figure shows an approach to defect detection based on a serpentine scan of the wafer using a die-to-die comparison;
`first showing A compared to B, B compared to C, etc., ultimately building a map of the entire wafer as shown in Fig. Sc.
`This electronic wafermap forms the primary data record that is maintained in the DMS and provides defect information for
`off-line review and spatial analysis. During off-line review the defect is re-detected using the specified electronic wafermap
`coordinates and die-to-die methods. The classification decision derived from the ADC process is maintained in the electronic
`wafermap for the wafer under test and will be used to assist in the rapid sourcing of yield impacting events and for predicting
`device yield through correlation with binmap and bitmap data if available.
`
`r1P
`
`(a)
`
`(b)
`
`Figure 5 — Schematic representation of the typical serpentine defect scanning process in (a) resulting in
`the detection of defects (b), and ultimately in the generation of the wafermap in (c), an electronic record of
`wafer defectivity that is maintained in the DMS.
`
`In semiconductor applications, the methods used for classifying defects vary greatly, although they are primarily feature-
`based. There are two broad categories of classifier in use: rule-based classifiers with a fixed number of pre-defined classes
`(pre-defined by the system developer), and trainable classifiers that are trained in the field by the end-user. Fixed-class
`systems have come into popularity for in-line applications since the resolution of these systems is generally less than off-line
`review microscopes. The reduced sensitivity of the in-line systems results in simple classification schemes that classify
`defects, for example, by size or brightness. There is no user training of a fixed-class system. The result is ease-of-use. The
`down side of this approach is that the system cannot easily be trained to accommodate new defect classes that are
`manufacturer-specific. A trainable system (e.g., based on distance-based classifiers such k-nearest neighbor or neural
`networks) can accommodate the wide range of defect types associated with different inspection points in the process, various
`process layers, or products, but can be cumbersome to train and maintain. The concept of having a classifier system that is
`ready to use has prompted the extension of the fixed-classifier concept to some off-line review systems but the lack of
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`classification flexibility is considered to be an undesirable limitation by yield engineers. Ultimately there will likely be a
`ftision of these two approaches that allows the yield engineer to use the system immediately to classify basic categories of
`defects, while fine-tuning these categories through a training process over time [14].
`
`2. Spatial Signature Analysis
`A spatial signature is defined as a unique distribution of wafer defects originating from a single manufacturing problem [1 5].
`The analysis of spatial patterns of defects across whole wafers can be described as a means to facilitate yield prediction in the
`presence of systematic effects. We have developed an automated whole-wafer analysis technique called SSA to address the
`need to intelligently group, or cluster, wafermap defects together into spatial signatures that can be uniquely assigned to
`specific manufacturing processes and tools [16, 17, 18]. This method results in the rapid resolution of systematic problems
`by assigning a label to a unique distribution; i.e., signature, of defects that encapsulate historical experience with processes
`and equipment. Standard practice in the industry has been to apply proximity clustering to defects that results in a single
`event being represented as many unrelated clusters. SSA performs data reduction by clustering defects together into
`extended spatial groups and assigning a classification label to the group that reflects a possible manufacturing source. Figure
`6 shows examples of clustered and distributed defect distributions that are isolated by the SSA technique for both randomly
`occurring defect patterns and systematic patterns. SSA technology has also been extended to analyze electrical test binmap
`data (i.e., functional test and sort) to recognize process-dependent patterns that result from visible and non-visible (e.g.,
`
`parametric) problems on the wafer [19].0(a)
`
`(c)
`(b)
`Figure 6 — Examples of spatial signatures isolated by the ORNL SSA technology. In (a) a random population of
`defects, in (b) a systematic (non-random), non-clustered distribution, in (c) a complex scratch, and in (d) a spin
`coater streak pattern. SSA classifies each of these distinct patterns even when they overlap on a single
`wafermap.
`
`(d)
`
`SSA is a feature-based system built upon a fuzzy k-Nearest Neighbor (k-NN) classifier [20]. In the manufacturing
`environment, electronic wafermap data is collected from in-line inspection tools and defect signatures are segmented for
`analysis. For semiconductor inspection, a signature object is defined as a unique pattern of individual optical defects or
`electrical bin codes that were generated by an errant process. Approximately 30 features are extracted from the segmented
`object and are sent to the classifier where a class label is assigned to the result based on user training. The user-defined class
`result then indicates the specific tool or process that must be corrected [21], e.g., the "spin coater streak" in Fig. 6d.
`
`For industrial pattern recognition problems non-parametric classifiers such as the classical k-NN [22] apply well since
`information about the shape of the distribution of features in the multi-dimensional space of the classifier is not required. It is
`difficult to ascertain a statistical parameterization for the large variety of class types encountered. Also, in an industrial
`setting it is often required that the classifier system begins to classify new data with few training examples while providing
`reasonable accuracy. Bayesian classifiers [23] and neural networks [24] generally require large sample populations to
`estimate the appropriate statistics and are therefore difficult to implement in general for industrial applications. This is
`primarily due to the diverse nature of the patterns that arise for different manufacturing processes and facilities, coupled with
`the length of time required collecting large sample populations. Also, over the period of time required to collect large sample
`sets, acceptable process variations can occur that confuse the boundaries between classes. The fuzzy k-NN classifier training
`set can readily be maintained over time (e.g., by including and excluding examples based on time and date), can be modified
`often, and can operate with relatively few examples for each class.
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`3. Automated Image Retrieval
`The ability to manage large image databases has been a topic of growing research in many fields. Imagery is being generated
`and maintained for a large variety of applications including remote sensing, architectural and engineering design, geographic
`information systems, and weather forecasting. Content-based image retrieval (CBIR) is a technology that is being developed
`to address these needs [25]. CBIR refers to techniques used to index and retrieve images from databases based on their
`pictorial content. Pictorial content is typically defined by a set of features extracted from an image that describe the color,
`texture and/or shape of the entire image or of specific image regions. This feature description is used in CBIR to index a
`database through various means such as distance-based techniques, approximate nearest-neighbor searching, rule-based
`decision-making, and fuzzy inferencing [25, 26].
`
`CBIR addresses a problem created by the growing proliferation of automated defect review and ADC technologies; i.e., the
`management and reuse of the large amounts of image data collected during review. For semiconductor yield management
`applications we have denoted CBIR technology as AIR [27, 28]. Digital imagery for failure analysis is generated between
`process steps from optical microscopy and laser scattering systems and from optical, confocal, SEM, AFM, and FIB imaging
`modalities. This data is maintained in a DMS and used by fabrication engineers to diagnose and isolate manufacturing
`problems. The semiconductor industry currently has no direct means of searching the DMS using image-based queries, even
`though many thousands of images are collected on a weekly basis [29]. Current abilities to query the fabrication process are
`based primarily on product ID, lot number, wafer ID, time/date, process layer, engineer classification, or ADC class, etc.
`Although this approach can be useful, it limits the user's ability to quickly locate historical examples of visually similar
`imagery, especially for data that was placed in the database over one or two weeks prior. Data much older than this is nearly
`irretrievable since retrieval is dependent on human memory and experience. Without the addition of datamining capabilities
`such as AIR, this large image repository will remain virtually untapped as a resource for rapidly resolving manufacturing
`problems.
`
`For AIR to be practical and useful in the yield management
`environment, the image data must be associated with the
`process conditions that caused the defect image to be
`generated by the review tool. The AIR system maintains
`this information in a relational database as shown in Fig. 7.
`The relational database manages standard wafermap
`information that is typically found in the wafermap file
`generated by the inspection tool such as defect data (e.g., X
`and Y coordinates, defect size, cluster number, etc.), wafer
`data ( e.g., Lot ID, wafer ID, Die pitch, etc.), and class data
`(e.g., engineer or ADC class labels for SEM inspection,
`optical inspection, cluster class, etc.). The primary starting
`point for AIR-based searches is the image feature data that
`is maintained in the image feature tables. These tables
`contain feature descriptions of the images (i.e., color,
`texture, shape, etc.) for the defect and substrate regions and
`file paths and names for the image directory that is
`maintained on the fab DMS side of the system. Once a
`query has been completed, the ranked list of similar
`imagery that is returned can be further analyzed to
`determine any number of statistical distributions, e.g., tool
`commonality, die location, wafer location, engineering
`classification, etc.
`
`Figure 7 — The fab DMS in (a) provides image and process
`data to the AIR system in (b) where it is maintained in a
`relational database.
`
`An example screen shot of the user-interface for the ORNL AIR system is shown in Fig. 8. This retriever interface represents
`the basic GUI for retrieving images based on several different criteria including image content. Images can be imported as
`query images using a cut-and-paste operation or file open browser dialog boxes. Once an image is imported into the system,
`a mask is generated for the defect that provides a localization of the defect region. Queries are performed by simply selecting
`the image areas of interest (e.g., defect texture, defect color, background color, etc), and optionally a set of layers or lots,
`which limits the query to images with these characteristics. Returned images are displayed in ranked order in a gallery.
`Clicking each returned image shows its lot, layer, file name, classifications, etc. The returned gallery can be exported to an
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`HTML file. In addition, Paretos are presented for the returned results that correlate the image list with processes. These
`Paretos can be exported to comma-separated value files for use with other analysis tools.
`
`4. INTEGRATED ANALYSIS
`Integrated analysis of DMS data goes beyond database infrastructure and merging issues and will encompass new methods
`that attribute informational content to data, e.g., the assignment of defect class labels through ADC, or unique signature
`labels in the population of defects distributed across the wafer using SSA. These methods put the defect occurrence into a
`context that can later be associated with a particular process, material characteristic, or even a corrective action. For
`example, a defect coordinate in a wafermap file contains very little information, but a tungsten particle within a deposition
`signature is placed in the context of a specific manufacturing process and contamination source. Later reporting of this
`information can lead to rapid yield learning, process isolation, and correction.
`
`Figure 9 shows the image-based technologies that have been surveyed in this paper and where they apply in the
`manufacturing environment that was described through Fig. 3. To begin the discussion of integrated analysis, we will focus
`on merging SSA and ADC technologies as in Fig. 9a. These technologies are being combined to facilitate intelligent
`wafermap defect sub-sampling for efficient off-line review and improved ADC classifier performance [30, 3 1 ,32]. The
`integration of SSA with ADC technology can result in an approach that improves yield through manufacturing process
`characterization. It is anticipated that SSA can improve the throughput of an ADC system by reducing the number of defects
`that must be automatically classified. For example, the large number of defects that comprise a mechanical scratch signature
`that is completely characterized by SSA will not
`need to be further analyzed by an ADC system.
`Even if a detected signature cannot be completely
`characterized, intelligent signature-level defect
`sampling techniques can dramatically reduce the
`number of defects that need to be sent to an ADC
`system for subsequent manual or automated
`analysis (e.g., defect sourcing, tool isolation,
`etc.).
`
`The accuracy of an ADC system can potentially
`be improved by using the output of the SSA
`wafermap analysis to perform focused ADC.
`Focused ADC is a strategy by which the SSA
`results are used to reduce the number of possible
`classes that a subsequent ADC system would
`have to consider for a given signature. SSA
`signature classification can be used to eliminate
`many categories of potential defects if the
`category of signature can be shown a-priori to
`consist of a limited number of defect types. This
`pre-filtering of classes reduces the possible
`alternatives for the ADC system and, hence,
`improves the chance that the ADC system will
`select the correct classification. It is anticipated
`that this will result in improved overall ADC
`performance and throughput.
`
`Figure 8 — Screen shot of the user interface for the ORNL AIR
`system showing the query (upper left) and returned list of similar
`images (lower right) and associated process statistics (lower right).
`
`Integrating AIR with ADC will enable easier compilation of example libraries for ADC training purposes. A common
`frustration with ADC systems is the work required to train them. Using AIR should enable easier retrieval of relevant
`imagery to assemble appropriate sets for defining ADC classes. In addition, AIR technology can help determine if an ADC
`system is operating within its original defined class range. For example, subclasses can arise in a particular defect type that
`ADC cannot discern due to its static training. Applying AIR to these defect images can help the operator determine if new
`subclasses of defect images are appearing, and if these subclasses are significant enough to warrant new training of the ADC.
`An automatic set of AIR queries could serve to validate ADC performance and monitor trends; for example, an AIR query
`that retrieved 100 images could show that 75 of them had the same ADC label. A later query that showed only 50 of them
`had the same label could indicate changes in the process line.
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`Finally, the integration of SSA signatures and AIR (i.e., as in Fig. 9c) becomes a beneficial extension of the retrieval
`technology when we consider that the spatial signature is a collection of features. These features are directly applicable in the
`AIR environment as a descriptive search and retrieval mechanism analogous to the features used to describe individual
`defects. The storage of signature images (e.g., as simple binary bitmaps) will facilitate the viewing of retrieval data, but as
`with individual defect images, the greatest benefit is derived from the collection and analysis of associated process
`information. These process statistics help the yield engineer to isolate and source problems to tools and equipment.
`
`...-
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`maintenance,
`training
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`AIR
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`SSA I ADC
`integration
`(a)
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`DataManagementSystem
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`I FrontEnd
`II BackEnd I
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`(c) Signature
`retrieval and
`management
`Figure 9 — The integration of these technologies in the yield management environment are
`resulting in the rapid isolation and correction of problems in complex semiconductor
`fabrication processes.
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`5. CONCLUSION
`Integrated yield management strategies will have to accommodate the ever-increasing volume of manufacturing data that is
`being sampled from the manufacturing process as the complexity trend continues to increase. This increasing volume of data
`is necessitating the development of automation tools that can ultimately relieve the analysis burden placed on the yield
`engineer thus making him/her more efficient in the sourcing and correction of yield impacting events and trends. While
`network bandwidth, database storage capacity, database retrieval rates, information transfer protocols, and other data
`standards must continue to evolve to meet these needs, automation technologies that take raw manufacturing data and convert
`it to useful information will provide the greatest advantage. In this paper we have surveyed several technologies that have
`been developed by ORNL and ISMT that take human expertise and encapsulate it such that it can be applied to the decision-
`making process in an automated fashion. ADC and SSA take wafermap defect data and place it in the context of specific
`manufacturing events that impact yield. Integrating these technologies can lead to in-line yield prediction that can assist in
`the rapid prioritization of these events. AIR technology has the potential to provide an efficient query window into the
`historical record of the manufacturing environment, allowing search and retrieval capabilities currently unavailable to the
`semiconductor manufacturer. The integration of AIR with SSA and