Microprocessor
`Data
`Book
`
`SECOND EDITION
`
`S. A. Money
`
`®
`
`ACADEMIC PRESS, INC.
`Harcourt Brace Jovanovich, Publishers
`San Diego New York Boston
`London Sydney Tokyo Toronto
`
`Anker, EX1015, p. 1
`
`

`

`This book is printed on acid-free paper. @
`
`Copyright © 1990, 1982 by S. A. Money
`All Rights Reserved.
`No part of this publication may be reproduced or transmitted in any form or
`by any means, electronic or mechanical, including photocopy, recording, or
`any information storage and retrieval system, without permission in writing
`from the publisher.
`
`Academic Press, Inc.
`San Diego, California 92101
`
`United Kingdom Edition published by
`Blackwell Scientific Publications Limited
`Osney Mead, Oxford OX2 OEL, England
`
`Library of Congress Cataloging-in-Publication Data
`
`Money, Steve A.
`Microprocessor data book /S.A. Money. ~ 2nd ed
`p. cm.
`Includes bibliographical references.
`ISBN 0-12-504445-3
`(alk. paper)
`1. Microprocessors. 2. Microcomputers.
`QA76.5.M549 1990
`004.16-dc20
`
`I. Title.
`
`Printed in the United States of America
`90 91 92 93
`9 8 7 6 5 4 3 2 1
`
`90-300
`CIP
`
`Anker, EX1015, p. 2
`
`

`

`PREFACE
`
`Advances in the techniques for manufacturing large
`scale integrated (LSI) circuits have, in recent years,
`made it feasible to incorporate most, or in some cases
`all, of the complex logic required for a small digital
`computer system on to a single silicon chip. One
`example of the application of these LSI techniques is in
`the familiar digital pocket calculator, which is in fact a
`specialised digital computer. In these devices all of the
`electronic logic is contained in a single integrated circuit
`package.
`In designing modern electronic systems the engineer
`must now take into account the ready availability of
`microcomputer and microprocessor devices which can
`simplify design, making the end product more versatile
`or more economical to produce.
`One problem which faces the designer planning to use
`a microprocessor is the great multiplicity of devices that
`have become available. Choosing a suitable micro­
`processor could involve collecting together and search­
`ing through a mountain of different data sheets and
`manuals.
`In this book condensed data have been provided for
`most of the available types of microprocessor and micro­
`computer device. For each major type or series a des­
`cription is given of the internal architecture, instruction
`set, main electrical data and package details.
`Most of the popular devices are manufactured by
`several different suppliers, and a list of alternative
`sources and type numbers have been included in the data
`for each type. Support chips designed for that processor
`have also been listed.
`For convenience the devices have been divided into
`groups covering 4, 8 and 16-bit types and other pro­
`cessors. It would not be practical to include full details of
`each type, but it is hoped that sufficient information has
`been provided to allow the designer to narrow down his
`choice to perhaps one or two types. The manufacturer's
`data sheets or manuals may then be consulted for more
`detailed operating and application information.
`In order to choose a processor for a project some
`knowledge of the basic principles of the devices is re­
`
`quired, and this has been covered in the introductory
`chapter. A general guide has also been included on the
`factors involved when a processor type is chosen.
`A complete system normally consists of a micropro­
`cessor together with a selection of supporting devices to
`handle input-output, external device control and to
`provide memory. The number of support devices avail­
`able is even greater than that of microprocessor types, so
`no attempt has been made to include details of all of
`these. Some descriptions have been included covering
`the major support device functions, and data have been
`included on some of the more popular types as a guide to
`the facilities provided by such devices.
`At the end of the book a directory of microprocessor
`manufacturers has been included and there is also a
`glossary of some of the terminology used in the micro­
`processor field.
`It is hoped that the information given in this book will
`assist designers in choosing suitable devices and that it
`will be generally useful to those engaged in designing or
`planning microprocessor based products.
`One problem encountered in producing any data
`book which deals with a rapidly advancing field, such as
`microprocessors, is that new devices are continually
`being introduced. To deal with this situation plans are
`being made for the publication, from time to time, of a
`supplement giving data on recently introduced devices.
`Readers wishing to have details of these supplements
`should complete and mail the coupon enclosed in this
`book, or alternatively write to the publishers, when they
`will automatically receive advance details of these sup­
`plements.
`The reader will notice that for a limited number of
`devices in this book only limited data are given. This is
`because at the time of compilation only preliminary
`information was available. The reader is referred to the
`supplement for full information.
`Finally, I would like to express my thanks to all those
`manufacturers and distributors who supplied the data
`and other information which made it possible to compile
`this book.
`
`VI
`
`Anker, EX1015, p. 3
`
`

`

`1 INTRODUCTION
`1
`INTRODUCTION
`
`Anker, EX1015, p. 4
`
`Anker, EX1015, p. 4
`
`

`

`In recent years the advent of microprocessors and micro­
`computers has revolutionised the whole process of digi­
`tal system design. Projects which, a few years ago,
`might have required tens or hundreds of digital logic
`devices can today be implemented by using perhaps one
`or two LSI circuits. Of course LSI circuits have been
`around for some years, but economic considerations
`have usually limited these to applications, such as digi­
`tal calculators where high volume production is possible
`and high design costs can be recovered quickly. The
`advantage of the microcomputer is that a standard
`device can be used for many applications merely by
`altering the program of instructions held in its memory.
`Thus design costs can be reduced and a variety of
`products may be built using perhaps a standard circuit
`board.
`Microcomputers, however, bring with them a number
`of new design concepts which may be unfamiliar to the
`system designer used to working with conventional digi­
`tal logic systems. In this introductory section we shall
`examine the internal organisation of microcomputer
`systems and their general principles of operation. Later
`we shall consider the various factors involved in choosing
`a suitable type of microprocessor for a design project.
`
`ARCHITECTURE
`
`The general organisation of a digital computer, whether
`it be a mainframe, a minicomputer or a microcomputer,
`follows the basic arrangement show in fig. 1.1.
`
`CPU
`
`CONTROL AND
`
`( P C)
`
`LOGIC
`TIMING
`PROGRAM
`COUNTER
`STACK
`INSTRUCTION
`DECODER
`> '
`
`A LU
`ACCUMULATOR
`
`WORKING
`REGISTERS
`
`—>■
`
`\
`
`1
`
`t
`
`i
`1
`t
`
`—*
`
`MEMORY
`
`PROGRAM
`(ROM OR RAM)
`
`DATA
`
`( R A M)
`
`<->
`
`INPUT AND
`
`OUTPUT
`
`PORTS
`
`1
`
`1
`
`>
`
`\
`
`i
`
`i
`
`Fig. 1.1
`
`At the heart of the system is the central processor
`unit, generally referred to as the CPU. Functionally the
`CPU can be broken down into two subsections, one of
`
`INTRODUCTION
`
`which is used to control the timing and sequence of
`operations in the system, whilst the other executes the
`required arithmetic and logic operations and handles
`the data being processed. A memory system is con­
`nected to the CPU and is used to store the list of
`instructions to be executed, known as the program, and
`the data being processed. In most systems a common
`memory is used to hold both the program instructions
`and the data but some types of processor use separate
`memory systems for the data and the instructions. Com­
`munication with the outside world is handled by a
`number of input and output ports, which allow data to
`be transferred to and from external devices such as
`keyboards, display units and printers. The various
`components of the microcomputer system are tied
`together by a system of bus lines which are common
`to all units. This is, of course, a very much simplified
`description of a microcomputer system and we shall
`now go on to look at each section in more detail.
`
`BUS SYSTEMS
`
`Data is transferred between the various units of the
`system over sets of parallel wires known as buses. In
`most systems there are three sets of bus wires, one
`carrying data, a second carrying memory address in­
`formation and the third carrying a selection of control
`signals.
`The data bus allows signals representing either data
`or program instructions to be transferred between the
`CPU and either the memory or the input-output ports.
`This bus is always bidirectional and its operation is
`controlled by the CPU. Read and write control lines
`from the CPU determine the direction of data flow
`through the data bus so that when a write operation is
`performed the signals always flow from the CPU out to
`memory or I -O ports. A read operation causes signals
`to flow into the CPU from the memory or I -O port.
`Many processors, such as the Motorola types, use a
`single read/write (R/W) control line to control the
`direction of signal flow on the data bus with one state of
`the control line indicating a read operation and the
`other indicating a write operation. Other types, such as
`the Intel and Zilog processors, have separate read and
`write control lines. Normally the data bus is set up for
`read operations as a default condition. There may be
`several memory or I -O devices which can access the
`data bus but only one may be allowed to actually drive
`the bus lines at a time so the bus drive circuits are either
`tri-state or wired OR type circuits.
`The address bus is used to provide an address signal
`which selects one particular location within the memory
`for connection to the data bus. The address bus lines are
`driven by output signals from the CPU. The address
`bus may also be used to select individual input or out­
`put channels where several are connected to the CPU
`system.
`Some processors use separate memories to hold the
`program instructions and the data. In such a system
`there may be one data and address bus system for the
`instruction memory and a separate data and address bus
`scheme for the data memory. Another variation uses a
`common address bus with separate data buses for the
`instructions and data.
`The control bus provides a selection of control signals
`
`3
`
`Anker, EX1015, p. 5
`
`

`

`MICROPROCESSOR DATA BOOK
`to and from the CPU which govern the timing and
`control of data transfers on the other bus lines. Among
`these may be signals for halting the operation of the
`CPU and perhaps disconnecting it from the bus system.
`This facility is important when it is desired to have
`another device take over control of the bus system.
`Typical applications might be in multiprocessor systems
`where a common bus is to be shared between two or
`more CPUs only one of which may control the bus at
`any time. The usual scheme is for the external device to
`send a bus request signal to the CPU when it wants to
`take over the bus system. On receipt of the bus request
`the CPU completes its current instruction then dis­
`connects itself from the bus and outputs a bus grant
`signal to indicate that the bus is free. When the bus
`request signal is removed the CPU again resumes con­
`trol of the bus system.
`In a large system the output drivers of the CPU chip
`and other devices may not be capable of driving all of
`the loads on the bus. In such cases bus drivers, or bus
`transceivers are used to drive the common bus system.
`
`CPU CONTROL UNIT
`
`Apart from the system timing and control logic the
`control section of the CPU contains a register called the
`program counter (PC), an address register, an instruction
`register, a stack or stack pointer register and some
`interrupt logic.
`The instructions which tell the CPU what to do
`consist simply of a sequence of numbers which are held
`in the memory. Each instruction usually consists of an
`opcode which defines the type of operation to be carried
`out and one or more operands which define the data to
`be used and what is to be done with any results.
`The program counter register holds the memory
`address where the opcode for the next instruction is
`held. When a program is initiated the program counter
`is loaded with the address for the first program instruc­
`tion. As each instruction is executed the program coun­
`ter is automatically updated to point to the address of
`the next instruction to be executed. Usually instructions
`are executed in sequence but occasionally the program
`sequence may jump to some new point in memory
`specified by the instruction that has just been executed.
`The first stage in executing an instruction is the fetch
`cycle when the opcode for the instruction is read in
`from the memory and placed in the instruction register.
`During the next phase of execution the opcode is de­
`coded and the control logic within the CPU is set up to
`perform the desired operation. During the decoding
`phase the CPU will determine whether it needs to read
`in any operand data from the memory. If data is required
`the next phase will be to read in the operand from
`memory. The final phase is the actual execution of the
`instruction.
`The timing of the execution sequence varies according
`to the type of processor involved. In a processor such as
`the 6800 a simple two phase clock program is used and
`all data transfers to and from the memory are made
`during the second half of each clock cycle when the
`phase 2 clock signal is high. A simple instruction such as
`Clear Accumulator A (CLRA) consists of an opcode
`only and executes in two clock cycles. The first cycle is
`used to read the opcode from memory. During the first
`
`4
`
`half of the next clock cycle the decoding is carried out
`and then the instruction is executed during the second
`half of that clock cycle. If the accumulator is to be
`loaded with immediate data, stored in the memory
`location following the opcode, the instruction takes up
`three cycles. The opcode is fetched on the first cycle
`then the address register is incremented and the data
`is read in from memory during the second cycle. If
`the data is to be loaded from an absolute address the
`number of cycles required goes up to four. Again the
`opcode is fetched during the first cycle and the next two
`cycles are used to read in the 16 bit address operand
`from the two memory locations following the opcode.
`This address operand is then transferred to the address
`register and during the fourth cycle the data is read in
`from the appropriate address in memory. In other types
`of processor such as the Z80 and 8086 each instruction
`cycle consists of three or four clock cycles. The clock in
`such processors usually runs at about four times the
`speed of the simple 6800 type clock so that actual in­
`struction execution times are similar for both types of
`processor.
`One problem with simple processors is that each
`instruction must complete its execution sequence before
`the next instruction is started. To speed up instruction
`execution most of the modern 16- and 32-bit processors
`use a pipeline system for instructions and data. In
`such a system several instructions may be in progress at
`the same time. Whilst one instruction is being executed
`the opcode for the next instruction can be decoded
`and the opcode for the following instruction can be
`fetched from memory and placed in the pipeline queue.
`With this overlapped processing of instructions the
`throughput of the processor can be increased by a factor
`of two or three over that of a system where each in­
`struction is processed completely before the next starts.
`One problem with fast 16- and 32-bit processors is
`that the speed of access to the main memory system is
`often much slower than the rate at which the CPU can
`process instructions. To overcome this situation many
`systems use a high speed cache memory, built from fast
`static RAM devices, to hold a block of recently executed
`instructions. In many program applications the process
`operates in relatively short loops where a sequence of
`instructions is repeated a number of times. If this se­
`quence is held in high speed cache memory then the
`program execution will not be slowed by repeated ac­
`cesses to the slow main memory. When the next re­
`quested instruction is not in the cache memory a cache
`miss occurs and the main memory is again accessed.
`Some systems use a similar cache system for data where
`recently accessed data is held in a cache memory and
`here again execution can be speeded up where say a
`table of data values is being processed.
`
`CPU EXECUTION UNIT
`
`The central part of the execution unit of a microprocessor
`is the arithmetic and logic unit or ALU which performs
`all of the arithmetic and logic functions specified for the
`execution of an instruction. In most processors the
`ALU works in conjunction with a special register called
`the accumulator.
`The ALU has two data inputs and one data output
`and these may be either 4, 8,16 or 32 bits wide according
`
`Anker, EX1015, p. 6
`
`

`

`to the type of processor. The accumulator register has
`the same number of bits as the ALU. Under normal
`conditions the accumulator provides one input to the
`ALU whilst the other input is fed either from another
`CPU register or from the external data bus. Output
`data from the ALU is written back into the accumulator.
`In some processor types the external data bus has
`fewer bits than the ALU. For example an 8088 has a 16-
`bit ALU but only an 8-bit data bus whilst the 68000 has
`a 32-bit ALU with a 16-bit data bus. In such cases if
`data is taken from memory to the ALU it is read in as
`two bytes or words and then assembled in an internal
`register before being applied to the ALU input. Pro­
`cessors such as the 6809 have two separate 8-bit accu­
`mulators which may be used independently or linked
`together to handle 16-bit numbers.
`Apart from the ALU the execution unit will contain a
`status register which gives information about the result
`produced by an instruction. This normally contains a
`series of flag bits which indicate if the result was zero,
`minus or has produced a carry or an overflow condition.
`These flags can be used to determine the future flow of
`program execution according to the state of one or
`more of the flag bits.
`All processors contain some registers which can be
`used for storing data and temporary results. An import­
`ant advantage of holding data within on chip registers is
`that access to register data is always much faster than
`access to data in the main memory so that program
`execution can be speeded up by using the internal
`registers. Most of the newer 16- and 32-bit processors
`such as the 68000 series have a bank of general purpose
`registers each of which may be used in the same way as
`a dedicated accumulator register.
`Most processors also contain data pointer registers
`which can be used to hold memory address information.
`In this case the pointer register is specified as an operand
`instead of using an actual memory address. The register
`can usually be specified in the instruction opcode so that
`there is no need to read in an operand from memory
`and thus execution is speeded up. This is particularly
`useful where a table of data is being accessed and items
`in the table are stored in successive memory addresses.
`To move through the table the pointer register is in­
`cremented after each instruction to point to the next
`memory address. In such a scheme the pointer register
`is usually referred to as the index register and in many
`types of processor the incrementing or decrementing of
`this register can be included as part of the action of the
`instruction.
`Typical arithmetic and logic functions provided by
`the ALU and its associated accumulator are ADD,
`SUBTRACT, AND, OR and EXCLUSIVE OR. In
`addition it is usually possible to set the data to zero or to
`set all the bits to the 1 state. Data held in registers can
`also be incremented or decremented. It is also possible
`to shift the data pattern left or right in a register or to
`rotate the data pattern so that bits spilling from one
`end of the register are re-inserted at the other end to
`produce a loop of data bits. In the 6800 series processors
`memory locations can be used as registers and data in
`them can be incremented, decremented, shifted and
`rotated directly.
`All of the 16- and 32-bit processors and some 8-bit
`types provide simple multiply and divide instructions
`which can handle either signed or unsigned data. These
`functions generally use an internally stored sequence of
`
`INTRODUCTION
`operations and may take up many instruction cycles. A
`few more sophisticated types such as the Am29000 use
`parallel logic arrays within the ALU to perform hard­
`ware multiplication or division and give high execution
`speed.
`Most processors provide only integer arithmetic which
`may use either pure binary or BCD number systems.
`For many applications floating point arithmetic may be
`required in order to deal with large numbers and frac­
`tional quantities. For the standard processors this is
`usually accomplished by using software routines which
`tend to be relatively slow in execution. An alternative
`approach is to add a dedicated floating point coprocessor
`which is designed specifically to carry out floating point
`operations. The main CPU now passes data and instruc­
`tions to the coprocessor and then reads back the results
`and this provides a much higher execution rate for
`programs requiring floating point calculations. A few of
`the more advanced processors such as the 80486 and
`some of the RISC type processors have the floating
`point execution unit built into the main processor
`chip.
`A very important facility in all microprocessors is the
`ability to test the results produced by executing an in­
`struction and then to take alternative courses of action
`according to the results obtained. The tests usually set
`or reset individual bits in a special register called the
`status register which may also be referred to as the
`condition code register. There are four flag bits Z, M, C
`and V which are common to all processors. The Z bit
`indicates that the result was zero and the M bit indicates
`a minus sign or a negative result. The C bit shows that a
`carry has been generated by an arithmetic or logic
`operation. The fourth status bit, usually labelled V,
`indicates an overflow condition where the result is
`outside the range of numbers that can be correctly
`represented in the accumulator register. Sometimes a
`half carry bit is provided which is used when handling
`numbers in the BCD format. Other bits in the status
`register may be used to indicate whether interrupts
`are enabled or disabled and to indicate whether the
`processor is operating in system or user mode.
`The simplest form of conditional instruction is a skip
`operation. The SKIP instruction examines the status
`bits and compares them with a specified set of conditions.
`Thus SKIPZ would check the state of the zero (Z) bit. If
`the Z bit is set, indicating that the result of the last
`operation was zero, the program execution jumps over
`the next instruction after SKIPZ. If the result was not
`zero then the instruction after SKIPZ is executed. This
`allows the possibility of two alternative courses of action
`depending on whether the result of the test was true or
`false.
`In most processors a conditional instruction called a
`branch is used in conjunction with the status register
`bits to control the flow of the program execution. The
`branch instruction tests for a particular state of one or
`more of the status bits. When the state is true the
`program execution branches to a new point specified by
`the operand of the branch instruction. If the specified
`condition is not met the program continues with execu­
`tion of the next instruction in the normal way. Usually
`the operand of the Branch instruction is added to the
`value in the program counter to calculate the new
`address from which the program will continue to ex­
`ecute. Some processors have conditional jump instruc­
`tions which perform in much the same way as a branch
`
`5
`
`Anker, EX1015, p. 7
`
`

`

`MICROPROCESSOR DATA BOOK
`
`except that the operand specifies the actual address to
`which the program execution must jump.
`
`SUBROUTINES AND STACKS
`
`In any program there are some sequences of instruc­
`tions which are frequently repeated as the program
`executes. Typical examples might be the routine to read
`a character in from a keyboard or some arithmetic
`routines such as number conversions or iterative cal­
`culations. Whilst these instruction sequences could
`simply be repeated at appropriate points in the program
`a more convenient technique is to make use of a sub­
`routine. In this technique the sequence of instructions
`is stored at a separate point in memory from the main
`program. The subroutine sequence is often placed im­
`mediately after the end of the main program code. To
`execute the subroutine sequence a special instruction
`such as CALL or JSR (jump to subroutine) is inserted
`in the main program sequence at the point where the
`subroutine is to be executed. This instruction simply
`tells the CPU that instead of executing the next instruc­
`tion in the main program it should jump to the first
`instruction of the subroutine sequence. Before making
`this jump however the contents of the program counter
`are saved by the CPU. The short set of subroutine
`instructions is then executed. At the end of the sub­
`routine sequence another special instruction called
`RET (return) or RTS (return from subroutine) is ex­
`ecuted. This instruction restores the saved contents of
`the program counter so that the next instruction in the
`main program sequence will be the one to be executed
`next.
`In simple processors a single save register within the
`CPU is used to hold the old program counter value
`whilst the subroutine executes. If a call were made to
`another subroutine from inside the first subroutine a
`new value would be written into the save register. At
`the end of the second subroutine the program would
`return correctly to the first subroutine but the original
`PC value in the main program would have been lost and
`the program would crash because at the end of the first
`subroutine it would not know where to go next. To
`overcome this some processors use two or three registers
`which form a last in first out or LIFO memory which is
`more generally called a stack. This arrangement works
`in a similar fashion to building a pile of cards. The first
`PC value is stored in the lowest register in the stack
`which acts as if it were a single card on a table. When
`another subroutine is called the PC is placed into the
`next higher register which is like placing a new card on
`top of the first. As each new subroutine is started a new
`higher position register is used and a new card is added
`to the pile. As a subroutine ends it reads the PC value
`from the top register in the stack and the next register
`down becomes the new top of the stack. This is equiv­
`alent to removing a card from the pile.
`In most processor systems the stack is created in the
`memory rather than using dedicated save registers. This
`is achieved by using a stack pointer register which holds
`the address of the top of the stack which is usually the
`empty location to which the next data value will be
`saved. In most systems the stack is arranged to build
`downwards in memory. Thus after a data word has been
`
`6
`
`written to the stack the stack pointer contents are
`decrementesd to point to the next free location in the
`memory. When a word is taken off the stack the pointer
`is incremented to pick up the last word written to the
`stack then the word is read out and its location becomes
`the new top of the stack.
`
`INTERRUPTS
`
`When communicating with the outside world there will
`be occasions where the processor is ready to transfer
`data but the external device is not or vice versa. One
`solution to this problem is to place the processor in a
`program loop where it repeatedly checks the state of the
`external device to see if it is ready to send or receive
`data. As an example if the processor is outputting data
`to a printer it has to wait for the printer to complete its
`printing operation before a new data character can be
`output. A typical printer might operate at perhaps 100
`characters per second but during the 0.01 second period
`for printing a character the processor could have ex­
`ecuted some 5000 or more instructions. In the case of
`keyboard input the program would have to be written
`so that it checked the keyboard at regular intervals to
`see if a key had been pressed. These approaches which
`use a regular testing loop are usually referred to as
`polling routines. In a real time controller application
`the processor will need to respond immediately to a
`number of inputs and if the polling techniques is used
`most of the available processing time could be spent in
`checking the status of external devices.
`An alternative and much more efficient method off
`dealing with external devices is to make use of an
`interrupt system. In an interrupt scheme when the
`external device is ready to transfer data it sends a signal
`to a special interrupt request (IRQ) input on the pro­
`cessor chip. When the IRQ input occurs the processor
`completes its currently executing instruction and then
`branches to an interrupt service routine which deals
`with the data transfer to or from the external device. In
`some ways this is like having a subroutine call which
`is initiated by an external hardware signal. Before
`branching off to the interrupt service routine the CPU
`will automatically save the program counter and the
`status register. Some processors such as the 6800 save
`all of the internal CPU registers to the stack when an
`interrupt occurs. At the end of interrupt service routine
`there is a return from interrupt (RTI) instruction which
`causes the saved CPU register contents to be restored
`so that the program resumes execution from the point
`where it was interrupted. In most of the 16- and 32-bit
`processors interrupts are referred to as exceptions but
`the action is the same.
`The simple form of interrupt is usually referred to
`as a non-maskable interrupt (NMI) and the interrupt
`service routine is automatically invoked whenever an
`input is applied to the NMI input line. The alternative
`type of interrupt scheme is the masked interrupt which
`is usually triggered by an input to an interrupt request
`(IRQ) input. When this type of interrupt occurs it sets a
`mask bit in the status register which causes the IRQ
`input to be disabled so that any further input signals are
`ignored whilst the interrupt is being serviced. At the
`end of the interrupt routine the mask bit is reset and the
`
`Anker, EX1015, p. 8
`
`

`

`IRQ input becomes active again. The mask bit can also
`be controlled by the program so that the interrupt input
`can be enabled or disabled as desired.
`Another type of interrupt is the software interrupt
`(SWI) or TRAP operation in which an instruction in
`the program invokes a branch to an interrupt service
`routine. Sometimes TRAP operations may be invoked
`by an error condition such as a divide by zero error. The
`main difference between a subroutine and a trap is that
`the subroutine call specifies the address to which the
`program must jump whereas the trap does not.
`Most processors use a vectored interrupt or exception
`scheme. When the interrupt or exception occurs the
`address for the start of the interrupt routine is read from
`a vector table in memory. The position of this address in
`the table is determined by the type of interrupt that has
`occurred. As an example in a 6800 processor the vector
`table is located at the top of the memory map in
`locations $FFF8-$FFFF. When an NMI input occurs
`the branch address for the interrupt service routine is
`take from locations $FFFC and $FFFD. If an IRQ input
`triggered the interrupt the address comes from locations
`$FFF8 and $FFF9 whilst an SWI software
`interrupt
`causes a branch to the address held in locations $FFFA
`and $FFFB. In the more complex processors such as the
`68000 or 8086 there may be a table of perhaps 256
`vector addresses each of which may be assigned to a
`particular type of interrupt or exc