`
`Proceedings of ICSP '98
`
`Multi-Standard DSP based wireless system
`
`Chaucer Kuo, John Wong
`
`Abstract
`
`band pass sampling DSP based multi-standard
`receiver.
`
`Rapid growth in the wireless communication has
`pushed semiconductor manufacture to seck low cost.
`highly integrated and multi-standard design for a wireless
`handset due to marketing situation - existing different air
`interface of wireless system.
`
`The paper also state different kind of standard and
`focus the main interesting topic in a high level design
`example of new receiver architecture for
`this multi-
`standard specification such as GSM, DCS1800, DECT,
`PHS. FHSS-DCT, and FHSS-WLAN.
`
`‘The paperwill focus on the description of:
`
`Introduction
`
`@
`
`@
`
`@
`
`Different kind of the multi-standards DSP based
`transceiver architecture inclide mixing analog
`function:
`
`overview among
`technical
`and
`Advantage
`different kind of the multi-standard transceiver.
`
`Describe new architecture:
`
`single conversion
`
`Digital radio personal communication most utilizing
`the band between 800MHz to 2.5GHz will play important
`role in overall communication infrastructure in next decade.
`For a multi-standards TDMA handset specification as
`shown in table 2, we know that
`tasks processing and
`resource allocation by commonalities will list as follows:
`
`Table 1.0 Multi-standard wireless system
`
`Bess eat)
`aeael!
`LAYER GSM .-FHSS-ITEM ;
`
`j
`* OCT
`mn
`
`ea
`
`
`
`
`
`|
`
`Rx Qreceiver
`
`| @
`
`/
`
`Multi-band digital tuning LNA.Mixer, plus AGC IF |,Q demodulatorin
`BiCMOS
`
`(@ Wideb
`Co
`Frequencyselect
`
`
`plus AGC IF LQdemodulator
`LNA, Mixer
`VCO+PLLfordifferent spec. and band can use :
`ie Ring OSC,clock PLL in CMOS as reference paper 1,
`
`BICMOSofCMOSmulti-bandVCOplusPLE
`/ Tx power
`
`A for different standards is mostdifficult, we can choosetechnical
`
`i
`.
`pproach:
`
`| ©—Multiple PA module in GaAS, HBT, MOSFET, BJT ( Bulky )
`
`_@—Several, multiband PA in GaAS, HBT, MOSFET, BJT
`
`
`
`.
`
`®=Single Multi-band PA in GaAS, HBT
`
`0-7803-4325-5/98/$10.00
`
`1712
`
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`
`4
`
`SAMSUNG 1039
`
`1
`
`SAMSUNG 1039
`
`

`

`
`
`
`
`Duplexing
`7
`
`
`
`«| @ =~. SeveralOR’fiter (Bulky and high cost).
`Widebandbandtunablefiter(Difficult)
`Multiple middle and wideband selectablefilter by LTCC combined
`with IR mixerin receiver and. gpurious performancetuning in
`transmitter
`
`Lo
`
`Powercontrol
`@
`Ramp & powerclass control by Mixing analog H/W and no problem
`to migrate different spec. Most important is programmable clock
`I and Ramp generator.
`
`MultipleAccess=j @
`Programmable frame based and clock generatorin digital H/W
`
`Bandwidth
`
`Modulation
`
`@
`
`Hardware DSPforiF channelselection plus IF under sampling can
`support different bandwidth channel selection spec.
`
`Hardware DSP for modulation of GMSK, G2FSK, G4FSK,
`
`pl4DQPSK
`
`Vocoder
`
`G.726, RPE_LTP(Full Rate,Half Rate, Enhance Full Rate ) easily
`include DSP S/W
`
`Frame.ch.rate__|@ProgrammableframebasedlogicandclockgeneratorindigitalHW
`Channelcoding_|¢
`
`Ch. Structure
`
`@
`
`Encryption
`
`
`
`nenoabn
`
`-
`
`Programmable frame based and clock generator in H/W and MCU
`layer 1 SAW
`_.
`
`
`AFCATCSync._|@ _DSP SW and MCU S/W
`
`AGC
`@
`DSP SWand MCU S/W
`7
`
`e@
`MCU SW
`e MCUSW
`
`Gallcontrol a
`
`Radiofescue|eCe—~
`
`Mobilit
`
`@ MCU
`
`Shortmessage|@ MCU’ _
`
`Supplementa
`@
`MCcuU*
`
`
`
`
`
`MMI Le Mcu
`
`From the TDMA commonality of the multi-
`standards as table 2, which only one different is CSMA in
`frequency hopping wireless LAN; we know the most
`difficulty for
`this multi-standards specification is
`the
`
`the
`the table 2 states,
`programmable transceiver; as
`transceiver can design as DSP portion after IF signal
`processing, this characteristic is obvious in receiver signal
`_ processing.
`
`1713 |
`
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`
`2
`
`2
`
`

`

`
`
`Table 2.0 Muiti-standard wireless system
`DCS 1800
`DECT
`
`FHSS-WLAN
`
`asisa0a
`
`
`
`Frequency:Mhz|T 890-915, T 1710-1785, 1895-1907 2400-2483.5
`
`
`
`
`
`R 935-965
`
`R 1805-1880
`
`Bandwidth
`(kHz)
`
`
`
`Modulation
`
`‘GMSK, BT=0.3
`
`G2FSK,G4FSK
`
`
`
`TOD/FOD
`
`
`
`Peak Tx power 1W MAX (USA)|1W MAX0.25W.1W 250mW
`
`
`
`Multiple Access
`
`FDMA/TDMA
`
`TDMA/FDMA
`
`TDMA/FDMA
`
`TDMA/FDMA
`
`
`
`RPE_LTP ADPCMG726|ADPCMG721 | ADPCMG726RPE_LTP
`
`
`
`
`
`32Kbivsec‘|32Kbitsec 32Kbitsec
`
`useTssisarsid- MS |
`
`
`
`
`
`Channel Rate © sates|384Kbps270,833Kbps 270.833 Kbps 1Mbps,2Mbps
`
`Standard Doc.
`
`ETS 300 175
`
`RCRStd-28
`
`(EE802.14
`
`Note: Sensitivity is an engineering specification to meet type approval.
`
`This architecture shown in Figure 1
`is not
`easily to meet multi-standard Air
`interface,
`even programmable DSP capable to process
`different physical
`layer
`1 protocol such as
`demodulation, modulation, channel coding and
`so on, but main problem is coming from
`transceiver can’t be programmable, this make
`this architecture need different kind subsystem
`
`@=Classic Transceiver plus DSP/MCU. for multi-standards, this make all seems
`
`
`
`impossible and cost expensive.
`
`Transceiverarchitecture
`.
`.
`.
`To seek low cost, highly integrated and multi-
`standard design for a wireless system, especially in handset
`or portable terminal will drive the system architecture as
`belowinto:
`
`1714:
`
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`
`3
`
`3
`
`

`

`
`
`®
`
`Transceiver: with single conversion band
`pass
`sampling wideband receiver plus
`DSP/MCU.
`
`Single conversion receiver with IF band
`pass sampling, I-Q digital mixer, AFC, AGC,
`and NCO logic is quite important at current
`stage due to difficulty of high resolution and
`higher frequency ADC with low distortion.
`This architecture as shown in Figure 2 can
`process different air interface, filter BPF-IF1
`can receive several Rx channel and do final
`channel selection at ASIC DSP portion, this
`will make filter BPF-IF1 can use middle Q
`type such as middle Q LTCC filter instead of
`higher Q SAW’s and lower Q type of VCO at
`receiver side if we choose proper sampling
`frequency;it actually means the cost down and.
`easily production of RF ‘module. This
`architecture has
`several
`characteristics
`as
`below :
`
`still.
`
`need
`
`several
`
`type
`
`1. Duplexing
`duplexer.
`It can use several middle bandwidth
`selection LNA + Double balance mixer
`for receiver front end.
`
`2.
`
`3.
`
`IF filtering can use high Q SAWfiltet or
`middle Q LTCC filter.
`
`4. AGC budget need several stages among
`LNA,
`IF -AMP, Digital Attenuator
`before ADC.
`
`5.
`
`6.
`
`architecture is this need to cancel DC-offset
`
`and deal with spurious leakage problem. Most
`difficult of DC-offset canceling is different
`physical
`layer standard with different DC- .
`offset canceling tracking filter, it is information
`dependent. This
`architecture
`has
`several
`characteristics as below :
`
`still
`
`seed
`
`several
`
`type
`
`1. Duplexing
`:
`duplexer.
`It can use several middle bandwidth
`
`2.
`
`selection LNA + Image rejection (IR)
`mixer
`for receiver front end. Several
`band IR mixer is quite difficult due to
`quadrature phase shifter, so that it need
`digital phase shift tuner
`
`3. AGC budget is same situation as band
`conversion
`pass
`sampling
`single
`architecture,
`—
`
`4.
`
`still need several
`PA in transmitter
`module,
`if we combine DDS based
`modulator as shown in Figute 5, we can
`build Image tejection mixer
`for up
`converter.
`
`are
`leakage
`spurious
`5. VCO and its
`difficult to pass specification of multi-
`standards.
`
`6.
`
`- DC-offset is also quite difficult as stated
`above.
`
`7. Major advantage ofthe architecture is IF
`filtering and channel selection, this can
`process with low Mips programmable
`ASIC DSPfilter or switching capacitor
`filter.
`
`
`
`Channelselection filter must process by
`IF processing DSP or ASIC DSP.
`PA in transmitter
`still need several
`module
`@ Transceiver with=direct
`sampling
`widebandreceiver plus DSP/MCU
`
`plus
`
`Direct sampling wideband receiver is an
`architecture without any RF mixer in RF front
`end; most of direct sampling receiver use
`under sampling approach. This architecture
`can process different air interface, filter BPF
`can receive full of Rx channel and do final
`
`channel selection at ASIC DSP portion, this
`will make filter BPF must have several band
`middle Q type LTCC, DR or SAW filter;
`Due to higher gain AGC LNA is difficult to
`integrate in one RF integrated chip, so it need
`higher dynamic range and most precise ADC
`
`receiver with
`conversion
`Direct
`baseband sampling, I-Q filtering, AFC, AGC,
`and NCO logic. This architecture shown in
`Figure 3 can process different Air interface,
`filter LPF can receive several Rx channel and
`do final channel
`selection at ASIC DSP
`portion, this will make filter LPF can use low
`Q type switching capacitor filter instead of
`higher Q SAW’s; main disadvantage of the
`
`1715|
`
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`
`4
`
`@
`
`Transceiver with
`baseband
`sampling
`DSP/MCU
`
`direct
`receiver
`
`conversion
`
`4
`
`

`

`
`
`for receiver signal. Higher precision and high
`frequency ADC is difficult subject for under
`samplingarchitecture; for example, How can a
`GSM/ICS1800 dual band receiver using a
`41MHz under sampling rate ADC operate
`precisely in 1800MHz, it is quite obvious this
`need a higher sampling rate Sigma-Delta ADC
`for precision consideration, it can convert low
`bits - higher samplingrate signal data to higher
`bits-middle rate sampling data, so that high
`precision characteristic can keep; but it. still
`have a lot challenges bke the jitter of sampling
`clock, low power consumption, longer taps of
`programmable channel filter and so on. This
`atchitecture
`has
`several
`characteristic
`as
`below:
`
`7. Higher ADC sampling tate and input
`range need.
`
`8 Higher resolution and dynamic range of
`ADC need.
`
`9. Higher IP3 LNA need due to higher
`gain at this stage.
`
`sampling
`direct
`with
`Transceiver
`wideband receiver, DDS based modulator
`plus DSP/MCU
`
`Direct sampling widebandreceiver have
`great advantage as description above, butit is
`still need a VCO to meet different
`<Air
`interface specification among standards,
`so
`DDS based modulator can overcome the
`
`than
`problem but consume higher power
`orginal one,
`the DDS based architecture
`makes transmitter frequencyselection in ASIC
`DSP portion and
`only
`a narrow band
`switchable VCO needed in RF up-converter,
`so that different standard can use same type of
`band switchable VCO. Due to low power
`DDS operating frequency up to 180MHz
`consume only 50mW at 1V CMOS process,
`DDSbased modulator will be trend for multi-
`standards wireless handset. Even,
`the high
`petformance modulator can produce; it also
`have many challenges in the jitter of DAC
`clock, low power consumption, higher SFDR,
`higher
`order
`low distortion
`switching
`capacitor filter and so on.
`
`several
`
`type
`
`still
`
`need
`
`ta
`
`1. Duplexing
`duplexer.
`Tt can use several middle bandwidth
`selection ].NA + double balance mixer
`for receiver front end.
`
`critical
`become
`is
`budget
`3. AGC
`sampling
`comparing with band pass
`single conversion architecture due to 45
`maximum AGC range in LNA.
`PA in transmitter
`still needs
`module.
`
`several
`
`4.
`
`5. Only one transmitter band switching
`VCOneed.
`
`6. No DC-offset problem.
`
`16°
`
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`
`5
`
`5
`
`

`

`
`
`
`
`
`
`—Bille|
`
`
`
`
`
`
`
`Figure 1: Classic Transceiver
`
`17
`
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`
`6
`
`6
`
`

`

`
`
`
`
`
`
`
`
`
`Antenna
`Switch LA
`
`i
`Duplexer
`
`Deokic bal.
`mixer Brrip AMP-IFt
`
`r Partet
`Ll. intend
`vee )
`Pea
`L
`
`oN
`
`
`
`
`
`bandpass
`samating
`ow
`hendpaes
`aader
`sampling
`
`contet
`
`||
`
`ooCera
`
`
`me|
`Me
`5 5|—
`|
`
`
`>
`in
`meduisier, |||walt,
`
`
`
`twhal.Cal.|nome nFInterface
`
`) (fel fog
`coir
`=
`tin
`PARampaiass|
`Kd
`mn |
`
`PAs fer different Aly intertace
`
`[|
`
`|L
`
`L
`
`5 OW|ASIC, | mrecess
`
`7
`
`ik
`
`Time
`
`generator
`
`Figure 2 : Transceiver with single conversiun band pass sampling receiver
`
`1718
`
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`
`7
`
`7
`
`

`

`
`
`
`
`
`
`
`
`
`
`
`
`generater
`
`
`
`
`PAstor different Mr imteriace
`PA
`
`H
`
`Modulates
`
`™ A
`
`SIC,
`modulatsr, .
`Ramp,
`Interface
`tubal. cal.
`contrel,
`Clock
`
`Figure 3 : Direct conversion transceiver with baseband sampling
`
`1719
`
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`
`8
`
`8
`
`

`

`
`
`
`4
`
` control YEO ref. cteck «——-
` aa“ot
`
`
`
`
`Jke)esL.~
`
`PAs fer different Air interiace
`
`thee |
`
`I ||
`
`|i
`
`moeduiater,
`Rams,
`imbal.cal,
`cal
`
`interface
`contrel,
`Cleck
`Generaier
`
`Distortion cal,
`
`oN
`
`|!
`ii
`
`Figure 4 : Transceiver with direct sampling receiver
`
`1720
`
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`
`9
`
`9
`
`

`

`
`-
`
`fol.
`\88
`=
`
`| LA
`
`SFRR>15a8
`
`
`
`
`
`
`
`
`
`
`
`“laxLftase
`Buf,
`Ae,
`age,
`
`PAs fer Hitferent Air imertace
`PA
`PABA
`
`control WEB rei.cleck
`ace
`Beuhie
`bantance
`miner
`
`
`
`Time
`Brecess
`™
`uu,
`ASIC,
`RF
`,| Medadater,
`ams,
`interface
`aeeruen |{|contrel,
`°
`Cleck
`Ny
`
`|_|
`
`
`
` Fe Paitaneatiass ne |
`
`Figure 5 : Transceiver with direct sampling receiver and DDS based modulator
`
`RF receiver signal processing by
`RF plus DSP unit
`
`To seek highly integrated multi-standard design for a
`wireless receivér system, In RF front end with no double to
`use RF signal processing architecture as figure 2 will be
`suitable at current generation of BiCMOSprocess.
`
`1. IF frequency selection and
`sampling clock
`
`Wecan see the simulation clock for different spec.
`
`of wireless system using bandpass under sampling scheme
`as below, we can understand selection of sampling clock
`and IF frequency is
`important as you think about
`performance and cost.
`It must satisfy the mle below
`according to sampling theory in reference book 1, 2,
`
`2* BWerr <n* feampte - IFiieq. 7n= 1,3, ... and select
`several channelinto IF,
`‘
`
`feampte < 28MHz for performance, power and cost
`consideration in under sampling IF signal
`processing scheme
`
`721
`
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`
`10
`
`10
`
`

`

`
`
`
`rey
`
`ee ee
`TSCUerialanerltedehieeyule
`Taxes
`
`
`
`
`
`[26.00__|2s40.01+010|9=294.00,234.10-01M;241Mha<Fe<246.0N2|
`
`[ascoamenasrussuay
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`234.0+0.1 + 0.10
`
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`
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`pas|2600|aarats«015|Fe=294.00,234.162I<2465M224.1606-0.15Mbz
`
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`foccr|19430__|amneteo65|rarta=230616,204-0a5Mi;240.4562cA650M|
`
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`
`
`
`Samplingrelationtableclock
`
`
`
`
`From the bandpass sampling scheme and theory, IF
`center frequency must meet:
`
`N*Fs/2+(BW/2) < IFfreq < (N+1)*Fs/2-(BW/2); to achieve
`free aliasing bandpass sampling scheme
`
`from
`frequency
`IF
`the
`select
`can
`we
`234.15~242.4MHz and using a SAW filter with 238.275+-
`3.275MHz bandwidth andit’s adjacent channel with higher
`rejection about 65dB; so we need a SAW filter with higher
`order ! Could we find a widebandfilter to minimize the cost
`
`ofIF filter ? It means we need to find a clock generator to
`tune the sampling clock to the frequency and make all under
`sampling IF band ADCashighas possible.
`
`From the table above, we know if we find common
`ratio frequency for sampling clock then the IF filter can
`cost down to middle Q type LTCCfilter due to 6~10%
`bandwidth dependency on sampling frequency; we know
`the commonratio frequency can deduce by system clock as
`table below from the multi-standard specification of
`physical layer specified above :
`
`
`
`
`
`SPEC. eenD
`“System Clock
`TCCUaroliemoceon en
`[osm|2iss76wme
`
`Fs*11= 241.3125 Mhz
`
`
`
`
`FHSS-DCT_| em|21.9375Mhz
`
`
`
`
`Band : 221.103 ~ 239.5845 Mhz
`
`DCS1800
`21,9375Mhz
`
`
`
`DECT
`
`21.9375Mhz
`
`21.9375Mhz
`
`
`
`FHSS-LAN|21.9375Mhz 1.0 or 2.0Mhz
`
`2.AGC, Dynamic range and ADC
`
`IM,and other performance in ADC :
`
`
`
`@ Pingniay|+—PGemaxy io *
`
`In order to build a digital receiver architecture as
`Figure 2, we need to find the how much of AGC gain
`
`enough for system performance budget. We know the
`Log((Vip/Ritiag.)/0.01);
`optimized sensitivity range must ensure the correct
`operation in the receiver’s ADC for smaller signal, this
`means we need to satisfy the rule below at optimized SFDR,
`
`
`
`@
`
`DR =P, + Gtot + P3; P, = It is 3 intersection
`pointofthe digital receiver system,it is relative
`
`1722 °
`
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`
`11
`
`11
`
`

`

`
`
`to ADC maximum operation voltage, so that for
`a digital Attenuator impedance ADC, we can
`
`understand the situation from impedancelisting
`below :
`
`
`
` aS of Attenuator
`
`Vatay of ADC
`
`a
`
`200K Ohm
`
`5K Ohm
`
`
`
`
`
`@®
`
`The Dynamic range (DR) for Idea ADC 1 I bit is
`67.76dB, We know DR = PidBe - ( KTB +
`3dB + Ftot + Gtot ) for RF system, a digital
`teceiver need to plus the effect of ADC in
`following receiver architecture;
`[If we design
`Gi yatGmixertGipamp from 76 ~ -13dB for 13bit
`ADC,Noise figure NF of system is 5dB, Piss
`and IP3 of RF frost end is 6dBm/9dBm, then
`maximum P, will be above 2dBm, the DR of
`bandpass sampling system below is 86dB;
`
`@ Minimum operating input voltage is 0.006V for
`minimum signal
`to quantization noise and
`minimum input power to ADC with impedance
`at SOK ~ 10K ohm will be -71dBm, so that
`overall system effective signal capture range is
`from -117dBm ~ -0.5dBm.
`
`@®
`
`ADC bit
`below:
`
`resolution can select by the rule
`
`1.
`
`|
`
`To find signal desired ADC dynamic
`range specification by:
`
`.
`InterferenceLeveltacimumadjacentChannel
`SignalLevelminimum -
`leveltatenvaion | +
`
`10*Log( Bandwidthgigna ) + Levelgensitivity
`- Levelnoiss
`=
`DR.
`( which is
`Dynamic range specification )
`
`attenuation
`the
`is
`Levelanention
`interference by IF band passfilter;
`
`of
`
`InterferenceLevelytaximumAdjacentChannel
`maximum adjacent interference level;
`
`is
`
`SignalLevelyinimum is minimum signal level to
`ADC;
`
`Levelgensitivity is receiver sensitivity,
`
`Levelnoise is receiver noise power;
`
`2.
`
`Calculate the numberof bits of ADC by :
`
`DR = -1.249 + 10*Log( Freqsampte ) +
`6.02 Bitsyumber
`
`Freq.ampte is Sampling frequency of
`ADC;
`
`so that, 12~14 bit ADC will be good enough to
`meet different specification.
`
`Miner
`
`
`;
`
`
`sng Denble bol. nrg9 aupsar|ane
`
`|<(9
`
`
`
`
`1723
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`
`12
`
`12
`
`

`

`
`
`if optimized operating ADC input voltage is around 0.6V
`at 1.8V VCC, and Rinag, can design around 200K ~ 5K
`Ohm,
`then we can summarize the AGC performance
`needed with different ADC resolution below. It means we
`
`- performance optimization by
`need to make a cost
`-technology; From the point of view of cost, power
`consumption and RF performance availability,
`13 bit
`Sigma - Delta ADC will be a good design in current
`technology.
`
`ETS 300 175
`Standard Doc.
`
`
`RCR Std-28
`
`1EE802.11
`
`open
`
`-105dBm
`-96dBm
`-104dBm
`-96dBm
`“Sensitivity
`
`
` Gre = 69~-7
`
`“Blocking
`
`ADC(12bit)
`
`ADC(13bit)
`
`Grr = 793
`
`Grr = 69~-7
`
`Gre = 74~-1
`
`Grr = 63~-13
`
`Gre = 63~-13
`
`3. Multi-rate Multi-stage
`channelfiltering
`
`After LNA, Double balance mixer, IF Amplifier, IF
`pre-filrering, AGC control and ADC sampling and first
`digital mixer, we catch several receiving channel; it need to
`select the wanted channel and processing into I, Q RF base
`band for DSP software manipulation. We know the
`optimized channel selectivity must spend a lot of Mips in the
`ASIC DSP, this means we need to do rate conversion in
`multiple stage to minimize the Mips and power consumption
`in ASIC DSP. For example,
`to select a 200KHz GSM
`channel after bandpass under sampling band 0~6MHz
`bandwidth with high sampling rate as ADC need 720 Mips I,
`Q digital mixer and 130 Taps I, Q channel selection filter to
`meet
`the specification of GSM, it is not practical, higher
`power consumption, and none cost effective.
`
`The opimum decimation filter and two stage digital
`
`mixer is important for single conversion bandpass sampling
`receiver design; From basic FIR filter design, we know the
`approximate number of taps required by an FIR filter can
`find by the equation” below:
`
`N =(-10Log(R/ Asp) —15)/(14fr/fs) +1;
`
`N is number of Taps;
`
`Ris peak passbandripple;
`
`Ajtp is stopband attenuation;
`
`fris transition bandwidth;
`
`fv is sample rate;
`
`If the decimation filter act like Y(n) like below:
`
`1724.
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`
`13
`
`13
`
`

`

`
`
`X(n)
`
`.
`
`
`
`
`
`Yan)
`
`
`
`
`
`
`at each sampling time to N/2 Tops -
`
`It's frequency response will behave as below and transition
`band become fr = ( f:/M1 - faop ) - fp , then we can use
`digital 1, Q mixer plus numeric control oscillator to down
`
`convert passing band by decimation filter to I, Q baseband
`and filtering desired channel as shown in block diagram
`below.
`
`Ht)
`
`'
`
`fs/Mi1-fstop_ +
`<= —_—>
`a
`a >a -——
`
`,
`
` fs/M 1
`
`1725
`
`us
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`
`14
`
`14
`
`

`

`
`
` 4p4.sg
`
`| Ade
`
`bondpate
`feaid tompling
`
`> Sumpling rate
` Decimals
`
`sts
`
`ap4.98 | ADE
`:
`g
`/y CS
`ape
`
`filter
`Z
`
`oo
`
`bandpass O80fram
`wander—tabs look up;
`sampling
`40 that
`Saenpling rate
`OSCfreqneny
`=F
`= Ff 246 )
`
`Jsing decimationfilter, we reduce a lot Mips need in channel
`:
`.
`ee
`filrering, so that if we can choose several stage decimation
`FIR filter, we can reduce the FIR filter to Mips due to less
`:
`.
`sampling clock after each, then wecan getthe selection band
`by filtering
`output RF baseband from [Q digital mixer
`°
`B
`oulp
`aed
`output down with NCO generating output
`frequency
`Fc=2.16MHz.So that, the 1, Q basebandselection filter can
`reduce to a lot of Mips, cost, and power consumption. We
`
`can fix our programmable channel selection filter in LQ
`baseband filtcr
`to minimize power consumption due to
`«0,
`able filter need more
`power than fix FIR filter in
`programm
`e
`.
`po
`.
`ASIC DSP. For multi-standards channel selection, the I, Q
`.
`baseband filter have variable Taps from 22~64. We can
`estimate the summarized computation load shown below by
`. . .
`.
`TMS320CS4x instruction, if sampling clock of ADClist as
`sampling clockrelation table above:
`
`
`
`Transceiver Mipsneedin Single conversion bandpass sampling Receiver
`
`Architecture by TMS320C54x like instruction
`
`oe[sm[oe[we[oman[res
`
`peje_jr_tete[a|]
`
`le stage Digital |, Q Mixer
`
`
`
`NCO ( Phase accumulator Osc
`
`
`—[25|
`
`|Decimationfiter2:1
`
`| Cecimation fter 24
`
`
`
`1726
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`
`15
`
`15
`
`

`

`
`
`Decimationfilter 2:1
`Decimation filter 2:1
`Decimationfilter 2:1
`
`Powerconsumptionby.25uprocess(mw)|241
`
`
`
`|, Q RF basebandfilter
`
`If we can use a multi-stage digital mixer plus decimationfiler,
`
`we can get transceiver Mips down much shown in table
`below :
`
`
`
`Transceiver Mips need in Single conversion bandpass sampling Receiver
`Architecture by TMS320C54x like instruction
`
`
`|osu|DCsi800=|DECT FHSS-WLAN|FHSS-DCTPHS
`
`
`
`
`1Digital |,Q Mixer 12|12 40 12
`
`
`1sNCO ( Tabie look up)
`Decimationfilter 2:1
`34
`
`Decimationfilter 2:1
`
`
`
`2”4 Digital 1,Q Mixer
`
`24
`
`13
`
`3.8
`
`
`
`
`24 NCO(Phase accumulator Ose
`
`72084111.8|402.5
`
`
`
`This transceiver architecture give us a understanding
`about Mips and power consumption reduction due to multi-
`stage multi-cate decimation filter approach;this also give us a
`general aschitecture of a programmable DSParchitecture as
`below; this DSP architecture can be a most reduce form
`from general DSP as TMS320C54x into a FIR filter, multiple
`
`MAC sequencer and so on. This could reduce power
`consumption of programmable digital receiver, by the way,
`the powcr consumption of the DSP sequencer must meets
`the 0.1 ~ 0.2 mw/Mips for
`the handset
`in different
`specification, this can easily reach by reduction of computing
`unit from TMS320C54x like DSP sequencer and CMOS
`process improvement.
`
`W27
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`16
`
`16
`
`

`

`
`
`
`
`
`
`Sampling rate
`=Fs
`
`Song, K. Bahrain, IEEE Symposium on VLSI Circuits,
`June 1994,
`
`6.
`
`“A 10-bits 40Msamples/s BiCMOS A/D converter,
`“T.-H. Shu, B.-S. Song, K. Bacrania, R. Gokhale,
`IEEE Symposium on VLSI Circuits, June 1994.
`
`Author:
`
`Chaucer Kuois Business manager of Wireless
`business unit, Asia; he major in DSP technology, signal
`processing architecture and he awards Senior Member
`TechnicalStaff in 1996
`
`John Wongreceived BS in EE, from National
`Taiwan Institute of Technology, 1982. He joins Taxis
`Instrument Taiwan DSP LBEof Wireless communication
`system on Dec. 1996. He has at least 10 years in Wireless
`Telecommunication, especially major in wireless
`communication include RF, analog and digital signal
`processing plus wireless communication system design. He
`awards Member Group Technical Staffof Taxis
`Instrument in 1998.
`,
`
`Conclusion
`
`To design a multi-standards DSP based wireless
`handset, we
`first
`inspect
`the
`different
`transceiver
`architecture, choose suitable one according to each
`component status, then do performance budget and design
`each stage of signal processing algorithm, and find
`computation load and define DSP receiver architecture.
`This paper will help all reader understand designing a
`Multi-standard architecture and different kind DSP based
`wireless architecture,
`
`Reference:
`
`1.
`
`“Discrete - Time Signal Processing “, Oppenheim
`Schafer, Pretice Hall
`
`“ Digital communication “, Proakis,McGRAW-HILL
`
`“ A simple Method of sampling In-phase and
`Quadrature component”, IEEE-pub. Vol. AES-20, No.
`6, Nov, 1984, pp. 821 821-824.
`“Some Comparisons between FIR and IIR Digital
`Filter ”(8), p.308, with permission. Copyright 1974 by
`AT&T
`“A 13bit 10MHz ADC background - calibrated with
`seal - time over sampling calibrator “, T.-H.Su, B.-S.
`
`4.
`
`5.
`
`1728
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`
`17
`
`17
`
`