Low-Power Implementation of a Fifth-Order Comb Decimation Filter for
`Multi-Standard Transceiver Applications
`
`Yonghong Gao and Hannu Tenhunen
`Electronic System Design Laboratory, RoyalInstitute of Technology
`Electrum 229, Isafjordsgatan 22, SE-164 40 Kista, Stockholm, Sweden
`gaoyh@ele.kth.se
`
`ABSTRACT
`
`In multi-standard transceivers a programmable
`decimationfilter is required to perform channel
`select filtering at baseband since the channel
`bandwidths, sampling rates, and CNR require-
`ments are different. This paper presents a low
`powerfifth-order comb decimation filter with
`programmable decimationratios (16 and 8) and
`sampling rates (12.8 MHz and 44.8 MHz) for
`GSM and DECTapplications. The non-recur-
`sive architecture for combfilter is employed and
`low power VLSI implementation techniques are
`developed.
`
`INTRODUCTION
`
`converter.
`While the sampling rate and resolution of
`oversampling SD A/D converters are typically
`determined by their analog modulators,
`the
`power consumption is governed largely by the
`digital decimationfilters [2]. It is possible to at-
`tenuate the quantization noise and undesired
`channels with a single filter and then decimate to
`the Nyquist rate, but this approach consumes
`much power. By decimating in multiple stages,
`the complexity of the filters is reduced, and sub-
`sequentfilters operate at lower samplingrates,
`further reducing the power consumption [3]. In
`multi-stage decimationfilters it has been shown
`in [4] that the combfilter is an efficient way to
`decimate the output of the analog modulator to
`four times the Nyquist rate. Fig. 2 shows a multi-
`Recent research on radio frequency (RF) com-
`stage decimation filter suitable for GSM and
`munication transceivers focuses on both higher
`DECTapplications. To meet the system require-
`integration and multi-standard operation. High-
`ments, a fifth-order comb decimation filter (6-bit
`er integration can be obtained by optimizing re-
`input) with programmable decimation ratios
`ceiver architectures to eliminate the off-chip
`16(GSM) / 8(DECT), and sampling rates 12.8
`components. The receiver architectures that per-
`MHz(GSM) / 44.8 MHz(DECT)
`is needed.
`forms channelselect filtering on chip at base-
`Since the combfilter operates at the high sam-
`band
`are
`preferred
`since
`digital
`signal
`pling rate its power consumptionis large. Hence
`processing techniques can beeasily applied to
`low power implementation of the combfilter is
`adapt to multiple communication standards. Fig.
`very important.
`1 shows the wide-band intermediate frequency
`The non-recursive architecture [5] for comb
`with double conversion (WIF)architecture [1]
`filters has lower power consumption compared
`which can be used to implement a multi-stand-
`with Hogenauer’s
`cascaded-integrator-comb
`ard (DECT and GSM)receiver. The WIF archi-
`(CIC) architecture [3] especially whenthefilter
`
`
`
`tecture a_highneeds dynamic range
`
`orders and decimation ratios are high. In this
`oversampling sigma-delta (SD) analog-to-digit-
`paper
`the
`non-recursive
`architecture
`is
`al (A/D) converter that can adapt to the different
`employed to design the combfilter. Low power
`requirements from the multi-standards. The dy-
`techniques have been developed for VLSI
`namic range of a SD A/D convertercanbe easily
`implementation of the non-recursive architec-
`adjusted by selecting different oversampling ra-
`ture.
`tios. Therefore a decimationfilter with program-
`mable decimation ratios is needed in the A/D
`
`SAMSUNG 1025
`
`1
`
`SAMSUNG 1025
`
`

`

`RF Filter
`
`Sigma-Delta
`
`3,
`Fig. 1. Wide-band IF with double conversion receiver architecture.
`
`x(n)
`va)
`
`IN |Fifth-order}.|Halfband|.|Halfband OUT
`
`of eet feet>at ) 2 a+z) 2 2
`
`FIRfilter
`
`
`
`combfilter
`filter
`filter
`Stage 1
`Stage 2
`
`N, = 16o0r8
`
`N;=2
`
`Stage MW
`
`Fig. 2. Multi-stage linear-phase decimationfilter.
`
`Fig. 3. The non-recursive architecture for comb decima-
`tion filtcrs.
`
`REVIEW OF THE NON-RECURSIVE ARCHITECTURE
`
`pared with the CIC architecture.
`
`Combfilters has the following transfer function
`
`LOW POWERIMPLEMENTATIONOF THE NON-
`RECURSIVE ARCHITECTURE
`
`“yy
`
`
`(N-1
`
`H(z) = (! =] =| 2°
`
`lz
`
`i=0
`
`One approach to implement each stage (142!)
`is to cascade the (+z!) processing element,
`shown in Fig. 4(a). In this paper 4 is 5. By fur-
`ther investigating this approach, we noticed that
`where JN is the decimationratio andkis the filer
`half of the computational operation is not neces-
`order. Notice that sometimesa scaling factor 1 /
`sary in each stage since only half of the output
`N* is includedin the transfer function in order to
`data will be fed into the next stage becauseofthe
`make the de gain unity.
`decimating by a factor of 2. In order to reduce
`Usually the decimation factor N is chosen to
`power consumption the unnecessary computa-
`be M-th power-of-two, i.e. N= 2™ Thetransfer
`tion should be eliminated. Based on this consid-
`function can be rewritten as
`eration, we developed a new technique to
`implement each stage. Using polyphase decom-
`position [6][7], the transfer function (Itz!) of
`each stage can be rewritten as
`
`(1)
`
`(2)
`
`k
`
`k
`
`k
`
`H(z) = datz!) (+27) dt27) fit? }
`
`M-~1yk
`
`the non-
`By applying the commutative rule,
`recursive architecture for comb decimation fil-
`ters is resulted, shownin Fig. 3. The switches in
`the figure indicate the reduction in the sampling
`rates by a factor of 2. Every stage is a simple
`FIR filter (ie.,
`( L427}, The word length
`increases through every stage by k bits but the
`sampling rate decreases through every stage by
`a factor of 2. Reducing the sampling rates as
`early as possible helps to save power consump-
`tion. On the other hand, the wordlength of the
`first stage is very short (m + k, where m is the
`wordlength of the input x(7)) so the non-recur-
`sive architecture can achieve higher speed com-
`
`“408
`_
`_
`_
`14
`= 1452 410274102 2452 742°
`H(z) = (1~z 4)
`=(1+ loz7+ sz4) +2! (5+ loz7 +24)
`= Eg)+2E>)
`
`(3)
`
`where E((?) and EWZ) are polyphase compo-
`nents. By applying commutative rule, a low-
`powerpolyphase implementation for each stage
`is resulted, shown in Fig. 4(b). Where
`Eg(z) = 1+ 10:| +527
`1
`2
`E,®)= S5+10z +2
`
`(4)
`
`2
`
`

`

`by+2
`
`b;+3
`
`b;t4
`
`bts
`
`are are are ary ab.
`
`IN. eee
`
`Fig. 4(b). Polyphase implementation for each stage.
`
`Fig. 4(a). An implementation of stage i by cascading
`a+ zy computational element.
`
`b;
`
`bol
`
`IN ne
`
`x(n)
`
`
`
`
`
`
`
`Fig. 5. Implementation of Ey(z) (a) The direct-form structure for FIRfilter; (b) The data-broadcast structure; (c) The
`multiplications are simplified to a few of shifts and adds; (d) The low-power implementation with substructure shar-
`ing.
`
`In this implementation, the input is decimated
`by 2 at first and the odd-numbered input data
`will go through E,(z) and even-numbered input
`data will go through E)(z). The output data are
`obtained by adding all polyphase components
`(Eg(z) and E}(z))
`together. Notice that cach
`polyphase operatesat half of the input sampling
`rate (i.e., f; /2, where f,; is the input sampling
`rate of stage 7) meanwhile the unnecessary com-
`putation
`has
`been
`eliminated. Therefore
`polyphase implementation consumes less power
`than the cascade implementation.
`each
`of
`Low power
`implementation
`polyphase component(FIRfilter) is also impor-
`tant. A FIR filter can be designed with different
`structures. We take polyphase component E(z)
`(see (4)) as an exampleto illustrate this. The di-
`rect-form structure is shown in Fig. 5(a). The
`critical path for processing a new sample is lim-
`ited by 1 multiply and 2 add timesso this struc-
`ture has lower speed. An alternative approach to
`reduce the critical path of the direct-form struc-
`ture without introducing any pipelining registers
`is to transpose the structure with the transposi-
`
`tion theorem [8]. Fig. 5(b) showsthe transposed
`structure which is referred to as data-broadcast
`structure. Notice that the critical path is reduced
`to 1 multiply and 1 add timesso the data-broad-
`cast structure can operate at higher speed. This
`makes it possible to use simple lower-speed
`adder to perform the addition in the moderate-
`speed applications instead of high-speed adders,
`such as carry-select adders and carry-lookahead
`adders, etc. Power consumption caused by the
`addition operation can be reduced. Another low-
`powerissue is how to implement the multiplica-
`tions in Fig. 5(b). First the multiplications are
`simplified to a few of shifts and adds, shown in
`Fig. 5(c). 5x(n) is calculated as 22x(n) + 2°x(n)
`and 10x/(n) is calculated as 23x(n) + 2!x(n). The
`data-broadcast structure make it possible to use
`substructure sharing techniques to reduce the
`power consumption. For example, 10x(n) can be
`obtained by only left-shift 5x(n) 1 bit instead of
`using 4 shifts and 1 add. This is shownin Fig.
`5(d).
`Finally the block diagram of the whole deci-
`mation filter is shown in Fig. 6. There are four
`
`3
`
`

`

`
`By.2 «.. by bh bo
` w-1 bits
`
`Fig. 6. The block diagram ofthe fifth order comb decimation filter with a decimation ratio of 8 or 16.
`
`Original x:
`
`MSB «——————_- LSB
`sign
`bgion
`Dy-2 «.. bz by by
`
`,
`
`: beien bigh bsion beign
`: beign bsign by2 byes b, bo 00
`-
`$1 Sq b; bo
`
`Dg;gnOcarr$w-28w-3 ~
`
`:
`
`(a)
`
`Fig. 7. Low power implementation of 5x (= xt 2x),
`
`stages. Each stage is implemented with the
`same structure (polyphase plus data-broad-
`cast). The switches in the figure indicate the
`reduction of the sampling rate, and the number
`close to each adder indicates the wordlength of
`the adder. For GSM applications,
`the four
`stages are neededsince the decimation ratio is
`16. But for DECT applications, only first three
`stages are needed because the decimation ratio
`is 8. In this case, a reset signal will make stage
`4 inactive to save power consumption.
`Recall that each polyphase component has
`the 5x(n) operation, and 5x(n) is calculated as
`2?x(n) + 2°x(n) (see the shadowedareasin Fig.
`
`6). If the wordlength of x(n) is w, a (w+3)-bit
`adder is needed in the 2’s complementarithme-
`tic to avoid the overflow problem. At first
`2°x(n) and 2?x(n) are extended to (w+3) bits as
`shownin Fig. 7(a). Notice that the two LSB bits
`of 2?x(n) are zero and the two MSB bits of
`2°%x(n) and 27x(n) are Dsjgn. The two LSBbits of
`5x(n) will be “b,bp” and the first MSB bit of
`5x(n) will be “b,jo,,”. In actual design we only
`need a (w-1)-bit adder (the shadowed area in
`Fig. 7(a)) to get other bits. Therefore we save 4
`bits in the adder wordlength. As an example,
`assume w = 6. We only need a 5-bit adder
`
`4
`
`

`

`ulation,” ZEEE Trans. on communications,
`vol. COM-34, pp. 72-76, 1986.
`[5] Y. Gao, L. Jia, J. Isoaho and H. Tenhunen,
`“A comparison design of comb decimators
`for sigma-delta analog-to-digital convert-
`ers,” to appear on the International Journal:
`Analog Integrated Circuits and Signal
`Processing, Kluwer Academic publishers,
`ISSN: 0925-1030, 1999.
`[6] P. P. Vaidyanathan, “Multirate digital filters,
`filter banks, polyphase networks, and appli-
`cations: A tutorial,” in Proc. of the IEEE,
`vol. 78, no. |, pp. 56-93, Jan. 1990.
`[7] Y. Gao, L. Jia and H. Tenhunen, “A Partial-
`Polyphase VLSI Architecture for Very High
`Speed CIC Decimation Filters,” to appear in
`Proc. the 12th Annual 1999 IEEE Interna-
`tional ASIC/SOC Conference(ASIC’99),
`USA, 1999,
`[8] Keshab K. Parhi, VLSI Digital Signal
`Processing Systems: Design and Implemen-
`tation. John Wiley & Sons, ISBN Number:
`0-471-24186-5, 1999.
`
`instead of a 9-bit adder to complete the 5x(n)
`operation as shownin Fig. 7(b).
`
`CONCLUSIONS
`
`A low-powerfifth-order comb decimationfilter
`with programmable decimation ratios (16 and
`8) and sampling rates (12.8 MHz and 44.8
`MHz) has been presented for GSM and DECT
`applications. Low power
`consumption
`is
`achieved by the following approaches: 1) the
`non-recursive architecture for comb decima-
`tion filter is employed; 2) unnecessary compu-
`tation
`is
`eliminated
`with
`polyphase
`implementation of
`each
`stage;
`3)
`each
`polyphase component
`is
`implemented with
`data-broadcast
`structure, and multiplications
`are simplified to a few of shifts and adds then
`substructure sharing techniques is applied to
`minimize the number of shifts and adds; 4)
`5x(n) is realized with a (w-1)-bit adder instead
`of a (w+3)-bit adder.
`
`ACKNOWLEDGMENTS
`
`This work is financially supported by SSF
`(Foundation for Strategic Research in Sweden).
`
`REFERENCES
`
`[1] J. C. Rudell, Jia-Jiunn Ou, T. B. Cho, G. Ch-
`ien, F. Brianti, J. A. Weldon, and P. R. Gray,
`“A 1.9-GHz wide-band IF double conver-
`sion CMOSreceiver for cordless telephone
`applications,” JEEE Journal of Solid-State
`Circuits, vol. 32, no. 12, pp. 2071-2088,
`1997,
`[2] Brian P. Brandt and Bruce A. Wooley, “A
`low-power, area-efficient digital filter for
`decimation and interpolation,’ JEEE Jour-
`nal ofSolid-State Circuits, vol. 29, no. 6, pp.
`679-687, 1994.
`[3] B. B. Hogenauer, “An economical class of
`digital filters for decimation and interpola-
`tion,” JEEE Trans. on Acoustics, Speech and
`Signal processing, vol. 29, no. 2, pp. 155-
`162, April 1981.
`[4] J. Candy, “Decimation for sigma-delta mod-
`
`5
`
`

`

`4/27/22, 10:52 PM
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`4/27/22, 10:52 PM
`
`https://people.kth.se/~hannu/Publications.htm
`
`
`International
`
`Journal
`
`of
`
`Embedded
`
`and Real-Time
`
`Communication
`
`Systems. 2012; 3(2):1-22.
`
`
`“Survey of Self-
`Isoaho, H.
`L. Guang, E. Nigussie, J.
`26.
`Tenhunen,
`
`Adaptive On-Chip Networking with Energy-Efficiency and Dependability
`
`“,
`accepted to Int.
`J.
`of Embedded and Real-Time Communication
`Systems
`(IJERTCS), 2012
`
`
`
`
`Isoaho & H.
`27. E. Nigussie, J. Plosila, S.Tuuna, J.
`Tenhunen, “Energy
`efficient semiserial on-chip link through circuit optimization and
`
`integration of signaling techniques”,
`accepted to IEEE Transactions
`
`
`Systems, 2012
`on Very Large Scale Integration (VLST)
`
`Rahmani A M, Vaddina K R, Latif K, Liljeberg P, Plosila J,
`28.
`
`Tenhunen H. Design and management of high-performance, reliable and
`
`
`
`thermal-aware 3D networks-on-chip.
`IET Circuits, Devices & Systems.
`2012; 6(5):308-321.
`
`29.
`Amin Y, Shao B, Chen Q, Zheng L, Tenhunen H. Electromagnetic
`
`analysis of RFID antennas for "green" electronics. Electromagnetics.
`2012;
`
`
`
`30. Amin Y, Kanth R K, Liljeberg P, Chen Q, Zheng L, Tenhunen H. Green
`
`wideband RFID tag antenna
`for
`supply chain
`applications.
`IEICE
`Electronics Express. 2012; 9(24):1861-1866.
`
`
`
`
`31.
`Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Flich J,
`
`Tenhunen H. Path-based Partitioning Methods for 3D Networks-on-Chip
`
`2012;
`with Minimal Adaptive Routing.
`IEEE Transactions on Computers.
`99:1-16.
`
`32.
`
`
`"Skewing-based method for
`Isoaho, H. Tenhunen,
`J.
`S. Tuuna,
`reduction of functional crosstalk and power supply noise caused by
`
`
`on-chip buses, accepted to
`IET Computers & Digital Techniques, 2012
`
` !"# $!%& $'ÿ)&*# $'ÿ&+ÿ,-."//"/ÿ$ /ÿ0"$'12%-"ÿ3&--* %4$!%&
`567!"-78ÿ9:;9<ÿ=>9?@;1998
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`33. Guang L,
`Kanth R, Plosila J, Tenhunen H. Hierarchical Monitoring
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`in Smart House:
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`End-of-Life Study of Polymer
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`12
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`7/93
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` 
`
`12
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`

 

 


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`13
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`4/27/22, 10:52 PM
`
`https://people.kth.se/~hannu/Publications.htm
`
`Modules
`
`
`D Sensing and Wireless Applications.
`
`12; 130:241-256.
`Electromagnetics Research-PIER. 20
`
`
`for RFI
`
`Progress
`
`in
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`
`
`
`
`49. Amin Y, Chen Q, Zheng L,
`
`Flexible UHF RFIID Antennas
`
`Electromagnetics Research-PIER. 20
`
`Tenhunen H.
`for
`
` Development and Analysis of
`"Green" Electronics. Progress
`in
`12; 130:1-15.
`
`50.
`
`Amin Y, Chen Q, Tenhunen H,
`
`
`Printable
`RFID
`Antennas
`for
`Electromagnetic Waves and Applicat
`
`Zheng L.
`"Green"
`
`Evolutionary Versatile
`Electronics.
`Journal
`
`ions. 2012;
`
`26(2-3):264-273.
`
`2011
`
`Top
`
`Kanth, Rajeev Kumar
`Qiansu and Kumar, Harish and
`and Wan,
`and Zheng, Lirong and Tenhunen,
`Liljeberg, Pasi
`and Chen, Qiang
`Environment Assessment and Toxic
`Hannu, "Evaluating Sustainability,
`of Printed Antenna"
`in Elsevier/
`Emissions
`in Life Cycle Stages
`
`
`1-6
`Science Direct, 1, Dec, 2011, pp.
`
`and
`Liang and Liljeberg, Pasi
`Yin, Alexander Wei
`52.
`and Guang,
`
`Jouni and Tenhunen,
`Hannu, “Hierarchical
`Rantala, Pekka and Isoaho,
`
`in International Journal of
`Agent Based NoC with
`DVFS Techniques"
`
`
`
`for
`Design, Analysis
`and Tools
`Integrated Circuits
`and Systems
`
`
`
`
`32-4
`(IJDATICS), 1, Jun, 2011, pp.
`
`
`
`0
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