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`Paper No. 1
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
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`
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`v.
`NETLIST, INC.,
`Patent Owner
`
`Patent No. 11,016,918
`Issued: May 25, 2021
`Filed: December 30, 2020
`Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, and Jayesh Bhakta
`
`Title: Flash-DRAM Hybrid Memory Module
`Inter Partes Review No. IPR2022-00996
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`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 11,016,918
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
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`TABLE OF CONTENTS
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`I.
`
`Page
`PETITIONER’S MANDATORY NOTICES ............................................. 1
`A.
`Real Parties-in-Interest (37 C.F.R. § 42.8(b)(1)) .................................. 1
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) .............................................. 1
`C.
`Lead and Back-up Counsel (37 C.F.R. § 42.8(b)(3)) ............................ 2
`D.
`Service Information (37 C.F.R. § 42.8(b)(4)) ....................................... 2
`INTRODUCTION ......................................................................................... 3
`II.
`III. COMPLIANCE WITH REQUIREMENTS FOR A PETITION
`FOR INTER PARTES REVIEW ................................................................. 3
`A.
`Standing (§42.104(a)) ............................................................................ 3
`B.
`Identification of Challenge (§42.104(b)) .............................................. 3
`IV. RELEVANT INFORMATION CONCERNING THE
`CONTESTED PATENT ............................................................................... 4
`A.
`Effective Filing Date of the 918 Patent ................................................. 4
`B.
`The 918 Patent ....................................................................................... 5
`1.
`Technical Overview .................................................................... 5
`2.
`Prosecution History and §325(d) ................................................ 7
`Person of Ordinary Skill in the Art (“POSITA”) .................................. 8
`C.
`Construction of Terms Used in the Claims ........................................... 9
`D.
`V. OVERVIEW OF THE PRIOR ART .........................................................10
`A. Harris (EX1023) ..................................................................................10
`B.
`FBDIMM Standards (EX1027-28) .....................................................11
`C.
`Amidi (EX1024) ..................................................................................12
`D. Hajeck (EX1038) .................................................................................12
`E.
`Spiers (EX1025) ..................................................................................13
`VI. ARGUMENT ................................................................................................14
`A. Ground 1 ..............................................................................................14
`1.
`Ground 1 combination: Harris (EX1023) + FBDIMM
`Standards (EX1027-28) ............................................................14
`Independent Claim 1 .................................................................19
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`2.
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`B.
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`C.
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`3.
`Claim 2 ......................................................................................35
`Claim 3 ......................................................................................41
`4.
`Claim 8 ......................................................................................41
`5.
`Claim 14 ....................................................................................46
`6.
`Claim 15 ....................................................................................47
`7.
`Independent Claim 23 ...............................................................50
`8.
`Ground 2 ..............................................................................................51
`1.
`Ground 2 combination: Ground 1 + Amidi (EX1024) .............52
`2.
`Claims 1-3, 15, 23 .....................................................................56
`3.
`Claim 4 ......................................................................................57
`4.
`Claim 5 ......................................................................................60
`5.
`Claim 6 ......................................................................................63
`6.
`Claim 7 ......................................................................................63
`7.
`Claims 8, 14 ..............................................................................66
`8.
`Claim 9 ......................................................................................67
`9.
`Claim 10 ....................................................................................67
`10. Claim 11 ....................................................................................68
`11. Claim 12 ....................................................................................69
`12. Claim 13 ....................................................................................69
`13. Claims 16-22, 24-30 ..................................................................70
`Ground 3 ..............................................................................................75
`1.
`Ground 3 combination: Ground 2 + Hajeck (EX1038) ............75
`2.
`Claims 1-30 ...............................................................................76
`D. Ground 4 ..............................................................................................77
`1.
`Ground 4 combination: Spiers (EX1025) + Amidi
`(EX1024) ...................................................................................78
`Independent Claim 1 .................................................................82
`Claim 2 ......................................................................................99
`Claim 3 ....................................................................................101
`Claim 4 ....................................................................................102
`Claim 5 ....................................................................................102
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`2.
`3.
`4.
`5.
`6.
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`7.
`Claim 6 ....................................................................................105
`Claim 7 ....................................................................................106
`8.
`Claim 8 ....................................................................................108
`9.
`10. Claim 9 ....................................................................................115
`11. Claim 10 ..................................................................................116
`12. Claim 11 ..................................................................................117
`13. Claim 12 ..................................................................................119
`14. Claim 13 ..................................................................................120
`15. Claim 14 ..................................................................................120
`16. Claim 15 ..................................................................................121
`17. Claims 16-30 ...........................................................................123
`Ground 5 ............................................................................................127
`1.
`Ground 5 combination: Ground 4 + Hajeck (EX1038) ..........128
`2.
`Claims 1-30 .............................................................................129
`VII. FINTIV ........................................................................................................130
`VIII. CONCLUSION ..........................................................................................130
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`E.
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`TABLE OF AUTHORITIES
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`Page(s)
`
`Cases
`Advanced Bionics, LLC v. Med-El Elektromedizinische Geräte GmbH,
`IPR2019-01469, Paper 6 (PTAB Feb. 13, 2020) (precedential) ............................ 8
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) (precedential) .....................130
`Gen. Hosp. Corp. v. Sienna Biopharms., Inc.,
`888 F.3d 1368 (Fed. Cir. 2018) ................................................. 27, 57, 64, 87, 102
`Iron Grip Barbell Co. v. USA Sports, Inc.,
`392 F.3d 1317 (Fed. Cir. 2004) ................................................. 28, 57, 64, 87, 102
`Thorne Research, Inc. v. Trustees of Dartmouth College,
`IPR2021-00491, Paper 18 (PTAB Aug. 12, 2021) ................................................ 8
`Statutes
`35 U.S.C. § 102(a) ............................................................................................ 10, 11
`35 U.S.C. § 102(b) ............................................................................................ 12, 13
`35 U.S.C. § 102(e) ...................................................................................................12
`35 U.S.C. § 103(a) ..................................................................................................... 3
`35 U.S.C. § 325(d) .................................................................................................7, 8
`Regulations
`37 C.F.R § 42.8(b)(1) ................................................................................................. 1
`37 C.F.R § 42.8(b)(2) ................................................................................................. 1
`37 C.F.R. § 42.104(a) ................................................................................................. 3
`37 C.F.R. § 42.104(b) ................................................................................................ 3
`37 C.F.R. § 42.8(b)(3) ................................................................................................ 2
`37 C.F.R. § 42.8(b)(4) ................................................................................................ 2
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
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`EXHIBIT LIST
`
`Description
`
`U.S. Patent No. 11,016,918
`
`File History of U.S. Patent No. 11,016,918
`
`Declaration of Dr. Andrew Wolfe
`
`Curriculum Vitae of Dr. Andrew Wolfe
`
`File History of U.S. Provisional Application No. 60/941,586
`
`File History of U.S. Patent Application No. 12/131,873
`
`File History of U.S. Patent Application No. 12/240,916
`
`File History of U.S. Provisional Application No. 61/512,871
`
`File History of U.S. Patent Application No. 13/559,476
`
`File History of U.S. Patent Application No. 14/489,269
`
`File History of U.S. Patent Application No. 14/840,865
`
`File History of U.S. Patent Application No. 15/934,416
`
`[Intentionally Omitted]
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 1 (PTAB
`June 20, 2014) (833 Patent IPR Petition)
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 8 (PTAB
`Dec. 16, 2014) (833 Patent Institution Decision)
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 8 (PTAB Sept. 22, 2014) (833 Patent IPR Corrected Petition)
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 13 (PTAB Mar. 13, 2015) (833 Patent Institution Decision)
`
`Exhibit #
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
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`1013
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`1014
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`1015
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`1016
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`1017
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
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`Exhibit #
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`1018
`
`1019
`
`1020
`
`Description
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 1
`(PTAB Jan. 13, 2017) (833 Patent IPR Petition)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 7
`(PTAB July 24, 2017) (833 Patent Institution Decision)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 1
`(PTAB Jan. 17, 2017) (831 Patent IPR Petition)
`
`1021
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 25
`(PTAB July 5, 2018) (831 Patent Final Written Decision)
`1022 Micron Tech., Inc. et al. v. Netlist, Inc., IPR2022-00418, Paper No. 2
`(PTAB Jan. 14, 2022) (833 Patent IPR Petition)
`
`1023
`
`U.S. Patent Application Publication No. 2006/0174140 to Harris et
`al.
`
`1024
`
`U.S. Patent No. 7,724,604 to Amidi et al.
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`U.S. Patent Application Publication No. 2006/0080515 to Spiers et
`al.
`
`JEDEC Standard, DDR2 SDRAM Specification, JESD79-2B
`(January 2005) (“JESD79-2B”)
`
`JEDEC Standard, FBDIMM: Advanced Memory Buffer (AMB),
`JESD82-20 (March 2007) (“JESD82-20”)
`
`JEDEC Standard, FBDIMM Specification: DDR2 SDRAM Fully
`Buffered DIMM (FBDIMM) Design Specification, JESD205 (March
`2007) (“JESD205”)
`
`Declaration of Julie Carlson for JESD82-20 and JESD205
`
`U.S. Patent No. 7,719,866 to Boldo
`
`PCI Local Bus Specification Revision 2.2 (1998)
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`vii
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`Description
`Exhibit #
`1032 Mohan et al., Power Electronics: Converters, Applications, and
`Design (2d ed. 1995)
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`U.S. Patent No. 7,721,130 to Prete et al.
`
`U.S. Patent No. 6,798,709 to Sim et al.
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0238536 to Hayashi et
`al.
`
`1038
`
`U.S. Patent No. 6,856,556 to Hajeck
`
`1039
`
`U.S. Patent Application Publication No. 2010/0257304 to Rajan et
`al.
`
`1040
`
`Texas Instruments, TPS51020 Datasheet (December 2003)
`
`1041
`Fairchild Semiconductor, FAN5026 Datasheet (October 2005)
`1042 Murata Power Supply Reference Guide for Xilinx FPGAs
`(September 2006)
`1043 Murata Power Supply Reference Guide for Altera FPGAs (February
`2008)
`
`1044
`
`1045
`
`1046
`
`U.S. Patent Application Publication No. 2010/0205470 to Moshayedi
`et al.
`
`JEDEC Standard, Double Data Rate (DDR) SDRAM Specification,
`JESD79 (June 2000) (“JESD79”)
`
`JEDEC Standard, DDR3 SDRAM, JESD79-3A (September 2007)
`(“JESD79-3A”)
`
`1047
`
`U.S. Patent No. 7,023,187 to Shearon et al.
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`
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`viii
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`Description
`Exhibit #
`1048 Murata, DC-DC Converter Specification (DRAFT), MPD4S014S
`Datasheet (Jan. 21, 2008)
`
`1049 Micron, NAND Flash Memory Datasheet (January 2006)
`
`1050
`
`1051
`
`1052
`
`1053
`
`1054
`
`1055
`
`1056
`
`1057
`
`1058
`
`1059
`
`1060
`
`1061
`
`1062
`
`1063
`
`1064
`
`U.S. Patent No. 7,692,938 to Petter
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0101147 to Amidi
`
`U.S. Patent No. 5,563,839 to Herdt et al.
`
`U.S. Patent No. 6,693,840 to Shimada et al.
`
`Lenk, John D., Simplified Design of Switching Power Supplies
`(1995)
`
`U.S. Patent No. 7,061,214 to Mayega et al.
`
`U.S. Patent No. 5,630,096 to Zuravleff et al.
`
`Analog Devices, ADM1066 Datasheet (2006)
`
`Alan Moloney, Power-Supply Management—Principles, Problems,
`and Parts, Analog Dialogue (May 2006)
`
`National Semiconductor, LMC6953 PCI Local Bus Power
`Supervisor Datasheet (October 1996)
`
`U.S. Patent Application Publication No. 2007/0136523 to Bonella et
`al.
`
`1065
`
`U.S. Patent Application Publication No. 2009/0034354 to Resnick
`
`
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`Exhibit #
`1066
`
`Description
`U.S. Patent No. 10,672,458 to Shaeffer et al.
`
`1067
`
`LatticeXP Family Data Sheet (March 2006)
`
`1068
`
`1069
`
`1070
`
`1071
`
`1072
`
`1073
`
`Complaint for Declaratory Judgment of Non-Infringement and
`Unenforceability; Breach of Contract, Samsung Electronics Co., Ltd.
`et al. v. Netlist, Inc., No. 1:21-cv-01453 (D. Del. filed Oct. 15, 2021)
`
`First Amended Complaint for Declaratory Judgment of Non-
`Infringement and Unenforceability; Breach of Contract, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Jan. 18, 2022)
`
`Netlist’s motion to dismiss the First Amended Complaint, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Feb. 16, 2022)
`
`Complaint in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Dec. 20, 2021)
`
`Answer in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Apr. 12, 2022)
`
`Amended Complaint in Netlist, Inc. v. Samsung Electronics Co., Ltd.
`et al., No. 2:21-cv-00463 (E.D. Tex. filed May 3, 2022)
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`CLAIM LISTING
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`Ref. #
`1.a
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`1.b
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`1.c
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`1.d
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`1.e
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`1.f
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`1.g
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`1.h
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`1.i
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`2
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`Listing of Challenged Claims
`1. A memory module comprising:
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface
`including a plurality of edge connections configured to couple power,
`data, address and control signals between the memory module and the
`host system;
`a first buck converter configured to provide a first regulated voltage
`having a first voltage amplitude;
`a second buck converter configured to provide a second regulated
`voltage having a second voltage amplitude;
`a third buck converter configured to provide a third regulated voltage
`having a third voltage amplitude;
`a converter circuit configured to provide a fourth regulated voltage
`having a fourth voltage amplitude; and
`a plurality of components coupled to the PCB, each component of the
`plurality of components coupled to one or more regulated voltages of
`the first, second, third and fourth regulated voltages, the plurality of
`components comprising:
`a plurality of synchronous dynamic random access memory (SDRAM)
`devices coupled to the first regulated voltage, and
`[1] at least one circuit coupled between a first portion of the plurality
`of edge connections and the plurality of SDRAM devices,
`[2] the at least one circuit operable to (i) receive a first plurality of
`address and control signals via the first portion of the plurality of edge
`connections, and (ii) output a second plurality of address and control
`signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated voltage
`and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`2. The memory module of claim 1, wherein the first and third buck
`converters are further configured to operate as a dual buck converter.
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`Ref. #
`3
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`4
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`5.a
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`5.b
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`6
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`7
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`8.a
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`8.b
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`9
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`10.a
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`10.b
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`
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`Listing of Challenged Claims
`3. The memory module of claim 1, wherein the first voltage amplitude
`is 1.8 volts.
`4. The memory module of claim 1, wherein the second, third, and
`fourth voltage amplitudes are 2.5 volts, 1.2 volts, and 3.3 volts,
`respectively.
`5. The memory module of claim 1, further comprising:
`a voltage monitor circuit configured to monitor a power input voltage
`received via a second portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a trigger signal in
`response to the power input voltage having a voltage amplitude that is
`greater than a first threshold voltage.
`6. The memory module of claim 5, wherein the voltage monitor circuit
`is further configured to produce the trigger signal in response to the
`power input voltage having a voltage amplitude that is less than a
`second threshold voltage.
`7. The memory module of claim 6, wherein the second threshold
`voltage corresponds to a voltage level that is ten percent less than a
`specified operating voltage.
`8. The memory module of claim 1, the plurality of components further
`comprising:
`[1] one or more registers coupled to one of the first, second, third and
`fourth regulated voltages,
`[2] the one or more registers configured to register, in response to a
`clock, the first plurality of address and control signals,
`[3] wherein the one of the first, second, third and fourth regulated
`voltages is selectively switched off to turn power off to the one or
`more registers while one or more components of the plurality of
`components are powered on.
`9. The memory module of claim 5, wherein the first threshold voltage
`corresponds to a voltage level that is ten percent greater than a
`specified operating voltage.
`The memory module of claim 5, the plurality of components further
`comprising:
`a logic element including a non-volatile memory, the non-volatile
`memory is configured to store configuration information.
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`Ref. #
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`11
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`12.a
`12.b
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`12.c
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`Listing of Challenged Claims
`11. The memory module of claim 10, wherein, in response to the
`trigger signal, the logic element writes information into the non-
`volatile memory.
`12. The memory module of claim 5, the plurality of components
`further comprising:
`a non-volatile memory; and
`a controller configured to receive the trigger signal, wherein, in
`response to the trigger signal, the controller performs a write operation
`to the non-volatile memory.
`13. The memory module of claim 5, wherein the power input voltage
`is coupled to the first, second, and third buck converters and the
`converter circuit.
`14. The memory module of claim 8, wherein, in response to
`selectively switching on the one of the first, second, third and fourth
`regulated voltages to the one or more registers, the one or more
`registers is configured to output the registered first plurality of address
`and control signals to the plurality of SDRAM devices.
`15. The memory module of claim 1, the plurality of components
`further comprising:
`a logic element including one or more integrated circuits and discrete
`electrical elements, the one or more integrated circuit including an
`internal non-volatile memory, wherein the non-volatile memory is
`configured to store configuration information.
`16.a A memory module comprising:
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface
`including a plurality of edge connections configured to couple power,
`data, address and control signals between the memory module and the
`host system;
`first, second, and third buck converters configured to receive a pre-
`regulated input voltage and to produce first, second and third regulated
`voltages, respectively;
`
`13
`
`14
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`15.a
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`15.b
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`16.b
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`16.c
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`Ref. #
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`16.d
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`16.e
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`16.f
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`17
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`18.a
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`18.b
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`19
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`20
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`21.a
`
`Listing of Challenged Claims
`[1] a converter circuit configured to reduce the pre-regulated input
`voltage to provide a fourth regulated voltage,
`[2] wherein the first, second, third and fourth regulated voltages have
`first, second, third, and fourth voltage amplitudes, respectively;
`a plurality of components coupled to the PCB, the plurality of
`components including a plurality of synchronous dynamic random
`access memory (SDRAM) devices, each component of the plurality of
`components coupled to one or more regulated voltages of the first,
`second, third and fourth regulated voltages; and
`a voltage monitor circuit configured to monitor an input voltage
`received via a first portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a signal in response to
`the input voltage having a voltage amplitude that is greater than a first
`threshold voltage.
`17. The memory module of claim 16, wherein the second and third
`buck converters are configured to operate as a dual buck converter.
`18. The memory module of claim 16, the plurality of components
`further including:
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein the controller executes a write operation in
`response to the signal.
`19. The memory module of claim 18, wherein the write operation
`includes writing data information into non-volatile memory.
`20. The memory module of claim 16, wherein the plurality of SDRAM
`devices are configured to receive at least one of the first, second, third
`and fourth regulated voltages having a voltage amplitude of 1.8 volts.
`21. The memory module of claim 16, the plurality of components
`further including:
`
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`Ref. #
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`21.b
`
`Listing of Challenged Claims
`[1] at least one circuit coupled between the interface and the plurality
`of SDRAM devices,
`[2] the at least one circuit operable to receive a first plurality of
`address and control signals via a second portion of the plurality of
`edge connections and to output a second plurality of address and
`control signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated voltage
`and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`22. The memory module of claim 16, the plurality of components
`further including:
`a logic element including an internal non-volatile memory, wherein
`the non-volatile memory is configured to store configuration
`information, wherein the configuration information is used to program
`the logic element.
`23.a A memory module comprising:
`
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface
`including a plurality of edge connections configured to couple power,
`data, address and control signals between the memory module and the
`host system;
`[1] a plurality of components coupled to the PCB, each component of
`the plurality of components coupled to one or more regulated voltages
`of first, second, third and fourth regulated voltages,
`[2] the plurality of components including a plurality of synchronous
`dynamic random access memory (SDRAM) devices and one or more
`registers, the plurality of SDRAM devices coupled to the first
`regulated voltage, the one or more registers coupled to (i) the second
`regulated voltage, (ii) a portion of the plurality of edge connections,
`and (iii) the plurality of SDRAM devices,
`[3] wherein a plurality of address and control signals are coupled to
`the one or more registers via the portion of the plurality of edge
`connections;
`first, second, and third buck converters configured to provide the first,
`second and third regulated voltages, respectively; and
`
`22.a
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`22.b
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`23.b
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`23.c
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`23.d
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`Ref. #
`23.e
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`23.f
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`23.g
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`23.h
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`24.a
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`24.b
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`25.a
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`25.b
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`26
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`27
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`28
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`29
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`Listing of Challenged Claims
`a converter circuit configured to provide the fourth regulated voltage,
`wherein the second regulated voltage is configured to be selectively
`switched on or off to the one or more registers while at least the
`plurality of SDRAM devices are powered on,
`wherein if the second regulated voltage is switched on while at least
`the plurality of SDRAM devices are powered on, the one or more
`registers are configured to couple the first plurality of address and
`control signals to the plurality of SDRAM devices, and
`wherein if the second regulated voltage is switched off while the
`plurality of SDRAM devices are powered on, the one or more registers
`are configured to decouple the plurality of SDRAM devices from the
`first plurality of address and control signals.
`24. The memory module of claim 23, further comprising:
`a voltage monitor circuit configured to monitor an input voltage
`received from the host system via the interface, the voltage monitor
`circuit configured to produce a signal in response to the input voltage
`having a voltage amplitude that is greater than a first threshold
`voltage.
`25. The memory module of claim 24, the plurality of components
`further including:
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein, in response to the signal, the controller
`executes a write operation.
`26. The memory module of claim 25, wherein the write operation
`includes writing data information to non-volatile memory.
`27. The memory module of claim 24, wherein the voltage monitor
`circuit is further configured to produce the signal in response to the
`input voltage having a voltage amplitude that is less than a second
`threshold voltage.
`28. The memory module of claim 23, wherein the second and third
`buck converters are configured to operate as a dual buck converter.
`29. The memory module of claim 23, wherein the plurality of SDRAM
`devices are configured to receive at least one of the first, second, third
`and fourth regulated voltages having a voltage amplitude of 1.8 volts.
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`30
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`Listing of Challenged Claims
`30. The memory module of claim 23, wherein the first, second, and
`third buck converters are configured to receive a pre-regulated input
`voltage and to provide the first, second and third regulated voltages,
`respectively, and wherein the converter circuit is configured to reduce
`the pre-regulated voltage input to provide the fourth regulated voltage.
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`xvii
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`I.
`
`PETITIONER’S MANDATORY NOTICES
`A. Real Parties-in-Interest (37 C.F.R. § 42.8(b)(1))
`The real parties in interest are the Petitioner, Samsung Electronics Co., Ltd.,
`
`and Samsung Semiconductor, Inc.
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`The following judicial or administrative matters would affect, or be affected
`
`by, a decision in this proceeding concerning U.S. Patent No. 11,016,918.
`
`The following proceedings are currently pending:
`
`• Samsung Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-
`
`01453 (D. Del. filed Oct. 15, 2021)
`
`• Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:21-cv-
`
`00463 (E.D. Tex. filed Dec. 20, 2021)
`
`• Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00999 (U.S.
`
`Patent No. 11,232,054)
`
`• Application No. 17/582,797
`
`The following proceeding is no longer pending:
`
`• SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692 (U.S. Patent No.
`
`8,874,831)
`
`
`
`1
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`
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`C. Lead and Back-up Counsel (37 C.F.R. § 42.8(b)(3))
`Lead Counsel is Eliot D. Williams (Reg. No. 50,822),
`
`DLSamsungNetlistIPRs@BakerBotts.com, (650) 739-7511, Baker Botts L.L.P.,
`
`1001 Page Mill Road, Building One, Suite 200, Palo Alto, CA 94304.
`
`Backup Lead Counsel are:
`
`• Theodore W. Chandler (Reg. No. 50,319),
`
`DLSamsungNetlistIPRs@BakerBotts.com, (213) 202-5702
`
`• Ferenc Pazmandi (Reg. No. 66,216),
`
`DLSamsungNetlistIPRs@BakerBotts.com, (415) 291-6255
`
`• Aashish Kapadia (Reg. No. 78,844),
`
`DLSamsungNetlistIPRs@BakerBotts.com, (512) 322-2554
`
`• Brianna L. Potter (Reg. No. 76,748),
`
`DLSamsungNetlistIPRs@BakerBotts.com, (650) 739-7556
`
`The fax number for lead and backup counsel is (650) 739-7611.
`
`Service Information (37 C.F.R. § 42.8(b)(4))
`D.
`Service information is provided in the designation of counsel above.
`
`Petitioner consents to service of all documents via electronic mail to
`
`DLSamsungNetlistIPRs@BakerBotts.com.
`
`
`
`2
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`
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`Petition for Inter Partes Review of U.S. Patent No. 11,016,918
`
`II.
`
`INTRODUCTION
`Petitioner respectfully requests trial on claims 1-30 of U.S. Patent
`
`11,016,918 (“918 Patent”) (EX1001) based on grounds not considered during
`
`prosecution.
`
`III. COMPLIANCE WITH REQUIREMENTS FOR A PETITION FOR
`INTER PARTES REVIEW
`Standing (§42.104(a))
`A.
`Petitioner certifies that the 918 Patent is available for IPR and that Petitioner
`
`is not barred or estopped from requesting an IPR challenging the 918 Patent claims
`
`on the grounds identified below.
`
`Identification of Challenge (§42.104(b))
`B.
`Petitioner challenges claims 1-30 of the 918 Patent as follows:
`
`Ground Claims Challenged 35 U.S.C. §
`1
`1-3, 8, 14-15, 23
`103(a)
`
`References
`Harris + FBDIMM Standards
`
`2
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`3
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`4
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`5
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`1-30
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`1-30
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`1-30
`
`1-30
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`103(a)
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`103(a)
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`103(a)
`
`103(a)
`
`Ground 1 + Amidi
`
`Ground 2 + Hajeck
`
`Spiers+Amidi
`
`Ground 4 + Hajeck
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`Petitioner’s prop