Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 1 of 49 PageID #: 1
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
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`
`
`Plaintiff,
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`
`
`v.
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`NETLIST, INC.
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`
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`
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`SAMSUNG ELECTRONICS CO., LTD.,
`SAMSUNG ELECTRONICS AMERICA,
`INC., SAMSUNG SEMICONDUCTOR,
`INC.
`
`
`
`
`
`
`
`
`
`
`Civil Action No.2:21-cv-463
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`JURY TRIAL DEMANDED
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`COMPLAINT
`
`Defendants.
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`
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`
`
`1.
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`Plaintiff Netlist, Inc. (“Netlist”), by its undersigned counsel, for its Complaint
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`against defendants Samsung Electronics Co., Ltd. (“SEC”), Samsung Electronics America, Inc.
`
`(“SEA”), and Samsung Semiconductor, Inc. (“SSI”) (collectively, “Samsung” or “Defendants”),
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`states as follows, with knowledge as to its own acts, and on information and belief as to the acts
`
`of others:
`
`2.
`
`This action involves three of Netlist’s patents: U.S. Patent Nos. 10,860,506 (the
`
`“’506 Patent,” Ex. 1), 10,949,339 (the “’339 Patent,” Ex. 2), and 11,016,918 (the “’918 Patent,”
`
`Ex. 3) (collectively, the “Patents-in-Suit”).
`
`
`
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`
`
`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 1
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 2 of 49 PageID #: 2
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`I.
`
`THE PARTIES
`3.
`Plaintiff Netlist is a corporation organized and existing under the laws of the State
`
`of Delaware, having a principal place of business at 111 Academy Drive, Suite 100, Irvine, CA
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`92617.
`
`4.
`
`On information and belief, SEC is a corporation organized and existing under the
`
`laws of the Republic of Korea, with its principal place of business at 129 Samsung-ro, Yeongtong-
`
`gu, Suwon, Gyeonggi, 16677, Republic of Korea. On information and belief, SEC is the
`
`worldwide parent corporation for SEA and SSI, and is responsible for the infringing activities
`
`identified in this complaint. On information and belief, SEC’s Device Solutions division is
`
`involved in the design, manufacture, use, offering for sale and/or sales of certain semiconductor
`
`products, including the Accused Instrumentalities as defined below. On information and belief,
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`SEC is also involved in the design, manufacture, and provision of products sold by SEA.
`
`5.
`
`On information and belief, SEA is a corporation organized and existing under the
`
`laws of the State of New York. On information and belief, SEA, collectively with SEC, operates
`
`the Device Solutions division, which is involved in the design, manufacture, use, offering for sale
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`and/or sales of certain semiconductor products, including the Accused Instrumentalities as defined
`
`below. Defendant SEA maintains facilities at 6625 Excellence Way, Plano, Texas 75023. SEA
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`may be served with process through its registered agent for service in Texas: CT Corporation
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`System, 1999 Bryan Street, Suite 900, Dallas, Texas 75201. SEA is a wholly owned subsidiary of
`
`SEC.
`
`6.
`
`On information and belief, SSI is a corporation organized and existing under the
`
`laws of the State of California. On information and belief, SSI, collectively with SEC, operates
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`the Device Solutions division, which is involved in the design, manufacture, use, offering for sale
`
`and/or sales of certain semiconductor products, including the Accused Instrumentalities as defined
`
`
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`- 2 -
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`
`
`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 2
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 3 of 49 PageID #: 3
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`below. Defendant SSI maintains facilities at 6625 Excellence Way, Plano, Texas 75023.
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`Defendant SSI may be served with process through its registered agent National Registered
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`Agents, Inc., 1999 Bryan St., Ste. 900, Dallas, TX 75201-3136. On information and belief, SSI is
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`a wholly owned subsidiary of SEA.
`
`7.
`
`On information and belief, Defendants have used, sold or offered to sell products
`
`and services, including the Accused Instrumentalities, in this judicial district.
`
`II.
`
`JURISDICTION AND VENUE
`8.
`Subject matter jurisdiction is based on 28 U.S.C. § 1338, in that this action arises
`
`under federal statute, the patent laws of the United States (35 U.S.C. §§ 1, et seq.).
`
`9.
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`Each Defendant is subject to this Court’s personal jurisdiction consistent with the
`
`principles of due process and/or the Texas Long Arm Statute.
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`10.
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`Personal jurisdiction exists generally over the Defendants because each Defendant
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`has sufficient minimum contacts and/or has engaged in continuous and systematic activities in the
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`forum as a result of business conducted within the State of Texas and the Eastern District of Texas.
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`Personal jurisdiction also exists over each Defendant because each, directly or through
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`subsidiaries, makes, uses, sells, offers for sale, imports, advertises, makes available, and/or
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`markets products within the State of Texas and the Eastern District of Texas that infringe one or
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`more claims of the Patents-in-Suit. Further, on information and belief, Defendants have placed or
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`contributed to placing infringing products into the stream of commerce knowing or understanding
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`that such products would be sold and used in the United States, including in this District.
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`11.
`
`Venue is proper in this Court pursuant to 28 U.S.C. §§ 1391(b) and (c) and/or
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`1400(b). For example, SEC maintains a regular and established place of business in this judicial
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`district at 6625 Excellence Way, Plano, Texas 75023 and has committed acts of infringement in
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`this judicial district. As another example, SEA maintains a regular and established place of
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`
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`- 3 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 3
`
`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 4 of 49 PageID #: 4
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`business in this judicial district at 6625 Excellence Way, Plano, Texas 75023 and has committed
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`acts of infringement in this judicial district. Venue is also proper for SSI because it maintains a
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`regular and established place of business in this judicial district at 6625 Excellence Way, Plano,
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`Texas 75023 and has committed acts of infringement in this judicial district.
`
`12.
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`Defendants have not contested proper venue in this District. See, e.g., Answer at ¶
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`10, Arbor Global Strategies LLC v. Samsung Elecs. Co., Ltd., No. 2:19-cv-333, Dkt. 43 (E.D. Tex.
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`Apr. 27, 2020); Answer at ¶ 29, Acorn Semi, LLC v. Samsung Elecs. Co., Ltd., No. 2:19-cv-347,
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`Dkt. 14 (E.D. Tex. Feb. 12, 2020).
`
`III.
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`FACTUAL ALLEGATIONS
`
`Background
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`13.
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`Since its founding in 2000, Netlist has been a leading innovator in high-
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`performance memory module technologies. Netlist designs and manufactures a wide variety of
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`high-performance products for the cloud computing, virtualization and high-performance
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`computing markets. Netlist’s technology enables users to derive useful information from vast
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`amounts of data in a shorter period of time. These capabilities will become increasingly valuable
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`as the volume of data continues to dramatically increase.
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`14.
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`Netlist has a long history of being the first to market with disruptive new products
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`such as the first load-reduced dual in-line memory module (“LR-DIMM”), HyperCloud®, based
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`on Netlist’s distributed buffer architecture later adopted by the industry for DDR4 LRDIMM.
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`Netlist was also the first to bring NAND flash to the memory channel with its NVvault®
`
`NVDIMM. These innovative products built on Netlist’s early pioneering work in areas such as
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`embedding passives into printed circuit boards to free up board real estate, doubling densities via
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`quad-rank double data rate (DDR) technology, and other off-chip technology advances that result
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`in improved performance and lower costs compared to conventional memory.
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`- 4 -
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`
`
`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 4
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 5 of 49 PageID #: 5
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`15.
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`Generally speaking, a memory module is a printed circuit board that contains,
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`among other components, a plurality of individual memory devices (such as DRAMs). The
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`memory devices are typically arranged in “ranks,” which are accessible by a processor or memory
`
`controller of the host system. A memory module is typically installed into a memory slot on a
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`computer motherboard.
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`16. Memory modules are designed for, among other things, use in servers such as those
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`supporting cloud-based computing and other data-intensive applications. The structure, function,
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`and operation of memory modules is defined, specified, and standardized by the JEDEC Solid
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`State Technology Association (“JEDEC”), the standard-setting body for the microelectronics
`
`industry. Memory modules are typically characterized by, among other things, the generation of
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`DRAM on the module (e.g., DDR5, DDR4, DDR3) and the type of module (e.g., RDIMM,
`
`LRDIMM).
`
`The ’506 Patent
`
`The Asserted Netlist Patents
`
`17.
`
`The ’506 Patent is entitled “Memory Module With Timing-Controlled Data
`
`Buffering.” Netlist owns the ’506 Patent by assignment from the listed inventors Hyun Lee and
`
`Jayesh R. Bhakta. The ’506 Patent was filed as Application No. 16/391,151 on April 22, 2019,
`
`issued as a patent on December 8, 2020, and claims priority to, among others, a utility application
`
`filed on July 27, 2013 (No. 13/952,599) and a provisional application filed on July 27, 2012 (No.
`
`61/676,883).
`
`18.
`
`Samsung had knowledge of the ’506 Patent no later than August 2, 2021 via its
`
`access to Netlist’s patent portfolio docket.
`
`19.
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`As described in the ’506 Patent, in conventional memory modules, the “distribution
`
`of control signals and a control clock signal in the memory module is subject to strict constraints”
`
`
`
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`- 5 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 5
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 6 of 49 PageID #: 6
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`to ensure that memory devices on the memory module can be properly accessed. Ex. 1 at 2:16-
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`17. For example, in some conventional memory modules, “control wires are routed so there is an
`
`equal length to each memory component, in order to eliminate variation of the timing of the control
`
`signals and the control clock signal between different memory devices in the memory modules.”
`
`Id. at 2:20-24. But as noted in the ’506 Patent, “[t]he balancing of the length of the wires to each
`
`memory devices compromises system performance, limits the number of memory devices, and
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`complicates their connections.” Id. at 2:24-27. In yet other conventional memory systems, the
`
`memory controller includes mechanisms for compensating for unbalanced wire lengths on the
`
`memory module. Id. at 2:30-32. However, with increasing memory operating speed and memory
`
`density “such leveling mechanisms are also insufficient to ensure proper timing of the control
`
`and/or data signals received and/or transmitted by the memory modules.” Id. at 2:32-36.
`
`20.
`
`The ’506 Patent discloses a memory module operable in a memory system with a
`
`memory controller that includes memory devices, a module control circuit, and a plurality of buffer
`
`circuits coupled between respective sets of data signal lines in a data bus and respective sets of the
`
`memory devices. As summarized in the Abstract, “[e]ach respective buffer circuit is configured
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`to receive the module control signals and the module clock signal, and to buffer a respective set of
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`data signals in response to the module control signals and the module clock signal. Each respective
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`buffer circuit includes a delay circuit configured to delay the respective set of data signals by an
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`amount determined based on at least one of the module control signals.” Id., Abstract.
`
`21.
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`The buffer circuits (118, highlighted below) are associated with respective groups
`
`of memory devices and are distributed across the memory module at positions corresponding to
`
`the respective groups of memory devices as illustrated in the exemplary configuration of Figure
`
`2A.
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`- 6 -
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`
`
`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 6
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 7 of 49 PageID #: 7
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`
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`’506 Patent, Figure 2A. However, because the buffer circuits—or “isolation devices”—are
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`distributed across the memory module, at high speeds of operation, the same set of module control
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`signals may reach different buffer circuits at different times across one cycle of the system clock.
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`Id. at 9:51-62 (“Because the isolation devices 118 are distributed across the memory module 110,
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`during high speed operations, it may take more than one clock cycle time of the system clock MCK
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`for the module control signals to travel along the module control signals lines 230 from the module
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`control device 116 to the farthest positioned isolation devices 118, such as isolation device ID-1
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`and isolation device ID-(n−1) in the exemplary configuration shown in FIG. 2.”). The ’506 Patent
`
`discloses an embodiment wherein “each isolation devices includes signal alignment circuits that
`
`determine, during a write operation, a time interval between a time when one or more module
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`control signals are received from the module control circuit 116 and a time when a write strobe or
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`write data signal is received from the MCH 101. This time interval is used during a subsequent
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`read operation to time the transmission of read data to the MCH 101, such that the read data follows
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`a read command by a read latency value associated with the system 100.” Id. at 10:11-21.
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`- 7 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 7
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 8 of 49 PageID #: 8
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`The ’339 Patent
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`22.
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`The ’339 Patent is entitled “Memory Module With Controlled Byte-Wise Buffers.”
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`Netlist owns the ’339 Patent by assignment from the listed inventors Hyun Lee and Jayesh R.
`
`Bhakta. The ’339 Patent was filed as Application No. 15/470,856 on March 27, 2017, issued as a
`
`patent on March 16, 2021, and claims priority to U.S. Patent Application No. 12/504,131 filed on
`
`July 16, 2009, U.S. Patent Application No. 12/761,179 filed on April 15, 2010 and U.S.
`
`Application No. 13/970,606 filed on August 20, 2013.
`
`23.
`
`Samsung had knowledge of the ’339 Patent no later than August 2, 2021 via its
`
`access to Netlist’s patent portfolio docket.
`
`24.
`
`As described in the ’339 Patent, in optimizing performance of memory subsystems
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`(e.g. memory modules) “consideration is always given to memory density, power dissipation (or
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`thermal dissipation, speed, and cost.” Ex. 2 at 2:5-7. The ’339 Patent further explains that
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`“[g]enerally, these attributes are not orthogonal to each other, meaning that optimizing one
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`attribute may detrimentally affect another attribute. For example, increasing memory density
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`typically causes higher power dissipation, slower operational speed, and higher costs.” Id. at 2:7-
`
`12. The ’339 Patent is generally directed to a memory module optimized to reduce the load
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`experienced by a system memory controller via the use of configurable data transmission circuits.
`
`25.
`
`The ’339 Patent discloses a memory module configured to communicate with a
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`memory controller that includes DDR DRAM devices arranged in multiple ranks each of the same
`
`width as the memory module, and a module controller configured to receive and register input
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`control signals for a read or write operation from the memory controller and to output registered
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`address and control signals. As summarized in the Abstract, “[t]he registered address and control
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`signals selects one of the multiple ranks to perform the read or write operation. The module
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`controller further outputs a set of module control signals in response to the input address and
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`- 8 -
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`
`
`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 8
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 9 of 49 PageID #: 9
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`control signals. The memory module further comprises a plurality of byte-wise buffers controlled
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`by the set of module control signals to actively drive respective byte-wise sections of each data
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`signal associated with the read or write operation between the memory controller and the selected
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`rank.” Id., Abstract.
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`26.
`
`Figure 3A illustrates an example of a memory subsystem consistent with
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`embodiments disclosed in the ’339 patent.
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`
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`’339 Patent, Figure 3A. As shown above, Figure 3A depicts a memory subsystem 400 including
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`memory modules 402 comprising memory devices 412, data transmission circuits 416 (highlighted
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`above), and module control circuits 430. The data transmission circuits 416 operate to reduce the
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`load experienced by the memory controller 420 to improve performance of a read or write
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`operation. Id. at 17:14-44 (“Referring again to FIG. 3A, when the memory controller 420 executes
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`read or write operations, each specific operation is targeted to a specific one of the ranks A, B, C,
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`and D of a specific memory module 402. The data transmission circuit 416 on the specifically
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`- 9 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 9
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 10 of 49 PageID #: 10
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`targeted one of the memory modules 402 functions as a bidirectional repeater/multiplexor, such
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`that it drives the data signal when connecting from the system memory controller 420 to the
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`memory devices 412. The other data transmission circuits 416 on the remaining memory modules
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`402 are disabled for the specific operation. . . . Thus, the memory controller 420, when there are
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`four four-rank memory modules, sees four load-reducing switching circuit loads, instead of sixteen
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`memory device loads. The reduced load on the memory controller 420 enhances the performance
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`and reduces the power requirements of the memory system . . . .”). In certain embodiments, “the
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`data transmission circuit 416 comprises or functions as a byte-wise buffer. In certain such
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`embodiments, each of the one or more data transmission circuits 416 has the same bit width as
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`does the associated memory devices 412 per rank to which the data transmission circuit 416 is
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`operatively coupled.” Id. at 13:31-36.
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`The ’918 Patent
`
`27.
`
`The ’918 Patent is entitled “Flash-DRAM Hybrid Memory Module.” Netlist owns
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`the ’918 Patent by assignment from the listed inventors Chi-She Chen, Jeffrey C. Solomon , Scott
`
`H. Milton, and Jayesh Bhakta. The ’918 Patent was filed as Application No. 17/138,766 on
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`December 30, 2020, issued as a patent on May 25, 2021, and claims priority to, among others, U.S.
`
`Application No. 13,559,476 filed on July 26, 2012, U.S. Application No. 12/240,916 filed on
`
`September 29, 2008, and U.S. Application No. 12/131,873 filed on June 2, 2008 as well as to two
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`provisional applications, filed on June 1, 2007 (No. 60/941,586) and July 28, 2011 (No.
`
`61/512,871).
`
`28.
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`Samsung had knowledge of the ’918 Patent no later than August 2, 2021 via its
`
`access to Netlist’s patent portfolio docket via notice of U.S. Patent Application No. 12/240,916
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`and U.S. Patent Application No. 12/131,873 on August 2, 2021.
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`
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`- 10 -
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`
`
`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 10
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 11 of 49 PageID #: 11
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`29.
`
`As summarized in the Abstract, the ’918 Patent discloses a memory module that
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`includes a printed circuit board with an interface that couples it to a host system for provision of
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`power, data, address and control signals, and additionally features “[f]irst, second, and third buck
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`converters [that] receive a pre-regulated input voltage and produce first, second and third regulated
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`voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated
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`voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or
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`more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage
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`monitor circuit monitors an input voltage and produces a signal in response to the input voltage
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`having a voltage amplitude that is greater than a threshold voltage.” Ex. 3, Abstract.
`
`30.
`
`The ’918 Patent discloses, inter alia, a power module that provides power to various
`
`components of the memory system as depicted in Figure 16, shown below.
`
`
`
`31.
`
`The ’918 Patent explains that “[t]he power module 1100 provides a plurality of
`
`voltages to the memory system 1010 comprising non-volatile and volatile memory subsystems
`
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`- 11 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 11
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 12 of 49 PageID #: 12
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`1030, 1040. The plurality of voltages comprises at least a first voltage 1102 and a second voltage
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`1104. The power module 1100 comprises an input 1106 providing a third voltage 1108 to the
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`power module 1100 and a voltage conversion element 1120 configured to provide the second
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`voltage 1104 to the memory system 1010. The power module 1100 further comprises a first power
`
`element 1130 configured to selectively provide a fourth voltage 1110 to the conversion element
`
`1120. In certain embodiments, the first power element 1130 comprises a pulse-width modulation
`
`power controller.” Id. at 28:3-15. “The conversion element 1120 can comprise one or more buck
`
`converters and/or one or more buck-boost converters.” Id. at 29:18-19.
`
`32.
`
`Relatedly, on December 10, 2021, the United States Patent and Trademark Office
`
`issued a Notice of Allowance for the pending claims of Application No. 17/138,019, a continuation
`
`of the ’918 Patent. See Ex. 4 (allowed claims of App. No. 17/138,019). Netlist intends to assert
`
`the allowed claims of App. No. 17/138,019 upon issuance against Samsung.
`
`33.
`
`The inventions of the ’918 Patent and App. No. 17/138,019 provide for the effective
`
`operation of DDR5 memory modules, by enabling, among other benefits, greater power efficiency
`
`than previous generations of DDR technology. The DDR5 standard is characterized by the use of
`
`an on-module power management system. Samsung itself notes “[t]he on-DIMM PMIC further
`
`boosts power management efficiency and power supply stability.” Ex. 12 at 5.
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`Samsung’s Infringing Activities
`
`34.
`
`Samsung is a global technology company that manufactures semiconductor
`
`memory products such as DRAM, NAND Flash and MCP (Multi-Chip Package). Samsung
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`develops, manufactures, sells and imports into the United States memory components and memory
`
`modules designed for, among other things, use in servers such as those supporting cloud-based
`
`computing and other data-intensive applications.
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`
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`- 12 -
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`
`
`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 12
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 13 of 49 PageID #: 13
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`35.
`
`Samsung was a licensee of Netlist until July 15, 2020. See Netlist Inc. v. Samsung
`
`Elecs. Co., Ltd., No. 20-cv-993, Dkt. 186 at 20-21 (C.D. Cal. Oct. 14, 2021). Immediately after
`
`Samsung’s license was deemed terminated, Samsung filed an improper declaratory judgment
`
`action in the District of Delaware concerning unrelated patents directed at different aspects of
`
`memory module technology than the patents in the present suit. See Samsung Elecs. Co., Ltd. et
`
`al v. Netlist, Inc., No. 21-cv-1453, Dkt. 1 (D. Del. Oct. 15, 2021). Netlist has moved to dismiss
`
`each count of Samsung’s declaratory judgment complaint in Delaware.
`
`36.
`
`On information and belief, Samsung makes, uses, sells, offers to sell, and/or imports
`
`within this District and elsewhere in the United States, without authority, infringing DDR4
`
`LRDIMMs, DDR5 LRDIMMs, DDR5 RDIMMs, DDR5 SODIMMs, DDR5 UDIMMs, and other
`
`products that have materially the same structures and designs in relevant parts (the “Accused
`
`Instrumentalities”).
`
`37.
`
`The accused DDR4 LRDIMMs include, without limitation, any Samsung DDR4
`
`LRDIMM products made, sold, used and/or imported into the United States by Samsung. By way
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`of non-limiting example, the accused DDR4 LRDIMMs products include, Samsung products
`
`having
`
`the
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`following part numbers: M386A4K40BB0-CRC, M386A8K40BM1-CRC,
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`M386A8K40BM2-CTD, M386A8K40BMB-CRC, M386A8K40CM2-CRC, M386A8K40CM2-
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`CTD,
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`M386A8K40CM2-CVF,
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`M386A8K40DM2-CTD,
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`M386A8K40DM2-CVF,
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`M386A8K40DM2-CWE,
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`M386AAG40AM3-CWE,
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`M386AAG40MM2-CVF,
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`M386AAG40MMB-CVF, M386AAK40B40-CUC, M386AAK40B40-CWD, M386ABG40M50-
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`CYF, M386ABG40M51-CAE, M386ABG40M5B-CYF. Further examples of Samsung’s DDR4
`
`LRDIMM products can be found via Samsung’s module-selector web page. See Module: Memory
`
`Modules
`
`For
`
`Extensive
`
`Use,
`
`Samsung,
`
`available
`
`at
`
`https://www.samsung.com/semiconductor/dram/module.
`
`
`
`
`- 13 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 13
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 14 of 49 PageID #: 14
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`38.
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`As further example, the Accused Instrumentalities include, without limitation, any
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`Samsung DDR5 LRDIMM and DDR5 RDIMM products made, sold, used and/or imported into
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`the United States by Samsung that are JEDEC-standard compliant memory modules. By way of
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`non-limiting example, the accused DDR5 LRDIMM and DDR5 RDIMM products include
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`products marketed and publicized in an October 12, 2021 Samsung Press release, as shown below.
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`
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`Ex. 5 at 1 (depiction of a Samsung DDR5 LRDIMM).
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`Id. at 3 (depiction of a Samsung DDR5 RDIMM).
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`IV.
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`FIRST CLAIM FOR RELIEF – ’506 PATENT
`39.
`Netlist re-alleges and incorporates by reference the allegations of the preceding
`
`paragraphs of this Complaint as if fully set forth herein.
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`- 14 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 14
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 15 of 49 PageID #: 15
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`40.
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`On information and belief, Samsung directly infringed and is currently infringing
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`at least one claim of the ’506 Patent by, among other things, making, using, selling, offering to
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`sell, and/or importing within this District and elsewhere in the United States, without authority,
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`the accused DDR4 LRDIMMs and other products with materially the same structures in relevant
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`parts. For example, and as shown below, the accused DDR4 LRDIMMs and other products with
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`materially the same structures in relevant parts infringe at least claim 1 of the ’506 Patent.1
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`41.
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`For example, to the extent the preamble is limiting, each of the accused DDR4
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`LRDIMMs comprise a memory module operable in a computer system to communicate with a
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`memory controller of the computer system via a memory bus including control and address (C/A)
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`signal lines and a data bus. As an example, Samsung’s website markets and contains datasheets
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`for the accused DDR4 LRDIMMs.
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`42.
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`Ex. 6 at 2 (depiction of a Samsung DDR4 LRDIMM). Each LRDIMM includes “a
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`register for enhancing clock, command and control signals” as well as data buffers for “[e]nhanced
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`
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`1 The theories set forth herein are based on Netlist’s present understanding of the Samsung
`Accused Instrumentalities. Netlist reserves the right to supplement or amend these contentions as
`permitted by the Local Rules and any Orders of the Court as discovery progresses. Further,
`Netlist’s contentions contain images and examples illustrating Netlist’s infringement theories. As
`such, the images and examples are not intended, and should not be read, as narrowing or limiting
`the scope of these contentions.
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`- 15 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 15
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 16 of 49 PageID #: 16
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`data signal.” Id. It communicates with a server’s memory controller via control and address signal
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`lines in a memory bus as well as a data bus. For example:
`
`Ex. 7 (M386AAK40B40 Datasheet) at 6.
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`- 16 -
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`
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 16
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`

`

`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 17 of 49 PageID #: 17
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`
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`Id. at 10 (red lines in original).
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`- 17 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 17
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`

`

`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 18 of 49 PageID #: 18
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`43.
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`The accused DDR4 LRDIMMs further each comprise a module board having edge
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`connections to be coupled to respective signal lines in the memory bus, as illustrated in the
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`examples below.
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`Ex. 6 at 2 (depiction of a Samsung DDR4 LRDIMM); see also Ex. 7 (M386AAK40B40 Datasheet)
`
`
`
`at 42.
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`44.
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`The accused DDR4 LRDIMMs further each comprise a module control device on
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`the module board configurable to receive input C/A signals corresponding to a memory read
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`operation via the C/A signal lines and to output registered C/A signals in response to the input C/A
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`signals and to output module control signals, as illustrated in the example below.
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`- 18 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 18
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`

`

`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 19 of 49 PageID #: 19
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`
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`
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`Ex. 7 (M386AAK40B40 Datasheet) at 10; see also id. at 42.
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`- 19 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 19
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 20 of 49 PageID #: 20
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`
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`Id. at 11-12.
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`45.
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`The accused DDR4 LRDIMMs also each include memory devices arranged in
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`multiple ranks on the module board and coupled to the module control device (e.g., RCD) via
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`module C/A signal lines that conduct the registered C/A signals, as illustrated in the examples
`
`below.
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`- 20 -
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`
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 20
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`

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`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 21 of 49 PageID #: 21
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`
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`Id. at 10; see also id. at 42.
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`46.
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`In each accused DDR4 LRDIMM’s memory devices, the registered C/A signals
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`cause a selected rank of the multiple ranks to perform the memory read operation by outputting
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`read data and read strobes associated with the memory read operation, and a first memory device
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`in the selected rank is configurable to output at least a first section of the read data and at least a
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`- 21 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 21
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`

`

`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 22 of 49 PageID #: 22
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`first read strobe. For example, each accused DDR4 LRDIMM follows the timing sequence for a
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`READ command shown below.
`
`Ex. 9 (JEDEC JESD82-32A Standard), at 14 (annotated); see also, e.g., Ex. 8 (M386A8K40BM1
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`Datasheet) at 11-12 (functional block for a representative product).
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`- 22 -
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`
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 22
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`

`

`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 23 of 49 PageID #: 23
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`
`
`Ex. 8 (M386A8K40BM1 Datasheet) at 11-12.
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`47.
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`The accused DDR4 LRDIMMs further each include data buffers on the module
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`board and coupled between the edge connections and the memory devices, wherein a respective
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`data buffer of the data buffers is coupled to at least one respective memory device in each of the
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`multiple ranks and is configurable to receive the module control signals from the module control
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`device, as illustrated below.
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`- 23 -
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 23
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`

`

`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 24 of 49 PageID #: 24
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`Ex. 6 at 2 (depiction of a Samsung DDR4 LRDIMM).
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`
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`Ex. 8 (M386A8K40BM1 Datasheet) at 11-12 (annotated to illustrate data buffers coupled
`
`between the plurality of 72-bit wide ranks and the 72-bit wide data bus).
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`- 24 -
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`
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`Samsung Electronics Co., Ltd.
`Ex. 1071, p. 24
`
`

`

`Case 2:21-cv-00463 Document 1 Filed 12/20/21 Page 25 of 49 PageID #: 25
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`48.
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`In each accused DDR4 LRDIMM, a first data buffer on the data buffers is coupled
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`to the first memory device and is configurable to, in response to one or more of the module control
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`signals: delay the first read strobe by a first predetermined amount to generate a first delayed read
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`strobe; sample the first section of the read data using the first delayed read strobe; and transmit the
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`first section of the read data to a first section of the data bus; wherein the first predetermined
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`amount is determined based at least on signals received by the first data buffer during one or more
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`previous operations. For example, the strobes MDQSO_t and MDQSO_c are delayed by a variable
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`delay circuitry and produce DQS0_t, DQS1_t and DQS0_c, DQS1_c. The predetermined amount
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`of delay is determined based on training.
`
`
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`
`
`Ex. 7 (M386AAK40B40 Datasheet) at 11-12.
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`49.
`
`On information and belief, Samsung also indirectly infringes the ’506 Patent, as
`
`provided in 35 U.S.C. § 271(b), by inducing infringement by others, such as Samsung’s customers
`
`and end users, in this District and elsewhere in the United States. For example, on information
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`- 25 -
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`Samsu