`
`
`
`LatticeXP Family Data Sheet
`
`Version 04.2, March 2006
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. Cover
`
`

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`LatticeXP Family Data Sheet
`Introduction
`
`■
`
`■
`
`December 2005
`Features
`Non-volatile, Infinitely Reconfigurable
`■
`• Instant-on – powers up in microseconds
`• No external configuration memory
`• Excellent design security, no bit stream to
`intercept
`• Reconfigure SRAM based logic in milliseconds
`• SRAM and non-volatile memory programmable
`through system configuration and JTAG ports
`Sleep Mode
`• Allows up to 1000x static current reduction
`TransFR™ Reconfiguration (TFR)
`• In-field logic update while system operates
`Extensive Density and Package Options
`• 3.1K to 19.7K LUT4s
`• 62 to 340 I/Os
`• Density migration supported
`Embedded and Distributed Memory
`• 54 Kbits to 414 Kbits sysMEM™ Embedded
`Block RAM
`• Up to 79 Kbits distributed RAM
`• Flexible memory resources:
`Distributed and block memory
`−
`
`■
`
`■
`
`Data Sheet
`
`■
`
`■
`
`■
`
`■
`
`Flexible I/O Buffer
`• Programmable sysIO™ buffer supports wide
`range of interfaces:
`LVCMOS 3.3/2.5/1.8/1.5/1.2
`−
`LVTTL
`−
`– SSTL 18 Class I
`SSTL 3/2 Class I, II
`−
`– HSTL15 Class I, III
`HSTL 18 Class I, II, III
`−
`PCI
`−
`LVDS, Bus-LVDS, LVPECL
`−
`Dedicated DDR Memory Support
`• Implements interface up to DDR333 (166MHz)
`sysCLOCK™ PLLs
`• Up to 4 analog PLLs per device
`• Clock multiply, divide and phase shifting
`System Level Support
`• IEEE Standard 1149.1 Boundary Scan, plus
`ispTRACY™ internal logic analyzer capability
`• Onboard oscillator for configuration
`• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
`power supply
`
`Table 1-1. LatticeXP Family Selection Guide
`Device
`LFXP3
`PFU/PFF Rows
`16
`PFU/PFF Columns
`24
`PFU/PFF (Total)
`384
`LUTs (K)
`3.1
`Distributed RAM (KBits)
`12
`EBR SRAM (KBits)
`54
`EBR SRAM Blocks
`6
`V
` Voltage
`1.2/1.8/2.5/3.3V
`CC
`PLLs
`2
`Max. I/O
`136
`Packages and I/O Combinations:
`100-pin TQFP (14 x 14 mm)
`144-pin TQFP (20 x 20 mm)
`208-pin PQFP (28 x 28 mm)
`256-ball fpBGA (17 x 17 mm)
`388-ball fpBGA (23 x 23 mm)
`484-ball fpBGA (23 x 23 mm)
`
`62
`100
`136
`
`
`
`
`LFXP6
`24
`30
`720
`5.8
`23
`72
`8
`1.2/1.8/2.5/3.3V
`2
`188
`
`LFXP10
`32
`38
`1216
`9.7
`39
`216
`24
`1.2/1.8/2.5/3.3V
`4
`244
`
`LFXP15
`40
`48
`1932
`15.4
`61
`324
`36
`1.2/1.8/2.5/3.3V
`4
`300
`
`LFXP20
`44
`56
`2464
`19.7
`79
`396
`44
`1.2/1.8/2.5/3.3V
`4
`340
`
`
`100
`142
`188
`
`
`
`
`
`
`188
`244
`
`
`
`
`
`188
`268
`300
`
`
`
`
`188
`268
`340
`
`© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
`or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
`www.latticesemi.com
`1-1
`Introduction_01.4
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 1-1
`
`

`

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`Lattice Semiconductor
`
`Introduction
`LatticeXP Family Data Sheet
`
`Introduction
`The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a
`single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs.
`
`The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-
`ogy. With this technology, expensive external configuration memories are not required and designs are secured
`from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.
`
`®
`The ispLEVER
` design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
`ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.
`The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
`and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-
`annotates it into the design for timing verification.
`
`Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.
`By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
`increasing their productivity.
`
`1-2
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 1-2
`
`

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`LatticeXP Family Data Sheet
`Architecture
`
`December 2005
`Architecture Overview
`The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
`spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 2-
`1.
`
`Data Sheet
`
`On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In configuration mode this non-
`volatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up,
`the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this
`technology, expensive external configuration memories are not required and designs are secured from unautho-
`rized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in
`microseconds, providing an “instant-on” capability that allows easy interfacing in many applications.
`
`There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
`without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
`tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
`are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
`arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
`side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
`three rows of PFF blocks there is a row of PFU blocks.
`
`Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
`right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
`memory blocks. They can be configured as RAM or ROM.
`
`The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
`Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
`route software tool automatically allocates these routing resources.
`
`At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
`PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
`clocks. The LatticeXP architecture provides up to four PLLs per device.
`
`Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG
`port which allows for serial or parallel device configuration. The LatticeXP devices are available for operation from
`3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system.
`
`© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
`or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
`www.latticesemi.com
`2-1
`Architecture_01.6
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-1
`
`

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`Lattice Semiconductor
`
`Figure 2-1. LatticeXP Top Level Block Diagram
`Programmable I/O Cell
`(PIC) includes sysIO
`Interface
`
`Architecture
`LatticeXP Family Data Sheet
`
`Non-volatile Memory
`
`sysCONFIG Programming
`Port (includes dedicated
`and dual use pins)
`
`sysMEM Embedded
`Block RAM (EBR)
`
`JTAG Port
`
`PFF (PFU without
`RAM)
`
`sysCLOCK PLL
`
`Programmable
`Functional Unit (PFU)
`
`PFU and PFF Blocks
`The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
`Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
`Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
`PFU to refer to both PFU and PFF blocks.
`
`Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
`tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
`
`Figure 2-2. PFU Diagram
`
`From
` Routing
`
`LUT4 &
`CARRY
`
`LUT4 &
`CARRY
`
`LUT4 &
`CARRY
`
`LUT4 &
`CARRY
`
`LUT4 &
`CARRY
`
`LUT4 &
`CARRY
`
`LUT4 &
`CARRY
`
`LUT4 &
`CARRY
`
`Slice 0
`
`Slice 1
`
`Slice 2
`
`Slice 3
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`To
` Routing
`
`2-2
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-2
`
`

`

`Lattice Semiconductor
`
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`
`
`Architecture
`LatticeXP Family Data Sheet
`
`Slice
`Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
`some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
`LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
`select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice.
`The registers in the slice can be configured for positive/negative and edge/level clocks.
`
`There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
`There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
`with each slice.
`
`Figure 2-3. Slice Diagram
`
`To / From
`Different slice / PFU Fast Carry In (FCI)
`
`Slice
`
`D
`
`FF/
`Latch
`
`D
`
`FF/
`Latch
`
`OFX1
`
`F1
`
`Q1
`
`To
` Routing
`
`OFX0
`
`F0
`
`Q0
`
`CO
`
`LUT4 &
`CARRY
`
`F
`
`SUM
`
`CI
`
`CO
`
`LUT
`Expansion
`Mux
`
`OFX0
`
`F S
`
`UM
`
`LUT4 &
`CARRY
`
`CI
`
`From
`Routing
`
`A1
`B1
`C1
`D1
`
`M1
`M0
`
`A0
`B0
`C0
`D0
`
`Control Signals
`selected and
`inverted per
`slice in routing
`
`CE
`CLK
`LSR
`
`Note: Some interslice signals
`are not shown.
`
`To / From
`Different slice / PFU Fast Carry Out (FCO)
`
`2-3
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-3
`
`

`

`Lattice Semiconductor
`
`Table 2-1. Slice Signal Descriptions
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`Architecture
`LatticeXP Family Data Sheet
`
`Type
`Function
`Data signal
`Input
`Data signal
`Input
`Multi-purpose
`Input
`Multi-purpose
`Input
`Control signal
`Input
`Control signal
`Input
`Control signal
`Input
`Inter-PFU signal
`Input
`Data signals
`Output
`Data signals
`Output
`Data signals
`Output
`Data signals
`Output
`Inter-PFU signal
`Output
`1. See Figure 2-2 for connection details.
`2. Requires two PFUs.
`
`Description
`
`Signal Names
`A0, B0, C0, D0 Inputs to LUT4
`A1, B1, C1, D1 Inputs to LUT4
`M0
`Multipurpose Input
`M1
`Multipurpose Input
`CE
`Clock Enable
`LSR
`Local Set/Reset
`CLK
`System Clock
`1
`
`FCIN
`Fast Carry In
`F0, F1
`LUT4 output register bypass signals
`Q0, Q1
`Register Outputs
`OFX0
`Output of a LUT5 MUX
`2
` MUX depending on the slice
`OFX1
`Output of a LUT6, LUT7, LUT8
`1
`FCO
`For the right most PFU the fast carry chain output
`
`Modes of Operation
`Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of
`all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
`
`Table 2-2. Slice Modes
`
`PFU Slice
`PFF Slice
`
`Logic
`LUT 4x2 or LUT 5x1
`LUT 4x2 or LUT 5x1
`
`Ripple
`2-bit Arithmetic Unit
`2-bit Arithmetic Unit
`
`RAM
`SP 16x2
`N/A
`
`ROM
`ROM 16x1 x 2
`ROM 16x1 x 2
`
`Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4
`
`can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this
`lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup
`tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.
`
`Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-
`
`lowing functions can be implemented by each Slice:
`
`• Addition 2-bit
`• Subtraction 2-bit
`• Add/Subtract 2-bit using dynamic control
`• Up counter 2-bit
`• Down counter 2-bit
`• Ripple mode multiplier building block
`• Comparator functions of A and B inputs
`- A greater-than-or-equal-to B
`- A not-equal-to B
`- A less-than-or-equal-to B
`
`Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast
`arithmetic functions to be constructed by concatenating Slices.
`
`RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.
`
`Through the combination of LUTs and Slices, a variety of different memories can be constructed.
`
`2-4
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-4
`
`

`

`Lattice Semiconductor
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`Architecture
`LatticeXP Family Data Sheet
`
`The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
`ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
`shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the dis-
`tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions
`as the read-write port. The other companion Slice supports the read-only port. For more information on RAM mode
`in LatticeXP devices, please see details of additional technical documentation at the end of this data sheet.
`
`Table 2-3. Number of Slices Required for Implementing Distributed RAM
`
`DPR16x2
`SPR16x2
`2
`1
`Number of Slices
`Note: SPR = Single Port RAM, DPR = Dual Port RAM
`
`Figure 2-4. Distributed Memory Primitives
`
`SPR16x2
`
`DPR16x2
`
`WAD0
`WAD1
`WAD2
`WAD3
`
`DI0
`DI1
`WCK
`WRE
`
`RAD0
`RAD1
`RAD2
`RAD3
`
`RDO0
`RDO1
`WDO0
`WDO1
`
`AD0
`AD1
`AD2
`AD3
`
`DI0
`DI1
`WRE
`CK
`
`AD0
`AD1
`AD2
`AD3
`
`DO0
`
`DO1
`
`DO0
`
`ROM16x1
`
`ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
`
`accomplished through the programming interface during configuration.
`
`PFU Modes of Operation
`Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
`functionality possible at the PFU level.
`
`2-5
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-5
`
`

`

`Lattice Semiconductor
`
`Table 2-4. PFU Modes of Operation
`
`
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`Architecture
`LatticeXP Family Data Sheet
`
`Ripple
`
`2-bit Add x 4
`
`2-bit Sub x 4
`
`Logic
`LUT 4x8 or
`MUX 2x1 x 8
`LUT 5x4 or
`MUX 4x1 x 4
`LUT 6x 2 or
`MUX 8x1 x 2
`LUT 7x1 or
`MUX 16x1 x 1
`1. These modes are not available in PFF blocks
`
`2-bit Counter x 4
`
`2-bit Comp x 4
`
`1
`RAM
`SPR16x2 x 4
`DPR16x2 x 2
`SPR16x4 x 2
`DPR16x4 x 1
`
`ROM
`
`ROM16x1 x 8
`
`ROM16x2 x 4
`
`SPR16x8 x 1
`
`ROM16x4 x 2
`
`ROM16x8 x 1
`
`Routing
`There are many resources provided in the LatticeXP devices to route signals individually or as buses with related
`control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
`ments.
`
`The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
`The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. The
`x2 and x6 resources are buffered allowing both short and long connections routing between PFUs.
`
`The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
`place and route tool is completely automatic, although an interactive routing editor is available to optimize the
`design.
`Clock Distribution Network
`The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
`through the chip via a clock distribution system.
`
`Primary Clock Sources
`LatticeXP devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. Lat-
`ticeXP devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four
`dedicated clock inputs, one on each side of the device. Figure 2-5 shows the 20 primary clock sources.
`
`2-6
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-6
`
`

`

`Lattice Semiconductor
`
`Figure 2-5. Primary Clock Sources
`From Routing
`
`Clock Input
`
`From Routing
`
`
`
`
`
`
`
`
`
`Architecture
`LatticeXP Family Data Sheet
`
`PLL Input
`
`PLL
`
`PLL
`
`PLL Input
`
`Clock Input
`
`20 Primary Clock Sources
`To Quadrant Clock Selection
`
`Clock Input
`
`PLL Input
`
`PLL
`
`PLL
`
`PLL Input
`
`From Routing
`
`Clock Input
`
`From Routing
`
`Note: Smaller devices have two PLLs.
`
`Secondary Clock Sources
`LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at
`every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary
`clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6.
`
`2-7
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-7
`
`

`

`
`
`Architecture
`LatticeXP Family Data Sheet
`
`
`
`
`
`
`
`
`
`Lattice Semiconductor
`
`Figure 2-6. Secondary Clock Sources
`
`From
`Routing
`
`From
`Routing
`
`Clock
`Input
`
`From
`Routing
`
`From
`Routing
`
`20 Secondary Clock Sources
`To Quadrant Clock Selection
`
`From Routing
`
`From Routing
`
`Clock Input
`
`From Routing
`
`From Routing
`
`From Routing
`
`From Routing
`
`Clock Input
`
`From Routing
`
`From Routing
`
`From
`Routing
`
`From
`Routing
`
`Clock
`Input
`
`From
`Routing
`
`From
`Routing
`
`Clock Routing
`The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
`work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
`clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
`8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
`9.
`
`Figure 2-7. Per Quadrant Primary Clock Selection
`
`20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
`
`DCS2
`
`DCS2
`
`4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
`
`1. Smaller devices have fewer PLL related lines.
`2. Dynamic clock select.
`
`2-8
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-8
`
`

`

`Lattice Semiconductor
`
`Figure 2-8. Per Quadrant Secondary Clock Selection
`
`
`
`Architecture
`LatticeXP Family Data Sheet
`
`
`
`
`
`
`
`
`
`
`20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
`
`4 Secondary Clocks per Quadrant
`
`Figure 2-9. Slice Clock Selection
`
`Primary Clock
`
`Secondary Clock
`Routing
`GND
`
`Clock to Each Slice
`
`sysCLOCK Phase Locked Loops (PLLs)
`The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
`nals to the feedback divider: from CLKOP (PLL internal), from clock net (CLKOP or CLKOS) or from a user clock
`(PIN or logic). There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-10
`shows the sysCLOCK PLL diagram.
`
`The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
`the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
`grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
` parameter has been satisfied. Additionally, the phase and duty cycle block
`adjustment and not relock until the t
`LOCK
`allows the user to adjust the phase and duty cycle of the CLKOS output.
`
`The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
`with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
`is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
`scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
`quency range. The secondary divider is used to derive lower frequency outputs.
`
`2-9
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-9
`
`

`

`Lattice Semiconductor
`
`Figure 2-10. PLL Diagram
`
`Dynamic Delay Adjustment
`
`
`
`
`
`
`
`Architecture
`LatticeXP Family Data Sheet
`
`
`
`RST
`
`CLKI
`(from routing or
`external pin)
`
`Input Clock
`Divider
`(CLKI)
`
`Delay
`Adjust
`
`Voltage
`Controlled
`VCO
`Oscillator
`
`Post Scalar
`Divider
`(CLKOP)
`
`Phase/Duty
`Select
`
`Feedback
`Divider
`(CLKFB)
`
`CLKFB
`from CLKOP
`(PLL internal),
`from clock net
`(CLKOP) or
`from a user
`clock (PIN or logic)
`
`Secondary
`Clock
`Divider
`(CLKOK)
`
`LOCK
`
`CLKOS
`
`CLKOP
`
`CLKOK
`
`Figure 2-11 shows the available macros for the PLL. Table 2-11 provides signal description of the PLL Block.
`
`Figure 2-11. PLL Primitive
`
`CLKI
`CLKFB
`
`EPLLB
`
`CLKOP
`LOCK
`
`RST
`
`CLKI
`
`CLKFB
`
`CLKOP
`
`CLKOS
`
`CLKOK
`
`LOCK
`
`DDAOZR
`
`DDAOLAG
`
`DDAODEL[2:0]
`
`DDA MODE
`
`EHXPLLB
`
`DDAIZR
`
`DDAILAG
`
`DDAIDEL[2:0]
`
`Description
`
`Table 2-5. PLL Signal Descriptions
`Signal
`I/O
`I
`I
`
`CLKI
`
`CLKFB
`
`RST
`CLKOS
`CLKOP
`CLKOK
`LOCK
`DDAMODE
`DDAIZR
`DDAILAG
`DDAIDEL[2:0]
`DDAOZR
`DDAOLAG
`DDAODEL[2:0]
`
`I
`O
`O
`O
`O
`I
`I
`I
`I
`O
`O
`O
`
`Clock input from external pin or routing
`PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
`(PIN or logic)
`“1” to reset input clock divider
`PLL output clock to clock tree (phase shifted/duty cycle changed)
`PLL output clock to clock tree (No phase shift)
`PLL output to clock tree through secondary clock divider
`“1” indicates PLL LOCK to CLKI
`Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)
`Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
`Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
`Dynamic Delay Input
`Dynamic Delay Zero Output
`Dynamic Delay Lag/Lead Output
`Dynamic Delay Output
`
`2-10
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-10
`
`

`

`Lattice Semiconductor
`
`
`
`
`
`
`
`
`
`
`
`
`
`Architecture
`LatticeXP Family Data Sheet
`
`For more information on the PLL, please see details of additional technical documentation at the end of this data
`sheet.
`Dynamic Clock Select (DCS)
`The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
`outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
`toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates
`the DCS Block Macro.
`
`Figure 2-12. DCS Block Primitive
`
`CLK0
`CLK1
`SEL
`
`DCS
`
`DCSOUT
`
`Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
`other modes. For more information on the DCS, please see details of additional technical documentation at the end
`of this data sheet.
`
`Figure 2-13. DCS Waveforms
`
`CLK0
`
`CLK1
`
`SEL
`
`DCSOUT
`
`sysMEM Memory
`The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a
`9-Kbit RAM, with dedicated input and output registers.
`
`sysMEM Memory Block
`The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
`a variety of depths and widths as shown in Table 2-6.
`
`2-11
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-11
`
`

`

`Lattice Semiconductor
`
`Table 2-6. sysMEM Block Configurations
`
`
`Architecture
`LatticeXP Family Data Sheet
`
`
`
`
`
`
`
`
`
`
`
`
`
`Memory Mode
`
`Single Port
`
`True Dual Port
`
`Pseudo Dual Port
`
`Configurations
` 8,192 x 1
` 4,096 x 2
` 2,048 x 4
` 1,024 x 9
` 512 x 18
`256 x 36
` 8,192 x 1
` 4,096 x 2
` 2,048 x 4
` 1,024 x 9
`512 x 18
` 8,192 x 1
` 4,096 x 2
` 2,048 x 4
` 1,024 x 9
`512 x 18
`256 x 36
`
`Bus Size Matching
`All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
`word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
`each port varies, this mapping scheme applies to each port.
`
`RAM Initialization and ROM Operation
`If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
`during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
`ROM.
`
`Memory Cascading
`Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
`cascade memory transparently, based on specific design inputs.
`
`Single, Dual and Pseudo-Dual Port Modes
`Figure 2-14 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
`modes the input data and address for the ports are registered at the input of the memory array. The output data of
`the memory is optionally registered at the output.
`
`2-12
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-12
`
`

`

`Lattice Semiconductor
`
`Figure 2-14. sysMEM Memory Primitives
`
`Architecture
`LatticeXP Family Data Sheet
`
`AD[12:0]
`DI[35:0]
`CLK
`CE
`RST
`WE
`CS[2:0]
`
`AD[12:0]
`CLK
`CE
`RST
`CS[2:0]
`
`EBR
`
`DO[35:0]
`
`ADA[12:0]
`DIA[17:0]
`CLKA
`CEA
`RSTA
`WEA
`CSA[2:0]
`DOA[17:0]
`
`EBR
`
`ADB[12:0]
`DIB[17:0]
`CEB
`CLKB
`RSTB
`WEB
`CSB[2:0]
`DOB[17:0]
`
`Single Port RAM
`
`True Dual Port RAM
`
`DO[35:0]
`
`ADW[12:0]
`DI[35:0]
`CLKW
`CEW
`WE
`RST
`CS[2:0]
`
`EBR
`
`ADR[12:0]
`
`DO[35:0]
`
`CER
`CLKR
`
`Pseudo-Dual Port RAM
`
`EBR
`
`ROM
`
`The EBR memory supports three forms of write behavior for single port or dual port operation:
`
`1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
`address) does not appear on the output. This mode is supported for all data widths.
`
`2. Write Through - a copy of the input data appears at the output of the same port during a write cycle. This
`mode is supported for all data widths.
`
`3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
`This mode is supported for x9, x18 and x36 data widths.
`
`2-13
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-13
`
`

`

`Lattice Semiconductor
`
`Architecture
`LatticeXP Family Data Sheet
`
`Memory Core Reset
`The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
`nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-
`tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
`ports are as shown in Figure 2-15.
`
`Figure 2-15. Memory Core Reset
`
`Memory Core
`
`QSETD
`
`LCLR
`
`Output Data
` Latches
`QSETD
`
`LCLR
`
`Port A[17:0]
`
`Port B[17:0]
`
`RSTA
`
`RSTB
`
`GSRN
`
`Programmable Disable
`
`For further information on sysMEM EBR block, see the details of additional technical documentation at the end of
`this data sheet.
`
`2-14
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-14
`
`

`

`Lattice Semiconductor
`
`Architecture
`LatticeXP Family Data Sheet
`
`Programmable I/O Cells (PICs)
`Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
`shown in Figure 2-16. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
`buffer, and receives input from the buffer.
`
`Figure 2-16. PIC Diagram
`
`TD
`OPOS1
`ONEG1
`
`OPOS0
`ONEG0
`
`INCK
`INDD
`INFF
`IPOS0
`IPOS1
`
`CLK
`CE
`LSR
`GSRN
`DQS
`DDRCLKPOL
`
`Control
`Muxes
`CLKO
`CEO
`LSR
`GSR
`CLKI
`CEI
`
`PIO A
`
`TD
`D0
`D1
`DDRCLK
`
`IOLT0
`
`Tristate
`DO
`Register Block
`(2 Flip Flops)
`
`D0
`D1
`DDRCLK
`
`IOLD0
`
`Output
`Register Block
`(2 Flip Flops)
`
`INCK
`INDD
`INFF
`IPOS0
`IPOS1
`
`DI
`
`Input
`Register Block
`(5 Flip Flops)
`
`PADA
`"T"
`
`sysIO
`Buffer
`
`PIO B
`
`PADB “C”
`
`In the LatticeXP family, seven PIOs or four (3.5) PICs are grouped together to provide two LVDS differential pairs,
`one PIC pair and one single I/O, as shown in Figure 2-17.
`
`Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”). The PAD Labels “T” and
`“C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be configured as
`LVDS transmit/receive pairs.
`
`One of every 14 PIOs (a group of 8 PICs) contains a delay element to facilitate the generation of DQS signals as
`shown in Figure 2-18. The DQS signal feeds the DQS bus which spans the set of 13 PIOs (8 PICs). The DQS sig-
`nal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is
`designed for memories that support one DQS strobe per eight bits of data.
`
`The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
`tional detail is provided in the Signal Descriptions table in this data sheet.
`
`2-15
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-15
`
`

`

`Lattice Semiconductor
`
`Figure 2-17. Group of Seven PIOs
`
`Four PICs
`
`Figure 2-18. DQS Routing
`
`DQS
`
`Architecture
`LatticeXP Family Data Sheet
`
` One PIO Pair
`
`PIO A
`PIO B
`
`PIO A
`PIO B
`
`PIO A
`
`PIO B
`PIO A
`
`PIO A
`PIO B
`
`PIO A
`PIO B
`
`PIO A
`PIO B
`
`PIO A
`
`PIO B
`
`PIO A
`
`PIO B
`
`PIO A
`PIO B
`
`PIO A
`PIO B
`
`PADA “T”
`LVDS Pair
`PADB “C”
`
`PADA “T”
`
`PADB “C”
`
`PADA “T”
`LVDS Pair
`PADB “C”
`
`PADA “T”
`
`PADA “T”
`LVDS Pair
`PADB “C”
`
`PADA “T”
`
`PADB “C”
`
`PADA “T”
`LVDS Pair
`PADB “C”
`
`PADA “T”
`
`sysIO
`Buffer
`
`Delay
`
`PADB “C”
`
`Assigned DQS Pin
`
`PADA “T”
`
`LVDS Pair
`
`PADB “C”
`
`PADA “T”
`
`PADB “C”
`
`PADA “T”
`LVDS Pair
`PADB “C”
`
`PIO
`The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
`block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
`with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
`nals are also included in these blocks.
`
`Input Register Block
`The input register block contains delay elements and registers that can be used to condition signals before they are
`passed to the device core. Figure 2-19 shows the diagram of the input register block.
`
`Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
`bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
`
`2-16
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-16
`
`

`

`Lattice Semiconductor
`
`Architecture
`LatticeXP Family Data Sheet
`
`in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
`passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time require-
`ment when using a global clock.
`
`The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
`registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
`to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
`These two data streams are synchronized with the system clock before entering the core. Further discussion on
`this topic is in the DDR Memory section of this data sheet.
`
`Figure 2-20 shows the input register waveforms for DDR operation and Figure 2-21 shows the design tool primi-
`tives. The SDR/SYNC registers have reset and clock enable available.
`
`The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
`quate timing when data is transferred from the DQS to the system clock domain. For further discussion of this topic,
`see the DDR memory section of this data sheet.
`
`Figure 2-19. Input Register Diagram
`
`DI
`(From sysIO
`Buffer)
`
`Delay Block
`
`Fixed Delay
`
`DQS Delayed
`(From DQS
`Bus)
`
`CLK0
`(From Routing)
`
`DDRCLKPOL
`(From DDR Polarity
`Control Bus)
`
`INCK
`
`INDD
`
`To Routing
`
`IPOS0
`
`IPOS1
`
`DDR Registers
`
`SDR & Sync
`Registers
`
`D
`
`Q
`
`D-Type
`
`D1
`
`D
`
`Q
`
`D-Type
`
`D
`
`Q
`
`D-Type
`
`D0
`
`D2
`
`Q
`D
`D-Type
`/LATCH
`
`Q
`D
`D-Type
`/LATCH
`
`2-17
`
`Samsung Electronics Co., Ltd.
`Ex. 1067, p. 2-17
`
`

`

`Lattice Semiconductor
`
`Figure 2-20. Input Register DDR Waveforms
`
`Architecture
`LatticeXP Family Data Sheet
`
`DI
`(In DDR Mode)
`
`A
`
`B
`
`C
`
`D
`
`E
`
`F
`
`DQS
`
`DQS
`Delayed
`
`D0
`
`D2
`
`Figure 2-21. INDDRXB Primitive
`
`B
`
`A
`
`D
`
`C
`
`D
`ECLK
`LSR
`SCLK
`CE
`DDRCLKPOL
`
`IDDRXB
`
`QA
`
`QB
`
`Output Register Block
`The output register block provides the ability to register signals from the core of the device before they are passed
`to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for
`DDR operation. Figure 2-22 shows the diagram of the Output Register Block.
`
`In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
`type or as a latch. In DDR mode, ONEG0 is fed into one register on