JEDEC
`STANDARD
`
`DDR3 SDRAM Specification
`
`JESD79-3A
`(Revision of JESD79-3)
`
`September 2007
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Samsung Electronics Co., Ltd.
`Ex. 1046, p. Cover
`
`

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`NOTICE
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. Notice
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. Copyright
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`

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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. Blank
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. Blank
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`

`

`JEDEC Standard No. 79-3A
`
`Contents
`1 Scope..........................................................................................................................................1
`2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
`2.1 DDR3 SDRAM x4 Ballout using MO-207 (Top view: see balls through package) ...... 3
`2.2 DDR3 SDRAM x8 Ballout using MO-207 (Top view: see balls through package) ..... 4
`2.3 DDR3 SDRAM x16 Ballout using MO-207 (Top view: see balls through package)..... 5
`2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207 (Top view: see balls through
`package).............................................................................................. 6
`2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207 (Top view: see balls through
`package).............................................................................................. 7
`2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207 (Top view: see balls through
`package).............................................................................................. 8
`2.7 Pinout Description..............................................................................................................9
`2.8 DDR3 SDRAM Addressing.............................................................................................11
`2.8.1 512Mb .....................................................................................................................11
`2.8.2 1Gb ...........................................................................................................................11
`2.8.3 2Gb ..........................................................................................................................11
`2.8.4 4Gb ..........................................................................................................................11
`2.8.5 8Gb ..........................................................................................................................12
`3 Functional Description.............................................................................................................13
`3.1 Simplified State Diagram.................................................................................................13
`3.2 Basic Functionality...........................................................................................................14
`3.3 RESET and Initialization Procedure ................................................................................15
`3.3.1 Power-up Initialization Sequence.............................................................................15
`3.3.2 Reset Initialization with Stable Power .....................................................................17
`3.4 Register Definition ...........................................................................................................18
`3.4.1 Programming the Mode Registers............................................................................18
`3.4.2 Mode Register MR0 .................................................................................................18
`3.4.3 Mode Register MR1 .................................................................................................22
`3.4.4 Mode Register MR2 .................................................................................................25
`3.4.5 Mode Register MR3 .................................................................................................27
`4 DDR3 SDRAM Command Description and Operation...........................................................29
`4.1 Command Truth Table .....................................................................................................29
`4.2 CKE Truth Table..............................................................................................................31
`4.3 No OPeration (NOP) Command ......................................................................................32
`4.4 Deselect Command ..........................................................................................................32
`4.5 DLL-off Mode..................................................................................................................33
`4.6 DLL on/off switching procedure......................................................................................34
`4.6.1 DLL “on” to DLL “off” Procedure ..........................................................................34
`4.6.2 DLL “off” to DLL “on” Procedure ..........................................................................35
`4.7 Input clock frequency change ..........................................................................................36
`4.8 Write Leveling .................................................................................................................38
`4.8.1 DRAM setting for write leveling & DRAM termination function in that mode......38
`4.8.2 Procedure Description ..............................................................................................39
`4.8.3 Write Leveling Mode Exit........................................................................................41
`4.9 Extended Temperature Usage ..........................................................................................42
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`i
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. i
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`

`

`JEDEC Standard No. 79-3A
`
`Contents
`
`4.9.1 Self-Refresh Temperature Range - SRT ..................................................................42
`4.10 Multi Purpose Register...................................................................................................44
`4.10.1 MPR Functional Description..................................................................................45
`4.10.2 MPR Register Address Definition..........................................................................46
`4.10.3 Relevant Timing Parameters ..................................................................................46
`4.10.4 Protocol Example ...................................................................................................46
`4.11 ACTIVE Command .......................................................................................................51
`4.12 PRECHARGE Command ..............................................................................................51
`4.13 READ Operation............................................................................................................52
`4.13.1 READ Burst Operation ..........................................................................................52
`4.13.2 READ Timing Definitions .....................................................................................53
`4.14 WRITE Operation ..........................................................................................................62
`4.14.1 DDR3 Burst Operation...........................................................................................62
`4.14.2 WRITE Timing Violations.....................................................................................62
`4.14.3 tWPRE Calculation ................................................................................................64
`4.14.4 tWPST Calculation.................................................................................................64
`4.15 Self-Refresh Operation...................................................................................................70
`4.16 Power-Down Modes.......................................................................................................72
`4.16.1 Power-Down Entry and Exit ..................................................................................72
`4.16.2 Power-Down clarifications - Case 1.......................................................................77
`4.16.3 Power-Down clarifications - Case 2.......................................................................78
`4.16.4 Power-Down clarifications - Case 3.......................................................................79
`5 On-Die Termination (ODT).....................................................................................................80
`5.1 ODT Mode Register and ODT Truth Table.....................................................................80
`5.2 Synchronous ODT Mode .................................................................................................81
`5.2.1 ODT Latency and Posted ODT ................................................................................81
`5.2.2 Timing Parameters ...................................................................................................81
`5.2.3 ODT during Reads....................................................................................................83
`5.3 Dynamic ODT..................................................................................................................85
`5.3.1 Functional Description: ............................................................................................85
`5.3.2 ODT Timing Diagrams ............................................................................................86
`5.4 Asynchronous ODT Mode ...............................................................................................91
`5.4.1 Synchronous to Asynchronous ODT Mode Transitions ..........................................92
`5.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry 92
`5.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit ..93
`5.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low
`periods.......................................................................................................................94
`5.5 ZQ Calibration Commands ..............................................................................................96
`5.5.1 ZQ Calibration Description ......................................................................................96
`5.5.2 ZQ Calibration Timing.............................................................................................97
`5.5.3 ZQ External Resistor Value, Tolerance, and Capacitive loading.............................97
`6 Absolute Maximum Ratings ....................................................................................................98
`6.1 Absolute Maximum DC Ratings......................................................................................98
`6.2 DRAM Component Operating Temperature Range ........................................................99
`7 AC & DC Operating Conditions............................................................................................100
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`ii
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. ii
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`

`

`JEDEC Standard No. 79-3A
`
`Contents
`7.1 Recommended DC Operating Conditions......................................................................100
`8 AC and DC Input Measurement Levels.................................................................................101
`8.1 AC and DC Logic Input Levels for Single-Ended Signals ............................................101
`8.2 AC and DC Logic Input Levels for Differential Signals ...............................................103
`8.2.1 Differential signal definition ..................................................................................103
`8.2.2 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)104
`8.2.3 Single-ended requirements for differential signals ................................................104
`8.3 Differential Input Cross Point Voltage ..........................................................................106
`8.4 Slew Rate Definitions for Single Ended Input Signals ..................................................107
`8.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) ..............107
`8.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) ...............107
`8.5 Slew Rate Definitions for Differential Input Signals.....................................................108
`9 AC and DC Output Measurement Levels ..............................................................................109
`9.1 Single Ended AC and DC Output Levels.......................................................................109
`9.2 Differential AC and DC Output Levels .........................................................................109
`9.3 Single Ended Output Slew Rate.....................................................................................110
`9.4 Differential Output Slew Rate........................................................................................111
`9.5 Reference Load for AC Timing and Output Slew Rate .................................................112
`9.6 Overshoot and Undershoot Specifications .....................................................................113
`9.6.1 Address and Control Overshoot and Undershoot Specifications ...........................113
`9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ............114
`9.7 34 ohm Output Driver DC Electrical Characteristics ....................................................115
`9.7.1 Output Driver Temperature and Voltage sensitivity ..............................................117
`9.8 On-Die Termination (ODT) Levels and I-V Characteristics .........................................118
`9.8.1 On-Die Termination (ODT) Levels and I-V Characteristics..................................118
`9.8.2 ODT DC Electrical Characteristics ........................................................................119
`9.8.3 ODT Temperature and Voltage sensitivity ............................................................122
`9.9 ODT Timing Definitions................................................................................................123
`9.9.1 Test Load for ODT Timings...................................................................................123
`9.9.2 ODT Timing Definitions ........................................................................................123
`10 IDD Specification Parameters and Test Conditions ............................................................127
`10.1 IDD Measurement Conditions .....................................................................................127
`10.2 IDD Specifications .......................................................................................................139
`11 Input/Output Capacitance ....................................................................................................141
`11.1 Input/Output Capacitance.............................................................................................141
`12 Electrical Characteristics & AC Timing for DDR3-800 to DDR3-1600.............................142
`12.1 Clock Specification ......................................................................................................142
`12.1.1 Definition for tCK(avg)........................................................................................142
`12.1.2 Definition for tCK(abs) ........................................................................................142
`12.1.3 Definition for tCH(avg) and tCL(avg) .................................................................142
`12.1.4 Definition for tJIT(per) and tJIT(per,lck).............................................................142
`12.1.5 Definition for tJIT(cc) and tJIT(cc,lck)................................................................143
`12.1.6 Definition for tERR(nper) ....................................................................................143
`12.2 Refresh parameters by device density..........................................................................143
`12.3 Standard Speed Bins ....................................................................................................144
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`iii
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. iii
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`

`

`JEDEC Standard No. 79-3A
`
`Contents
`
`12.3.1 Speed Bin Table Notes .........................................................................................148
`13 Electrical Characteristics and AC Timing ...........................................................................149
`13.1 Jitter Notes ...................................................................................................................156
`13.2 Timing Parameter Notes ..............................................................................................157
`13.3 Address / Command Setup, Hold and Derating ...........................................................159
`13.4 Data Setup, Hold and Slew Rate Derating ...................................................................166
`
`iv
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. iv
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`

`

`JEDEC Standard No. 79-3A
`
`List of Figures
`Figure 1 —Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`Figure 2 —Reset and Initialization Sequence at Power-on Ramping. . . . . . . . . . . . . . . . . . . . . . 16
`Figure 3 —Reset Procedure at Power Stable Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`Figure 4 —tMRD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
`Figure 5 —tMOD Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
`Figure 6 —MR0 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`Figure 7 —MR1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
`Figure 8 —MR2 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`Figure 9 —MR3 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`Figure 10 —DLL-off mode READ Timing Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
`Figure 11 — DLL Switch Sequence from DLL-on to DLL-off . . . . . . . . . . . . . . . . . . . . . . . . . . 34
`Figure 12 —DLL Switch Sequence from DLL Off to DLL On . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`Figure 13 —Change Frequency during Precharge Power-down . . . . . . . . . . . . . . . . . . . . . . . . . 37
`Figure 14 —Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
`Figure 15 —Timing details of Write leveling sequence [DQS - DQS# is capturing CK - CK# low
`at T1 and CK - CK# high at T2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
`Figure 16 —Timing details of Write leveling exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
`Figure 17 —MPR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
`Figure 18 —MPR Readout of predefined pattern, BL8 fixed burst order, single readout . . . . . . 47
`Figure 19 —MPR Readout of predefined pattern, BL8 fixed burst order, back-to-back readout 48
`Figure 20 —MPR Readout predefined pattern, BC4, lower nibble then upper nibble. . . . . . . . . 49
`Figure 21 —MPR Readout of predefined pattern, BC4, upper nibble then lower nibble . . . . . . 50
`Figure 22 —READ Burst Operation RL = 5 (AL = 0, CL = 5, BL8). . . . . . . . . . . . . . . . . . . . . . 52
`Figure 23 —READ Burst Operation RL = 9 (AL = 4, CL = 5, BL8). . . . . . . . . . . . . . . . . . . . . . 52
`Figure 24 —READ Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`Figure 25 —Clock to Data Strobe Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
`Figure 26 —Data Strobe to Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
`Figure 27 —tLZ and tHZ method for calculating transitions and endpoints . . . . . . . . . . . . . . . . 56
`Figure 28 —Method for calculating tRPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . . 57
`Figure 29 —Method for calculating tRPST transitions and endpoints. . . . . . . . . . . . . . . . . . . . . 57
`Figure 30 —READ (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Figure 31 —READ (BC4) to READ (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Figure 32 —READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`Figure 33 —READ (BC4) to WRITE (BC4) OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`Figure 34 —READ (BL8) to READ (BC4) OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`Figure 35 —READ (BC4) to READ (BL8) OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`Figure 36 —READ (BC4) to WRITE (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`Figure 37 —READ (BL8) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`Figure 38 —Write Timing Definition and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Figure 39 —Method for calculating tWPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . . 64
`Figure 40 —Method for calculating tWPST transitions and endpoints . . . . . . . . . . . . . . . . . . . . 64
`Figure 41 —WRITE Burst Operation WL = 5 (AL = 0, CWL = 5, BL8) . . . . . . . . . . . . . . . . . . 65
`Figure 42 —WRITE Burst Operation WL = 9 (AL = CL-1, CWL = 5, BL8) . . . . . . . . . . . . . . . 65
`Figure 43 —WRITE (BC4) to READ (BC4) Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`Figure 44 —WRITE (BC4) to PRECHARGE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`Figure 45 —WRITE (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`Figure 46 —WRITE (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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`v
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`Samsung Electronics Co., Ltd.
`Ex. 1046, p. v
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`

`

`JEDEC Standard No. 79-3A
`
`List of Figures
`
`Figure 47 —WRITE (BL8) to READ (BC4/BL8) OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`Figure 48 —WRITE (BC4) to READ (BC4/BL8) OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`Figure 49 —WRITE (BL8) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`Figure 50 —WRITE (BC4) to WRITE (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`Figure 51 —Self-Refresh Entry/Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
`Figure 52 —Active Power-Down Entry and Exit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 73
`Figure 53 —Power-Down Entry after Read and Read with Auto Precharge . . . . . . . . . . . . . . . . 73
`Figure 54 —Power-Down Entry after Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . 74
`Figure 55 —Power-Down Entry after Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`Figure 56 —Precharge Power-Down (Fast Exit Mode) Entry and Exit . . . . . . . . . . . . . . . . . . . . 75
`Figure 57 — Precharge Power-Down (Slow Exit Mode) Entry and Exit. . . . . . . . . . . . . . . . . . . 75
`Figure 58 — Refresh Command to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Figure 59 — Active Command to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Figure 60 — Precharge / Precharge all Command to Power-Down Entry . . . . . . . . . . . . . . . . . . 77
`Figure 61 — MRS Command to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`Figure 62 —Power-Down Entry/Exit Clarifications - Case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`Figure 63 —Power-Down Entry/Exit Clarifications - Case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`Figure 64 —Power-Down Entry/Exit Clarifications - Case 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
`Figure 65 —Functional Representation of ODT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
`Figure 66 —Synchronous ODT Timing Example for AL = 3; CWL = 5; ODTLon = AL + CWL -
`2 = 6.0; ODTLoff = AL + CWL - 2 = 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
`Figure 67 —Synchronous ODT example with BL = 4, WL = 7. . . . . . . . . . . . . . . . . . . . . . . . . . 83
`Figure 68 —ODT must be disabled externally during Reads by driving ODT low. (example:
`CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8;
`ODTLoff = CWL + AL - 2 = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
`Figure 69 —Dynamic ODT: Behavior with ODT being asserted before and after the write. . . . 87
`Figure 70 —Dynamic ODT: Behavior without write command, AL = 0, CWL = 5 . . . . . . . . . . 87
`Figure 71 —Dynamic ODT: Behavior with ODT pin being asserted together with write command
`for a duration of 6 clock cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
`Figure 72 —Dynamic ODT: Behavior with ODT pin being asserted together with write command
`for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5.89
`Figure 73 —Dynamic ODT: Behavior with ODT pin being asserted together with write command
`for a duration of 4 clock cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
`Figure 74 —Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition: AL
`is ignored. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
`Figure 75 —Synchronous to asynchronous transition during Precharge Power Down (with DLL
`frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
`Figure 76 —Asynchronous to synchronous transition during Precharge Power Down (with DLL
`frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9) . . . . . . . . . . . . . . . . . . 94
`Figure 77 —Transition period for short CKE cycles, entry and exit period overlapping
`(AL = 0, WL = 5, tANPD = WL - 1 = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
`Figure 78 —ZQ Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
`Figure 79 —Illustration of VRef(DC) tolerance and VRef ac-noise limits . . . . . . . . . . . . . . . . 102
`Figure 80 —Definition of differntial ac-swing and “time above ac-level” tDVAC. . . . . . . . . . 103
`Figure 81 —Single-ended requirement for differential signals. . . . . . . . . . . . . . . . . . . . . . . . . . 105
`Figure 82 —Vix Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
`
`vi
`
`Samsung Electronics Co., Ltd.
`Ex. 1046, p. vi
`
`

`

`JEDEC Standard No. 79-3A
`
`List of Figures
`Figure 83 —Input Nominal Slew Rate Definition for Single-Ended Signals. . . . . . . . . . . . . . . 107
`Figure 84 —Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# . . . . . . . . 108
`Figure 85 —Single Ended Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
`Figure 86 —Differential Output Slew Rate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
`Figure 87 —Reference Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . . 112
`Figure 88 —Address and Control Overshoot and Undershoot Definition . . . . . . . . . . . . . . . . . 113
`Figure 89 —Clock, Data, Strobe and Mask Overshoot and Undershoot Definition . . . . . . . . . 114
`Figure 90 —Output Driver: Definition of Voltages and Currents . . . . . . . . . . . . . . . . . . . . . . . 115
`Figure 91 —On-Die Termination: Definition of Voltages and Currents . . . . . . . . . . . . . . . . . . 118
`Figure 92:
`ODT Timing Reference Load123
`Figure 93 —Definition of tAON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
`Figure 94 —Definition of tAONPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
`Figure 95 —Definition of tAOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
`Figure 96 —Definition of tAOFPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
`Figure 97 —Definition of tADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
`Figure 98 —IDD1 Example (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer
`should be switched off (per MR1 bit A12 =”1”) to achieve Iout = 0mA. Address inputs are split
`into 3 parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
`Figure 99 —IDD2N / IDD3N Example (DDR3-800-555, 512Mb x8). . . . . . . . . . . . . . . . . . . . 132
`Figure 100 —IDD4R Example (DDR3-