(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2008/0238536A1
`HAYASH et al.
`(43) Pub. Date:
`Oct. 2, 2008
`
`US 200802.38536A1
`
`(54) SUPPLY VOLTAGE GENERATING CIRCUIT
`
`Publication Classification
`
`(75) Inventors:
`
`Koichiro HAYASHI, Tokyo (JP):
`Hitoshi Tanaka, Ome (JP)
`
`Correspondence Address:
`
`SUGHRUE MION, PLLC
`2100 PENNSYLVANIA AVENUE, N.W., SUITE
`8OO
`WASHINGTON, DC 20037 (US)
`
`(73) Assignee:
`
`(21) Appl. No.:
`
`ELPIDA MEMORY, INC, Tokyo
`(JP)
`12/052,422
`
`(22) Filed:
`
`Mar. 20, 2008
`
`Foreign Application Priority Data
`(30)
`Mar. 27, 2007 (JP) ................................. 2007-081754
`
`(51) Int. Cl.
`(2006.01)
`GOSF I/O
`(52) U.S. Cl. ......................................... 327/537; 327/535
`(57)
`ABSTRACT
`-
`-
`-
`A supply voltage generating circuit that enables a reduction in
`chip area includes: a booster for outputting a boosted voltage
`upon setts the boosted
`ge by class Rypig of a
`capacitor element; a power-supply step-down unit for step
`ping down Voltage of an external power Supply to a Voltage
`within a breakdown-Voltage range of the capacitor element,
`and applying the stepped-down voltage to the power Supply of
`the booster; and a switch element for switching between
`application of the external power Supply to the power Supply
`of the booster directly or via the power-supply step-down
`unit. The booster comprises multiple stages of booster cir
`cuits. The thicknesses of gate oxide films of capacitor ele
`ments constituted by MOS transistors included in respective
`ones of the booster circuits are the same and are made Smaller
`than the thickness of a gate oxide film of a MOS transistor
`included in a load circuit having the output of the booster at its
`power Supply.
`
`VDDP1
`
`VDOP2
`
`1 O
`
`
`
`
`
`
`
`
`
`POWER-SUPPLY
`STEP-DOWN UNIT
`
`SO
`
`BOOSTER
`CIRCUIT
`
`VPP
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 1
`
`

`

`Patent Application Publication
`
`Oct. 2, 2008 Sheet 1 of 5
`
`US 2008/0238536 A1
`
`FIG.1
`
`VDDP
`
`VDOP2
`
`
`
`SO
`
`BOOSTER
`CIRCUIT
`
`VPP
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 2
`
`

`

`Patent Application Publication
`
`Oct. 2, 2008 Sheet 2 of 5
`
`US 2008/0238536A1
`
`
`
`Vodd
`
`VPP
`
`SO
`
`SIGNAL SUPPLY
`CIRCUIT
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 3
`
`

`

`Patent Application Publication
`
`Oct. 2, 2008 Sheet 3 of 5
`
`US 2008/0238536A1
`
`FIG.3A
`
`
`
`Vod EVDDP 1
`
`Vdd EVDDP1
`S1 — N3
`
`A2 N4
`
`VPP
`
`Vss
`
`S5
`
`FIG.3B
`
`S1
`
`S3
`
`S5
`
`S2
`
`2 VDDP1
`
`...
`WDDP1 - - - -
`
`VDOP 1
`
`Vss
`
`- - - -
`
`VDDP1-VPP - - - -
`
`VDOP 1
`
`VDDP1 - - - -
`
`Vss
`
`2. VDDP1 - - -
`
`Vss
`
`3. VDDP1 ---
`
`
`
`A2
`
`VDDP1
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 4
`
`

`

`Patent Application Publication
`
`Oct. 2, 2008 Sheet 4 of 5
`
`US 2008/0238536A1
`
`Vodd FVDLP
`
`S1
`Vodd - — N3
`VDLP
`
`A2 N4
`
`So-
`
`VPP
`
`FIG.4A
`
`SW7
`O
`
`Vss
`
`C1
`
`FIG.4B
`
`S1
`
`2 VDLP
`...
`VDLP ----
`
`S5
`
`VDLP+VPP ----
`VDLP
`
`VDLP - - - -
`Vss
`
`2. VDLP - - -
`
`S4
`
`A2
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 5
`
`

`

`Patent Application Publication
`
`Oct. 2, 2008 Sheet 5 of 5
`
`US 2008/0238536 A1
`
`FIG.5
`
`VDDP1 VDDP1 WDDP2 VDDP2
`SW8
`
`
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 6
`
`

`

`US 2008/0238,536 A1
`
`Oct. 2, 2008
`
`SUPPLY VOLTAGE GENERATING CIRCUIT
`
`REFERENCE TO RELATED APPLICATION
`0001. This application is based upon and claims the ben
`efit of the priority of Japanese patent application No. 2007
`081754, filed on Mar. 27, 2007, the disclosure of which is
`incorporated herein in its entirety by reference thereto.
`
`FIELD OF THE INVENTION
`0002 This invention relates to a supply voltage generating
`circuit and, more particularly, to a Supply Voltage generating
`circuit for generating a boosted Voltage within a semiconduc
`tor storage device.
`
`BACKGROUND OF THE INVENTION
`0003) If specifications relating to a DRAM are changed or
`the specifications have not been fully decided, there are cases
`where the Supply Voltage Supplied from the outside in accor
`dance with a request from the user differs. A Supply Voltage
`supply circuit for driving a word line is one circuit for which
`different Supply Voltages are required of externally applied
`power. Designing Such a Supply Voltage Supply circuit
`involves preparing a plurality of types of transistors having
`oxide-film thicknesses for which circuit operation is opti
`mum, and designing the circuit based upon the plurality of
`types of transistors. If a booster circuit is designed assuming
`a case where the power Supplied will differ depending upon
`the specifications, the problem of oxide-film withstand volt
`age and a current-consumption problem ascribable to gate
`leakage must be taken into account. If, in order to avoid these
`problems, a transistor for thick-film capacitance is used in the
`circuit in accordance with the higher Voltage among Voltages
`that have been set depending upon specifications, there is the
`danger that this will result in a booster circuit of larger area.
`0004 Patent Document 1 describes a supply voltage gen
`erating circuit in which capacitors having different film thick
`nesses are used selectively in dependence upon the operating
`Supply Voltage, thereby reducing circuit layout area and gen
`erating a stable Supply Voltage. This Supply Voltage generat
`ing circuit is one that boosts the operating Supply Voltage of
`the device and outputs the boosted Voltage and has a first
`capacitor made of a thick insulating film, a second capacitor
`made of a thin gate insulating film, and a Switch circuit for
`changing the circuit connections of the first and second
`capacitors in accordance with the operating Supply Voltage.
`0005
`Patent Document 1
`0006 Japanese patent Kokai Publication No. JP-P2005
`158098A
`
`SUMMARY OF THE DISCLOSURE
`0007. The following analyses are given by the present
`invention. The entire disclosure of the above mentioned
`patent document is incorporated herein by reference thereto.
`0008. The booster of the supply voltage generating circuit
`has a boosting pump capacitor element that utilizes the oxide
`film capacitance of a transistor. There are many cases where
`the boosting capacitor element requires a very large capaci
`tance. This necessitates a large area and has a major impact
`upon the area of the overall chip. Since the capacitance of the
`oxide film is inversely proportional to the thickness of the
`oxide film, usually use of a thin-film capacitor element (thin
`film transistor) is desired. However, in a case where the Sup
`ply Voltage Supplied from the outside differs depending upon
`
`the specifications, as mentioned above, a thick-film transistor
`usually is used as the boosting capacitor element in order that
`the supply voltage supplied will not exceed the breakdown (or
`withstand) voltage of a thin-film transistor. Normally the
`value of a voltage for driving a word line will exhibit almost
`no change even if the Supply Voltage Supplied from the out
`side changes. Accordingly, regardless of the fact that the
`lower the external Supply Voltage, the greater the number of
`pump capacitor elements required, a thick film having little
`capacitance must be used even in a case where Voltage is low
`because of the breakdown voltage of the oxide film. Thus,
`with the conventional circuitry, the design must be such that
`transistor breakdown voltage will be in conformity with the
`high side of the external Supply Voltage. Consequently, part of
`the booster capacitance in the booster circuit, e.g., the first
`capacitor in Patent Document 1, must be made a thick-film
`capacitor element and, hence, the degree to which chip area
`can be reduced is limited.
`0009. Accordingly, it is an object of the present invention
`to provide a Supply Voltage generating circuit of Smaller chip
`aca.
`0010. According to a first aspect of the present invention,
`there is provided a Supply Voltage generating circuit compris
`ing: a booster that outputs a boosted Voltage upon generating
`the boosted Voltage by charge pumping of a capacitor ele
`ment. There is a power-supply step-down unit that steps down
`Voltage of an external power Supply to a Voltage within a
`breakdown-Voltage range of the capacitor element, and
`applies the stepped-down voltage to the power supply of the
`booster. There is a switch circuit group that switches between
`application of the external power Supply to the power Supply
`of the booster directly or via the power-supply step-down
`unit
`Preferably, in the supply voltage generating circuit
`0011
`of the present invention, the capacitor element is constituted
`by a MOS transistor having a gate oxide film, and the thick
`ness of the gate oxide film is made less than thickness of a gate
`oxide film of a MOS transistor included in a load circuit
`having the output of the booster as its power Supply.
`0012 Preferably, in the supply voltage generating circuit
`of the present invention, the booster comprises multiple
`stages of booster circuits, and thicknesses of gate oxide films
`of capacitor elements constituted by MOS transistors
`included in respective ones of the booster circuits are the
`SaC.
`0013 Preferably, in the supply voltage generating circuit
`of the present invention, the booster is so adapted that the
`number of booster stages in the multiple stages of booster
`circuits is changed over by the Switch circuit group in accor
`dance with the power-supply Voltage applied to the booster.
`0014 Preferably, in the supply voltage generating circuit
`of the present invention, the booster includes a pre-stage
`booster circuit and a post-stage booster circuit; the pre-stage
`booster circuit generates a first boosted signal having an
`amplitude between ground potential and a potential that is
`double the potential of the external power supply; the post
`stage booster circuit receives, as an input, the first boosted
`signal or a second boosted signal having an amplitude
`between ground potential and the output potential of the
`power-supply step-down unit; and the Switch circuit group
`has a first Switch element for Switching a connection destina
`tion of the power supply of the booster to the external power
`Supply or to the output of the power-supply step-down unit,
`and a second Switch element for Switching a connection des
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 7
`
`

`

`US 2008/0238,536 A1
`
`Oct. 2, 2008
`
`tination of the input of the post-stage booster circuit to the first
`or second boosted signal; wherein the second Switch element
`is switched to the first boosted signal when the first switch
`element has been Switched to the external power Supply, and
`the second switch element is switched to the second boosted
`signal when the first switch element has been switched to the
`output of the power-supply step-down unit.
`00.15
`Preferably, in the supply voltage generating circuit
`of the present invention, it is so arranged that a capacitor
`element that has become unnecessary for the boosting opera
`tion in the multiple stages of booster circuits owing to Switch
`ing by the Switch circuit group in accordance with the power
`Supply Voltage applied to the booster is connected by the
`Switch circuit group and made to function as a capacitor
`element for Stabilizing the output of the power-supply step
`down unit.
`0016 Preferably, in the supply voltage generating circuit
`of the present invention, the Switch circuit group is controlled
`by any of a metal option, fuse option and bonding option.
`0017. In a second aspect of the present invention, there is
`provided a semiconductor storage device comprising the Sup
`ply Voltage generating circuit, and a load circuit having the
`output of the booster as its power Supply.
`0018. The meritorious effects of the present invention are
`Summarized as follows.
`0019. In accordance with the present invention, the volt
`age of the external power Supply is stepped down to a Voltage
`within the breakdown-Voltage range of the capacitor element
`and is supplied to the booster in a case where the voltage of the
`external power supply exceeds the breakdown voltage of the
`capacitor element. As a result, thin-film capacitor elements
`can be used for all of the capacitor elements in the booster.
`This makes it possible to reduce chip area.
`0020. Other features and advantages of the present inven
`tion will be apparent from the following description taken in
`conjunction with the accompanying drawings, in which like
`reference characters designate the same or similar parts
`throughout the figures thereof.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0021
`FIG. 1 is a block diagram illustrating the configura
`tion of a Supply Voltage generating circuit according to an
`exemplary embodiment of the present invention;
`0022 FIG. 2 is a circuit diagram of a booster according to
`an exemplary embodiment of the present invention;
`0023 FIG. 3A is an equivalent circuit in a case where the
`booster performs a two-stage operation, and FIG. 3B is a
`timing chart illustrating the waveforms of signals associated
`with the equivalent circuit;
`0024 FIG. 4A is an equivalent circuit in a case where the
`booster performs a single-stage operation, and FIG. 4B is a
`timing chart illustrating the waveforms of signals associated
`with the equivalent circuit; and
`0025 FIG. 5 is a circuit diagram of a power-supply step
`down unit.
`
`PREFERRED MODES OF THE INVENTION
`0026. A preferred exemplary embodiment of the present
`invention will now be described in detail with reference to the
`accompanying drawings.
`0027 FIG. 1 is a block diagram illustrating the configura
`tion of a Supply Voltage generating circuit according to an
`exemplary embodiment of the present invention. As shown in
`
`FIG. 1, the Supply Voltage generating circuit includes a
`power-supply step-down unit 10, a booster 20 and a switch
`element SW1.
`0028. The booster 20 generates a boosted voltage by the
`charge pumping of capacitor elements and outputs the
`boosted Voltage generated. In a case where the Voltage of an
`external power supply exceeds the breakdown voltage of the
`capacitor elements, the power-supply step-down unit 10 steps
`down the external Supply Voltage to a Voltage within the range
`of breakdown Voltage of the capacitor elements and applies
`the stepped-down voltage to the power supply of the booster
`20. The switch element SW1 switches between application of
`the external power supply to the power supply of the booster
`20 directly or via the power-supply step-down unit 10.
`0029. The capacitor elements in the booster 20 are consti
`tuted by MOS transistors. Preferably, the thickness of the gate
`oxide film of each MOS transistor is made less than the
`thickness of a gate oxide film of a MOS transistor included in
`a load circuit having the output VPP (FIG. 1) of the booster 20
`as its power Supply. An example of the load circuit is a circuit
`for driving a word line.
`0030 Preferably, the booster 20 comprises multiple
`booster circuits 21a and 21b, and the thicknesses of gate
`oxide films of the capacitor elements constituted by the MOS
`transistors included in respective ones of the booster circuits
`are the same.
`0031 Preferably, the booster 20 is so adapted that the
`number of booster stages (e.g., one stage or two stages) con
`stituted by the multiple booster circuits 21a, 21b is changed
`over by a switch element SW2 in accordance with the power
`supply voltage applied to the booster 20.
`0032. It may be so arranged that a semiconductor storage
`device typified by a DRAM, particularly a DDR-SDRAM,
`includes a Supply Voltage generating circuit having the above
`described configuration, and a load circuit (not shown) the
`power supply of which is the output of the booster 20. An
`example of the load circuit is a circuit for driving a word line.
`0033. In accordance with the supply voltage generating
`circuit having the above-described configuration, the Voltage
`of the external power supply is stepped down by the power
`Supply step-down unit 10 in a case where the external Supply
`Voltage is so high as to exceed the breakdown Voltage of the
`capacitor elements (thin-film transistors). This is based upon
`the condition that the external supply voltage will differ
`depending upon the specifications. It is possible for thin-film
`capacitor elements having a large capacitance to be used in
`the booster 20 and to be used conjointly also in a case where
`the Supply Voltage is low. Accordingly, layout area in the chip
`can be reduced by a wide margin. Now an exemplary embodi
`ment of the present invention will be described in detail.
`
`Exemplary Embodiment
`0034 FIG. 1 is a block diagram illustrating a supply volt
`age generating circuit according to an exemplary embodi
`ment of the present invention. As shown in FIG. 1, the supply
`Voltage generating circuit includes the power-supply step
`down unit 10, booster 20 and switch element SW1, which is
`of single-pole, double-throw type. The switch element SW1
`Switches between application of the Voltage of an external
`power supply VDDP1 to power supply Vdd of the booster 20
`directly or as power supply VDLP following stepping down
`of the voltage of an external power supply VDDP2 by the
`power-supply step-down unit 10,
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 8
`
`

`

`US 2008/0238,536 A1
`
`Oct. 2, 2008
`
`0035. The booster 20 includes a pre-stage booster circuit
`21a, apost-stage booster circuit 21b, and single-pole, double
`throw switch element SW2 for switching between the booster
`circuits 21a and 21b. The booster 20 generates a boosted
`Voltage from power Supply Vdd by charge pumping of the
`capacitor elements using a driving signal S0, and Supplies the
`boosted Voltage to a load circuit, an example of which is a
`circuit for driving a word line, as power supply VPP. At this
`time the switch element SW2 changes over the number of
`booster stages in the booster 20 to one stage, namely the
`booster circuit 21b, or to two stages, namely the booster
`circuits 21a and 21b.
`0036. The booster circuit 21a receives the driving signal
`S0 as an input and outputs a signal (a first boosted signal)
`having an amplitude between ground potential and apotential
`that is double the potential of the external power supply
`VDDP1. Further, the booster circuit 21b receives a signal (a
`second boosted signal) having an amplitude between ground
`potential and the potential of power supply VDLP, or the
`output signal (the first boosted signal) of the booster circuit
`21a, as an input, boosts the signal and outputs the boosted
`signal as power supply VPP. The switch element SW2 is
`switched to the first boosted signal when the switch element
`SW1 has been switched to the external power supply VDDP1,
`and the Switch element SW2 is switched to the second
`boosted signal when the switch element SW1 has been
`switched to the output (VDLP) of the power-supply step
`down unit 10.
`0037. The details of the booster 20 will be described next.
`FIG. 2 is a circuit diagram of the booster according to this
`exemplary embodiment of the present invention. As shown in
`FIG. 2, the booster 20 includes the booster circuits 21a, 21b
`and a signal Supply circuit 22 to which the signal S0 is input
`and which outputs signals S1 to S5. The booster circuit 21a
`has N-channel transistors N1, N2, a P-channel transistor P1,
`a capacitor element C1 constituted by a MOS transistor, and
`single-pole, double-throw switch elements SW3 to SW7. The
`booster circuit 21b has N-channel transistors N3, N4, a
`capacitor element C2 constituted by a MOS transistor, and the
`switch element SW2. The N-channel transistor N1 and
`capacitor elements C1, C2 are transistors (thin-film transis
`tors) each having a thick gate insulating film. The N-channel
`transistors N2 to N4 and the P-channel transistor P1 are
`transistors (thick-film transistor) each having a thick gate
`insulating film. Furthermore, the switches SW1 to SW7 are
`controlled by a changeover Switch-option signal according to
`any of a metal option, fuse option or bonding option.
`0038. The N-channel transistor N1 has a drain connected
`to the power Supply Vdd a source connected to one end of the
`switch element SW4, the other end of which is connected to
`the power supply Vdd, and to the source of the P-channel
`transistor P1, and a gate connected to the contact on the
`single-pole side of the switch element SW5. The P-channel
`transistor P1 has a drain connected to the drain of the N-chan
`nel transistor N2 and to one end of the Switch element SW2,
`and a gate connected to the contact on the single-pole side of
`the Switch element SW3. The N-channel transistor N2 has a
`Source connected to power Supply VSS (ground) and a gate
`connected to the single-pole side of the switch element SW6.
`The capacitor element C1 has one end connected to the con
`tact on the single-pole side of the switch element SW4, and its
`other end connected to the contact on the single-pole side of
`the switch element SW7. The signal S3 is applied to one end
`of the Switch element SW3, the other end of which is con
`
`nected to the power supply Vss. The signal S1 is applied to
`one end of the switch element SW5, the other end of which is
`connected to the power Supply VSS. The signal S2 is applied to
`one end of the switch element SW7, the other end of which is
`connected to the power supply Vss. The signal S3 is applied to
`one end of the switch element SW6, the other end of which is
`connected to the power supply Vdd.
`0039. The N-channel transistor N3 has a drain connected
`to the power Supply Vdd a source connected to one end of the
`capacitor element C2 and to the drain of the N-channel tran
`sistor N4, and a gate to which the signal S1 is applied. The
`N-channel transistor N4 has a source connected as the power
`supply VPP and a gate to which the signal S5 is applied. The
`capacitor element C2 has its other end connected to the con
`tact on the single-pole side of the switch element SW2. The
`signal S4 is applied to the other end of the switch element
`SW2.
`0040. Described next will be operation of the booster cir
`cuits when the switches SW2 to SW7 in FIG. 2 are changed
`over in operative association with the switch element SW1 in
`FIG.1. FIG.3A illustrates the connections inacase where the
`voltage of the external power supply VDDP1 is lower than the
`thin-film transistor breakdown voltage, and FIG. 4A illus
`trates the connections in a case where the Voltage of the
`external power supply VDDP2 is higher than the thin-film
`transistor breakdown voltage. It should be noted that the
`power Supplies and the Voltage values of these power Supplies
`will be represented by the same reference characters. VDDP1
`indicates external supply voltage that is lower than the thin
`film transistor breakdown voltage, VDDP2 indicates external
`Supply Voltage that is higher than the thin-film transistor
`breakdown voltage, VPP indicates supply voltage for driving
`a word line, and VDLP indicates supply voltage obtained by
`stepping down VDDP2 to the range of the thin-film transistor
`breakdown voltage by the power-supply step-down unit 10.
`That is, it is assumed that the allowable range of thin-film
`breakdown voltage is less than VDLP and that the allowable
`range of thick-film breakdown voltage is less than VPP. The
`relationships among these Supply Voltages are as follows for
`the sake of simplicity: VPPs-VDDP2>VDLP>VDDP1,
`2.VDLP>VPP 3.VDDP1-VPP VPP-2.VDDP1.
`0041
`FIG. 3A is an equivalent circuit in a case where the
`booster performs a two-stage operation, and FIG. 3B is a
`timing chart illustrating the waveforms of signals associated
`with the equivalent circuit. More specifically, FIG. 3A illus
`trates an equivalent circuit relating to the connections of the
`booster 20 in a case where the voltage of the external power
`supply VDDP1 is lower than the thin-film transistor break
`down voltage. FIG. 3B is a timing chart of the associated
`signals.
`0042 (1) When the voltage level of the signal S1 is
`2:VDDP1, the N-channel transistor N1 to the gate of which
`the signal S1 is applied turns on and the source of the N-chan
`nel transistor N1, namely one end of the capacitor element
`C1, is charged toward VDDP1. Since the voltage level of the
`signal S3 is VDDP1 at this time, the P-channel transistor P1 if
`off and has no effect upon the charging operation of the
`capacitor element C1. It should be noted that the voltage level
`of the signal S2 is VSS. Accordingly, the capacitor element C1
`is charged by the potential VDDP1-Vss.
`0043. On the other hand, since the voltage level of the
`signal S1 is 2:VDDP1, the N-channel transistor N3 turns on
`and contact A2, which is the source of the N-channel transis
`tor N3, namely one end of the capacitor element C2, is
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 9
`
`

`

`US 2008/0238,536 A1
`
`Oct. 2, 2008
`
`charged toward VDDP1. Since the voltage level of the signal
`S3 is VDDP1 at this time, the N-channel transistor N2 is on
`and the potential at the other end of the capacitor element C2
`is Vss.
`0044 (2) If the voltage level of the signal S1 becomes
`VDDP1, then the voltage level of the signal S2 rises from Vss
`to VDDP1 and this is accompanied by a rise in the potential at
`the source of the N-channel transistor N1, namely at one end
`of the capacitor element C1, from VDDP1 to 2:VDDP1. The
`N-channel transistor N1 turns off and has no effect upon the
`potential elevating operation. Since the voltage level of the
`signal S3 is Vss at this time, the P-channel transistor P1 is on
`and the N-channel transistor N2 is off. Accordingly, the
`potential at one end of the capacitor element C1 is transmitted
`to the other end of the capacitor element C2 as the potential at
`contact (node) A1.
`0045. As a result, the potential at one end of the capacitor
`element C2 rises from VDDP1 to 3:VDDP1. Since the voltage
`level of the signal S1 is VDDP1 at this time, the N-channel
`transistor N3 is off and has no effect upon the potential
`elevating operation. Further, since the voltage level of the
`signal S5 is VDDP1+VPP, the N-channel transistor N4 turns
`on and the potential at one end of the capacitor element C2,
`namely at contact (node) A2, is transmitted to VPP. By sup
`plying the electric charge that has accumulated by charging in
`the capacitor element C2 to the outside, the potential at con
`tact A2 gradually declines.
`0046. The booster 20 supplies VPP with a voltage close to
`2:VDDP1 by the operation described above. At this time, the
`locations at which the thin-film transistors of the capacitor
`elements C1 and C2, etc. are formed in the booster 20 are
`always subjected to only a difference potential of not more
`than VDDP1 across the gate and Source or across the gate and
`drain.
`0047 FIG. 4A is an equivalent circuit in a case where the
`booster performs a single-stage operation, and FIG. 4B is a
`timing chart illustrating the waveforms of signals associated
`with the equivalent circuit. More specifically, FIG. 4A illus
`trates an equivalent circuit relating to the connections of the
`booster 20 in a case where the voltage of the external power
`supply VDDP2 is higher than the thin-film transistor break
`down voltage. In this case, VDDP2 is stepped down to VDLP
`by the power-supply step-down unit 10 and VDLP is applied
`as the power supply Vdd of the booster 20.
`0.048.
`In FIG. 2, the N-channel transistor N1, which has its
`gate connected to Vss, is turned off. Further, the N-channel
`transistor N2, which has its gate connected to Vdd, turns on,
`and so does the P-channel transistor P1, which has its gate
`connected to Vss. Accordingly, the N-channel transistors N1,
`N2 and P-channel transistor P1, which have been isolated
`from the boosting operation, have no effect upon the other
`circuits.
`0049. On the other hand, as illustrated in FIG. 4A, one end
`of the capacitor element C1 is connected to the power Supply
`Vdd, namely to the power supply VDLP which is the result or
`step-down by the power-supply step-down unit 10, and the
`other end of the capacitor element is connected to Vss.
`Accordingly, the capacitor element C1 functions as a stabi
`lizing capacitance between Vdd/Vss in the booster 20.
`0050 FIG. 4B is a timing chart of signals associated with
`FIG. 4A.
`0051 (1) When the voltage level of the signal S1 is
`2VDDP1, the N-channel transistor N3 to the gate of which
`the signal S1 is applied turns on and the source of the N-chan
`
`nel transistor N3, namely one end of the capacitor element
`C2, is charged toward VDLP. The other end of the capacitor
`element C2 is made Vss by the signal S4.
`0.052
`(2) If the Voltage level of the signal S1 becomes
`VDLP, then the voltage level of the signal S4 rises from Vss to
`VDLP and the potential at contact A2, namely at one end of
`the capacitor element C2, rises from VDLP to 2-VDLP. Since
`the voltage level of the signal S1 is VDLP at this time, the
`N-channel transistor N3 is off and has no effect upon the
`potential elevating operation. Further, since the Voltage level
`of the signal S5 is VDLP+VPP, the N-channel transistor N4
`turns on and the potential at one end of the capacitor element
`C2, namely at contact A2, is transmitted to VPP. By supplying
`the electric charge that has accumulated by charging in the
`capacitor element C2 to the outside, the potential at contact
`A2 gradually declines.
`0053. The locations (portions) at which the thin-film tran
`sistors of the capacitor elements C1 and C2, etc. are formed in
`the booster 20 which operates as set forth above are always
`subjected to only a difference potential of not more than
`VDDP1 across the gate and source or across the gate and
`drain.
`0054. In a case where the external supply voltage is
`VDDP2 in the booster 20 constructed as described above, the
`configuration is made one in which the number of booster
`stages is made a single stage. This is because 2-VDLP is
`Somewhat larger than VPP and the single-stage configuration
`is better than the two-stage configuration in that current con
`sumption declines and a power supply at the VPP level is
`capable of being provided. The reason for this is that although
`the contacts A1 and A2 in FIG. 3A should ideally take on
`potentials of 2:VDDP13VDDP1, respectively, in actuality
`the ideal potentials are not attained owing to the influence of
`parasitic capacitance. Accordingly, it is preferred in terms of
`obtaining good Voltage conversion efficiency that the number
`of stages be made as Small as possible so as to eliminate the
`influence of parasitic capacitance. Further, the two-stage con
`figuration is not preferred over the one-stage configuration
`since current consumption increases by an amount commen
`Surate with the increased number of operating contacts.
`0055 FIG. 5 is a circuit diagram of the power-supply
`step-down unit 10. The power-supply step-down unit 10 is a
`circuit for performing driving by stepping down VDDP2 and
`bringing the power-supply voltage of VDLP/2, which has
`been generated within the DRAM, etc., to the VDLP level.
`The power-supply step-down unit 10 has N-channel transis
`tors N11 to N16, P-channel transistors P11 to P14 and switch
`elements SW8 to SW10. The N-channel transistors N12 and
`N13, which form a differential pair, have their sources tied
`together and connected to the N-channel transistor N11 serv
`ing as a current source, and have their drains connected
`respectively to the P-channel transistors P11, P12, which
`construct a current mirror. Further, VDLP/2 is applied to the
`gate of the N-channel transistor N12, and the gate of N-chan
`nel transistor N13 is connected to the middle point of a series
`circuit comprising diode-connected N-channel transistors
`N14 and N15. The drain of the N-channel transistor N12 is
`connected to the gate of the P-channel transistor P14, whose
`source is connected to VDDP2. Furthermore, the drain of the
`P-channel transistor P14 supplies the booster 20 with VDLP
`as the output of the power-supply step-down unit 10 and is
`connected to the anode (drain and gate) of the N-channel
`transistor N14. The N-channel transistor N14 has its source
`connected to VSS.
`
`Samsung Electronics Co., Ltd.
`Ex. 1037, p. 10
`
`

`

`US 2008/0238,536 A1
`
`Oct. 2, 2008
`
`0056. It should be noted that in a case where the step-down
`function of the power-supply step-down unit 10 is not used,
`the Switch elements SW8 to SW10 shown in FIG. 5 are
`changed over so as not to actuate the power-supply step-down
`unit 10. That is, the gate of the P-channel transistor P13
`becomes Vss, and P-channel transistor P13 turns on and the
`P-channel transistors P11, P12, P14 are turned off. Further,
`the gate of the N-channel transistor N11 becomes Vss, the
`N-channel transi