(12) United States Patent
`Sim et al.
`
`USOO6798709B2
`(10) Patent No.:
`US 6,798,709 B2
`(45) Date of Patent:
`Sep. 28, 2004
`
`(54) MEMORY DEVICE HAVING DUAL POWER
`PORTS AND MEMORY SYSTEM
`INCLUDING THE SAME
`
`(75) Inventors: Jae-Yoon Sim, Suwon (KR); Dong-Il
`Seo, Yongin-Shi (KR)
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Suwon-si (KR)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 10 days.
`
`(*) Notice:
`
`(21) Appl. No.: 10/384,630
`(22) Filed:
`Mar 11, 2003
`(65)
`Prior Publication Data
`
`US 2003/0201673 A1 Oct. 30, 2003
`Foreign Application Priority Data
`(30)
`Apr. 25, 2002 (KR) ................................ 10-2002-0022682
`(51) Int. Cl." .................................................. G11C 7700
`(52) U.S. Cl. .............. 365/226; 365/189.09; 365/189.11
`(58) Field of Search ............................ 365/226, 189.09,
`365/189.11, 227
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`6,320,457 B1 11/2001 Yang
`
`6,574,161 B2
`
`6/2003 Ooishi ........................ 365/226
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`O9-006442
`
`1/1997
`
`* cited by examiner
`
`Primary Examiner David Lam
`(74) Attorney, Agent, or Firm Volentine Francos, PLLC
`(57)
`ABSTRACT
`
`A plurality of internal circuits of a memory device are
`operable at first and Second internal Voltages, where the first
`internal Voltage is less than the Second internal Voltage. A
`first power port of the memory device receives a first power
`Supply Voltage, and a Second power port of the memory
`device receives a Second power Supply Voltage, where the
`first power Supply Voltage is less than the Second power
`Supply Voltage. An internal Voltage generation circuit of the
`memory device is Selectively operable in either a first mode
`in which the Second internal Voltage is generated from the
`first power Supply Voltage, or a Second mode in which the
`Second internal Voltage is generated from the Second power
`Supply Voltage.
`
`23 Claims, 6 Drawing Sheets
`
`200 \
`
`
`
`210
`
`220
`
`VOLTAGE
`REGULATOR
`
`CONTROLLER
`
`WCC1
`
`MEMORY DEVCE
`
`WCC2
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 1
`
`

`

`U.S. Patent
`
`Sep. 28, 2004
`
`Sheet 1 of 6
`
`US 6,798,709 B2
`
`100 \
`
`
`
`110
`
`120
`
`VOLTAGE
`REGULATOR
`
`WCC
`
`CONTROLLER
`
`FIG. 1
`
`PRIOR ART
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 2
`
`

`

`U.S. Patent
`
`Sep. 28, 2004
`
`Sheet 2 of 6
`
`US 6,798,709 B2
`
`200 \
`
`
`
`210
`
`220
`
`VOLTAGE
`REGULATOR
`
`WCC1
`
`CONTROLLER
`
`WCC1
`
`MEMORY DEVICE
`
`WCC2
`
`FIG. 2
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 3
`
`

`

`U.S. Patent
`
`Sep. 28, 2004
`
`Sheet 3 of 6
`
`US 6,798,709 B2
`
`w
`
`
`
`
`
`310
`
`330
`
`FIRST VOLTAGE
`REGULATOR
`
`SECOND WOLAGE
`REGULATOR
`
`FIG. 3
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 4
`
`

`

`U.S. Patent
`
`Sep. 28, 2004
`
`Sheet 4 of 6
`
`US 6,798,709 B2
`
`WCC
`
`WCC
`
`CNT or MRS
`
`WCC2
`
`FiRST VOLTAGE SECOND VOLTAGE
`GENERATOR
`EN
`
`
`
`
`
`
`
`THIRD WOLTAGE
`GENERATOR
`EN
`
`/CNTL of /MRS
`in arm - an on as me - al
`
`
`
`WNT
`
`WPP
`
`FIG. 4
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 5
`
`

`

`U.S. Patent
`
`Sep. 28, 2004
`
`Sheet 5 of 6
`
`US 6,798,709 B2
`
`520
`
`VCC2
`
`500
`\
`
`CNTL. Or MRS
`
`
`
`HGH WOLTAGE
`GENERATOR
`
`VPP
`
`510
`
`F.G. 5
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 6
`
`

`

`U.S. Patent
`
`Sep. 28, 2004
`
`Sheet 6 of 6
`
`US 6,798,709 B2
`
`600
`\,
`
`CNT or MRS
`
`620
`
`HGH VOLTAGE
`GENERATOR
`
`
`
`VPP
`
`610
`
`F.G. 6
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 7
`
`

`

`US 6,798,709 B2
`
`1
`MEMORY DEVICE HAVING DUAL POWER
`PORTS AND MEMORY SYSTEM
`INCLUDING THE SAME
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention generally relates to memory
`devices, and more particularly, the present invention relates
`to memory devices having dual power ports and to memory
`Systems equipped with memory devices having dual power
`ports.
`A claim of priority is made to Korean Patent Application
`No. 2002-22682, filed on Apr. 25, 2002, the contents of
`which are incorporated herein by reference.
`2. Description of the Related Art
`Currently, most memory Systems are equipped to receive
`an externally Supplied power Voltage, and to convert the
`externally Supplied power Voltage into an internal power
`Voltage. The internal power Voltage, which may be higher or
`lower than the externally Supplied power Voltage, is used as
`an operational Voltage of internal circuits of the memory
`System.
`FIG. 1 is a block diagram illustrating major components
`parts of a conventional dynamic random acceSS memory
`(DRAM) system. As shown, a DRAM system 100 includes
`a DRAM 130, a voltage regulator 110 to which an external
`power Voltage VEXT is Supplied, and a memory controller
`120. The voltage regulator 110 converts the external power
`voltage VEXT into a power voltage VCC which is lower
`than the external power voltage VEXT. For example, the
`external power voltage VEXT may be 5.0V and the power
`voltage VCC may be 3.3V. The regulated power voltage
`VCC is Supplied as an operational power Voltage to the
`controller 120 and DRAM 130. The use of a lower-voltage
`power Voltage VCC is primarily intended to reduce power
`consumption.
`In Some cases, for example to compensate for a Voltage
`loSS caused by a drop in a transistor threshold Voltage, it may
`be necessary for the DRAM 130 to internally generate an
`internal power voltage VPP which is higher than the power
`voltage VCC. The internal power voltage VPP Voltage may
`be used in Several DRAM circuit components, particularly
`those constructed with NMOS transistors, Such as a word
`line driver circuit, a bit line isolation circuit in a shared Sense
`amplifier circuit Structure, and/or a data output buffer circuit.
`Specifically, the word line driver circuit may Supply the
`voltage VPP to a word line to allow data be read from or
`written to a DRAM cell during a read or write operation,
`without a threshold voltage loss of a transfer transistor of the
`cell. The bit line isolation circuit may be supplied with the
`voltage VPP for full HIGH level data transmission between
`a bit line and a data line. The output buffer may be supplied
`with the voltage VPP to sufficiently drive an output high
`voltage (VOH) level.
`U.S. Pat. No. 6,320,457 describes circuits having electric
`charge pumps for generation of the internal power Voltage
`VPP. However, as is generally known, charge pump circuits
`are generally inefficient and consume large amounts of
`current. Also, when employing a given charge pump circuit,
`the pumping current increases with an increase in the target
`voltage VPP, while pumping efficiency decreases with an
`increase in the target voltage VPP. Current consumption of
`the charge pump circuit is often a critical factor in the overall
`power performance of a memory device, and it is necessary
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`to adopt a charge pump circuit which has appropriate
`characteristics for a particular memory device.
`SUMMARY OF THE INVENTION
`According to one aspect of the invention, a plurality of
`internal circuits of a memory device are operable at first and
`Second internal Voltages, where the first internal Voltage is
`less than the Second internal Voltage. A first power port of the
`memory device receives a first power Supply Voltage, and a
`Second power port of the memory device receives a Second
`power Supply Voltage, where the first power Supply Voltage
`is less than the Second power Supply Voltage. An internal
`Voltage generation circuit of the memory device is Selec
`tively operable in either a first mode in which the second
`internal Voltage is generated from the first power Supply
`Voltage, or a Second mode in which the Second internal
`Voltage is generated from the Second power Supply Voltage.
`According to another aspect of the present invention, a
`Voltage regulator of a memory System generates a first
`power Supply Voltage from a Second power Supply Voltage,
`where the Second power Supply Voltage is greater than the
`first power Supply Voltage. A plurality of internal circuits of
`a memory device of the memory System are operable at first
`and Second internal Voltages, where the first internal Voltage
`is less than the Second internal Voltage. A first power port of
`the memory device receives the first power Supply Voltage,
`and a Second power port of the memory device receives the
`Second power Supply Voltage. An internal Voltage generation
`circuit of the memory device is Selectively operable in either
`a first mode in which the Second internal Voltage is generated
`from the first power Supply Voltage, or a Second mode in
`which the second internal voltage is generated from the
`Second power Supply Voltage. A control circuit of the
`memory System controls an operation of the memory device.
`According to Still another aspect of the present invention,
`a first voltage regulator of a memory System generates a first
`power Supply Voltage from a Second power Supply Voltage,
`where the Second power Supply Voltage is greater than the
`first power Supply Voltage, and a Second Voltage regulator of
`the memory System generates a third power Supply Voltage
`from the Second power Supply Voltage, where the third
`power Supply Voltage is less than the Second power Supply
`Voltage and greater than the first power Supply Voltage. A
`plurality of internal circuits of a memory device of the
`memory System are operable at first and Second internal
`Voltages, where the first internal Voltage is less than the
`Second internal Voltage. A first power port of the memory
`device receives the first power Supply Voltage, and a Second
`power port of the memory device receives the third power
`Supply Voltage. An internal Voltage generation circuit of the
`memory device is Selectively operable in either a first mode
`in which the Second internal Voltage is generated from the
`first power Supply Voltage, or a Second mode in which the
`Second internal Voltage is generated from the third power
`Supply Voltage. A control circuit of the memory System
`controls an operation of the memory device.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The above and other aspects of the invention will become
`readily apparent from the detailed description that follows,
`with reference to the accompanying drawings, in which:
`FIG. 1 is a block diagram illustrating a conventional
`memory System;
`FIG. 2 is a block diagram illustrating a memory System
`according to an embodiment of the present invention;
`FIG. 3 is a block diagram illustrating a memory System
`according to another embodiment of the present invention;
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 8
`
`

`

`US 6,798,709 B2
`
`3
`FIG. 4 is a block diagram illustrating a memory device
`according to an embodiment of the present invention;
`FIG. 5 is a block diagram illustrating a memory device
`according to another embodiment of the present invention;
`and
`FIG. 6 is a block diagram illustrating a memory device
`according to Still another embodiment of the present inven
`tion.
`
`4
`system 300 includes a first voltage regulator 310, a second
`voltage regulator 320, a controller 330 and a memory device
`340. The first voltage regulator 310 receives an external
`power voltage VEXT and outputs a first voltage VCC1. The
`Second Voltage regulator 320 receives the external power
`voltage VEXT and outputs a second voltage VCC2. Here,
`VEXT>VCC2>VCC1. The first voltage VCC1 is supplied as
`an operational voltage to the controller 330 which outputs a
`control signal CNTL to the memory device 340.
`The memory device 340 is connected to receive the first
`voltage VCC1 and the second voltage VCC2. The memory
`device is made up of a plurality of internal circuits which are
`operable at first and second internal voltages, VINT and
`VPP, where VINT is less than VPP. By way of examples,
`VEXT is 5.0V, VCC1 is 3.3V, VCC2 is 4.0V, VINT is 2.4V,
`and VPP is 4.5V. The memory device 340 is selectively
`operable in either a normal power mode in which the Second
`internal voltage VPP is generated from the first power
`supply voltage VCC1, or a low power mode in which the
`second internal voltage VPP is generated from the second
`power supply voltage VCC2 which is higher than VCC1.
`Similar to the first embodiment, the selection of the
`normal power mode or the low power mode will depend on
`whether the second voltage VCC2 is applied to the VCC2
`terminal of the memory device 340. That is, while the
`memory device 340 may be equipped with the VCC2
`terminal, the memory System (module), into which the
`memory device 340 is plugged, may in Some cases not be of
`a type which is configured with the Second Voltage regulator
`320. Thus, the memory device 340 is equipped to operate in
`either power mode.
`One manner of controlling the power mode of the
`memory device 340 is by way of a control signal from the
`controller 330 of the memory system 300. Another way is to
`rely on information contained in the mode register set MRS
`of the memory device, which generally contains information
`as to a configuration of the memory system 300. Yet another
`way is to detect the presence of the voltage VCC2 on the
`terminal VCC2. If the voltage VCC2 is detected at the VCC2
`terminal, then the low power mode is Selected, and if no
`voltage is detected at the VCC2 terminal, then the normal
`power mode is Selected.
`FIG. 4 illustrates a memory device having dual power
`ports according to an embodiment of the present invention.
`To assist in the understanding of the operation of the
`memory device, the description below includes a number of
`exemplary Specific Voltage values. However, it should be
`understood that these voltages values are non-limiting
`examples only.
`The memory device 400 of FIG. 4 includes first through
`third voltage generators 410, 420, 430, and a switching unit
`440. The first voltage generator 410 receives a first voltage
`VCC1 (3.3V), and drops the received voltage to generate a
`first internal voltage VINT (2.4V). The second voltage
`generator 420 also receives the first voltage VCC1 (3.3V),
`and raises the received Voltage to generate a Second internal
`voltage VPP (4.5V). The second voltage generator 420 may
`include a charge pump. The third voltage generator 430
`receives a second voltage VCC2 (5.0V), and drops the
`received Voltage to generate the Second internal Voltage VPP
`(4.5V).
`In the example above, VCC1 (3.3V) is greater than VINT
`(2.4V), and VCC2 (5.0V) is greater than VPP (4.5V), and
`therefore the first and third voltage generators 410 and 430
`do not require a charge pump operation. However, the
`second voltage VCC2 may be less than VPP (e.g., VCC2
`
`15
`
`25
`
`35
`
`40
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Several non-limiting embodiments of the present inven
`tion are described in detail below. Each embodiment is
`characterized by a memory device which is capable of
`receiving dual power Voltages or by a memory System which
`includes Such a memory device. The dual power Voltages are
`represented, by way of example, as a Voltage VCC1 and a
`voltage VCC2, where VCC2 is higher than VCC1. The
`voltages VCC1 and VCC2 are selectively used to generate
`the internal power voltage VPP
`FIG. 2 illustrates a memory system 200 according to an
`embodiment of the present invention. The memory System
`200 includes a voltage regulator 210, a controller 220 and a
`memory device 230. The voltage regulator 210 receives an
`external power Voltage VEXT and outputs a first voltage
`VCC1. Here, VEXT-VCC1. The first voltage VCC1 is
`Supplied as an operational Voltage to the controller 220
`which outputs a control signal CNTL to the memory system
`200.
`The memory device 230 is connected to receive the
`external voltage VEXT and the first voltage VCC1. In this
`embodiment, VEXT is the same as a second voltage VCC2.
`The memory device is made up of a plurality of internal
`circuits which are operable at first and Second internal
`voltages, VINT and VPP, where VINT is less than VPP. By
`way of examples, VCC1 is 3.3V, VCC2 is 5.0V, VINT is
`2.4V, and VPP is 4.5V.
`Since the voltage VCC2 is higher than the voltage VCC1,
`less power is consumed when generating the Second internal
`voltage VPP from the voltage VCC2. Accordingly, the
`memory device 230 is selectively operable in either a normal
`power mode in which the second internal voltage VPP is
`generated from the first power Supply Voltage VCC1, or a
`low power mode in which the second internal voltage VPP
`is generated from the Second power Supply Voltage VCC2.
`45
`Generally, the Selection of the normal power mode or the
`low power mode will depend on whether the external
`voltage VEXT is directly applied to the VCC2 terminal of
`the memory device 230. That is, while the memory device
`230 may be equipped with the VCC2 terminal, the memory
`system (module), into which the memory device 230 is
`plugged, may in Some cases not be a type which is config
`ured to supply the VEXT Voltage. Thus, the memory device
`230 is equipped to operate in either power mode.
`One manner of controlling the power mode of the
`memory device 230 is by use of a control signal CNTL from
`the controller 220 of the memory system 200. Another way
`is to rely on information contained in the mode register Set
`MRS of the memory device, which generally contains
`information as to a configuration of the memory system 200.
`Yet another way is to detect the presence of the Voltage
`VEXT on the terminal VCC2. If the voltage VEXT is
`detected at VCC2, a control Signal is generated to Select the
`low power mode, and if no Voltage is detected at VCC2, a
`control Signal is generated to Select the normal power mode.
`FIG. 3 illustrates a memory system 300 according to
`another embodiment of the present invention. The memory
`
`50
`
`55
`
`60
`
`65
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 9
`
`

`

`S
`may be 4.0V), in which case the third voltage generator
`would be equipped with a charge pump to increase is VCC2
`(4.0V) to VPP (4.5V). However, since the voltage increase
`of 0.5 volts required by the third voltage generator 430 is
`less than the Voltage increase of 1.2 volts required by the
`Second Voltage generator 420, the third voltage generator
`430 operates much more efficiently than the second voltage
`generator 420.
`The Switching unit 440 receives a control signal CNTL
`from the controller of the memory system or the information
`contained in a mode register MRS of the memory device,
`and Selectively enables either one of the Second Voltage
`generator 420 or the third voltage generator 430. It is noted
`that the control signal CNTL may instead by derived inter
`nally of the memory device upon detecting the presence or
`absence of the voltage VCC2. In this example, the Switching
`unit 440 includes an inverter connected to receive the
`control signal CNTL or the mode register signal MRS. The
`second voltage generator 420 is enabled by the inverted
`signal CNTL/MRS and the third voltage generator 430 is
`enabled by the control signal CNTL or the information of the
`mode register MRS.
`In operation, a power mode of the memory device is used
`to control the generation of the voltage VPP. That is, during
`a normal power mode, the Second Voltage generator 420 is
`enabled to generate the voltage VPP from the voltage VCC1.
`On the other hand, in a low power mode, the third Voltage
`generator 430 is enabled to generate the voltage VPP from
`the higher Voltage VCC2, thus lowering power consump
`tion.
`FIGS. 5 and 6 illustrate memory devices having dual
`power ports according to other embodiments of the present
`invention. To assist in the understanding of the operation of
`memory devices, the descriptions below include a number of
`exemplary Specific Voltage values. However, it should be
`understood that these voltages values are non-limiting
`examples only.
`Referring to FIG. 5, the memory device 500 includes a
`high voltage generator 510 and a switching unit 520. The
`high Voltage generator 510, which includes a charge pump,
`receives a first voltage VCC1 (3.3V) and generates a high
`voltage (4.0V) at a VPP terminal. The switching unit 520
`includes an inverter 522 which receives a control Signal
`CNTL or a mode register signal MRS, and outputs an enable
`Signal to the high Voltage generator 510. The Switching unit
`520 further includes Switch 524 which connects a supplied
`second voltage VCC2 to the high voltage VPP terminal in
`response to the control Signal CNTL or the mode register
`signal MRS. The Switching unit 520 is thus responsive to the
`signal CNTL/MRS to generate the high voltage VPP by
`enabling the high Voltage generator 510 or by connecting the
`VPP terminal to the second voltage VCC2.
`Accordingly, in a low power mode, the memory device
`500 connects the second voltage VCC2 to the high voltage
`VPP terminal without operation of the high voltage genera
`tor 510. Since the charge pump of the high Voltage generator
`510 is not operated, power consumption is reduced in the
`low power mode.
`Referring to FIG. 6, a memory device 600 includes a high
`voltage generator 610 and a Switching unit 620. The high
`Voltage generator 610, which includes a charge pump,
`receives a first voltage VCC1 (3.3V) and generates a high
`voltage (4V) at a VPP terminal. The Switching unit 620
`includes an inverter 622 which receives a control Signal
`CNTL or a mode register signal MRS, and outputs an enable
`Signal to the high Voltage generator 610. The Switching unit
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 6,798,709 B2
`
`15
`
`25
`
`6
`620 further includes transistor 626 which connects a Sup
`plied second voltage VCC2 to the high voltage VPP terminal
`in response to the control Signal CNTL or the mode register
`signal MRS. The Switching unit 620 is thus responsive to the
`signal CNTL/MRS to generate the high voltage VPP by
`enabling the high Voltage generator 610 or by connecting the
`VPP terminal to the second voltage VCC2. Also, the Switch
`ing unit 620 primarily differs from that of the embodiment
`of FIG. 5 in that the Switching unit 620 is additional
`equipped with a level shifter 624. The level shifter 624
`receives the control Signal CNTL or the mode register Signal
`MRS, and outputs a predetermined voltage level (about
`VCC2+Vth, where Vth is a threshold voltage of transistor
`626). The transistor 626 of Switch 620 is turned on in
`response to the output of the level shifter 624 and the second
`voltage VCC2 is connected to the high voltage VPP termi
`nal. In this manner, the second voltage VCC2 is transmitted
`to the high voltage VPP terminal without loss of the thresh
`old voltage (Vth) of the transistor 626.
`In the drawings and Specification, there have been dis
`closed typical preferred embodiments of this invention and,
`although specific terms are employed, they are used in a
`generic and descriptive Sense only and not for purposes of
`limitation, the Scope of the present invention being Set forth
`in the following claims.
`What is claimed is:
`1. A memory device, comprising:
`a plurality of internal circuits which are operable at first
`and Second internal Voltages, wherein the first internal
`Voltage is less than the Second internal Voltage;
`a first power port for receiving a first power Supply
`Voltage,
`a Second power port for receiving a Second power Supply
`Voltage, wherein the first power Supply Voltage is less
`than the Second power Supply Voltage; and
`an internal Voltage generation circuit which is Selectively
`operable in either a first mode in which the second
`internal Voltage is generated from the first power Sup
`ply Voltage, or a Second mode in which the Second
`internal Voltage is generated from the Second power
`Supply Voltage.
`2. The memory device of claim 1, wherein the internal
`Voltage generation circuit is responsive to an externally
`Supplied control Signal to Select one of the first and Second
`modes.
`3. The memory device of claim 1, further comprising a
`mode register Set, wherein the internal Voltage generation
`circuit is responsive to the mode register Set to Select one of
`the first and Second modes.
`4. The memory device of claim 1, wherein the internal
`Voltage generation circuit is responsive to the absence of the
`Second power Supply Voltage on the Second power port to
`Select the first mode, wherein the Voltage generation circuit
`is responsive to the presence of the Second power Supply
`Voltage on the Second power port to Select the Second mode.
`5. The memory device of claim 1, wherein the internal
`Voltage generation circuit comprises:
`a Voltage generator circuit which is enabled in the first
`mode and disabled in the Second mode, and which
`increases the first power Supply Voltage to the Second
`internal Voltage when enabled; and
`a Switching circuit which is open in the first mode and
`closed in the Second mode, and which outputs the
`Second power Supply Voltage as the Second internal
`Voltage when closed.
`6. The memory device of claim 5, wherein the voltage
`generator circuit is enabled and disabled, and the Switching
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 10
`
`

`

`US 6,798,709 B2
`
`7
`circuit is opened and closed, in response to an externally
`Supplied control Signal.
`7. The memory device of claim 5, further comprising a
`mode register Set, wherein the Voltage generator circuit is
`enabled and disabled, and the Switching circuit is opened
`and closed, in response to an output of the mode register Set.
`8. The memory device of claim 5, wherein the voltage
`generator circuit is a charge pump.
`9. The memory device of claim 6, wherein the Switching
`circuit is comprised of a transistor and a Voltage shifter, and
`wherein the Voltage shifter increases a Voltage of the exter
`nally Supplied control Signal and applies the increased
`Voltage to a gate of the transistor.
`10. The memory device of claim 7, wherein the Switching
`circuit is comprised of a transistor and a Voltage shifter, and
`wherein the Voltage shifter increases a Voltage of the output
`of the mode register Set and applies the increased Voltage to
`a gate of the transistor.
`11. The memory device of claim 5, wherein the internal
`Voltage generation circuit is operable in both the first and
`Second modes to generate the first internal Voltage from the
`first power Supply Voltage.
`12. The memory device of claim 1, wherein the internal
`Voltage generation circuit comprises:
`a first Voltage generator circuit which is enabled in the
`first mode and disabled in the second mode, and which
`increases the first power Supply Voltage to the Second
`internal Voltage when enabled; and
`a Second Voltage generator circuit which is enabled in the
`Second mode and disabled in the first mode, and which
`increases or decreases the Second power Supply Voltage
`to the Second internal Voltage when enabled.
`13. The memory device of claim 12, wherein the first and
`Second Voltage generator circuits are enabled and disabled in
`response to an externally Supplied control Signal.
`14. The memory device of claim 12, further comprising a
`mode register Set, wherein the first and Second Voltage
`generator circuits are enabled and disabled in response to the
`mode register Set.
`15. The memory device of claim 12, wherein the first
`Voltage generator circuit is a charge pump.
`16. The memory device of claim 15, wherein the second
`Voltage generator is either a down converter or a charge
`pump.
`17. The memory device of claim 12, wherein the internal
`Voltage generation circuit is operable in both the first and
`Second modes to generate the first internal Voltage from the
`first power Supply Voltage.
`18. A memory System comprising:
`a Voltage regulator which generates a first power Supply
`Voltage from a Second power Supply Voltage, wherein
`the Second power Supply Voltage is greater than the first
`power Supply Voltage,
`a memory device comprising (a) a plurality of internal
`circuits which are operable at first and Second internal
`
`1O
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`8
`Voltages, wherein the first internal Voltage is less than
`the Second internal voltage, (b) a first power port for
`receiving the first power Supply voltage, (c) a second
`power port for receiving the Second power Supply
`Voltage, and (d) an internal voltage generation circuit
`which is selectively operable in either a first mode in
`which the Second internal Voltage is generated from the
`first power Supply Voltage, or a Second mode in which
`the Second internal Voltage is generated from the Sec
`ond power Supply Voltage, and
`a control circuit which controls an operation of the
`memory device.
`19. The memory system of claim 18, wherein the internal
`Voltage generation circuit is responsive to a control Signal
`Supplied from the control circuit to Select one of the first and
`Second modes.
`20. The memory system of claim 18, wherein the memory
`device further comprises a mode register Set, wherein the
`internal Voltage generation circuit is responsive to the mode
`register Set to Select one of the first and Second modes.
`21. A memory System comprising:
`a first voltage regulator which generates a first power
`Supply Voltage from a Second power Supply Voltage,
`wherein the Second power Supply Voltage is greater
`than the first power Supply Voltage;
`a Second Voltage regulator which generates a third power
`Supply Voltage from the Second power Supply Voltage,
`wherein the third power Supply Voltage is less than the
`Second power Supply Voltage and greater than the first
`power Supply Voltage,
`a memory device comprising (a) a plurality of internal
`circuits which are operable at first and Second internal
`Voltages, wherein the first internal Voltage is less than
`the Second internal voltage, (b) a first power port for
`receiving the first power Supply voltage, (c) a second
`power port for receiving the third power Supply
`Voltage, and (d) an internal voltage generation circuit
`which is selectively operable in either a first mode in
`which the Second internal Voltage is generated from the
`first power Supply Voltage, or a Second mode in which
`the Second internal Voltage is generated from the third
`power Supply Voltage, and
`a control circuit which controls an operation of the
`memory device.
`22. The memory system of claim 21, wherein the internal
`Voltage generation circuit is responsive to a control Signal
`Supplied from the control circuit to Select one of the first and
`Second modes.
`23. The memory system of claim 21, wherein the memory
`device further comprises a mode register Set, wherein the
`internal Voltage generation circuit is responsive to the mode
`register Set to Select one of the first and Second modes.
`
`k
`
`k
`
`k
`
`k
`
`k
`
`Samsung Electronics Co., Ltd.
`Ex. 1034, p. 11
`
`