I, Julie Carlson, declare as follows:
`
`1.
`
`I have personal knowledge of the facts set forth herein, and if called to
`
`testify, I could and would competently testify to the same.
`
`2.
`
`I have been involved in semiconductor standardization and
`
`publication services for over twenty years. For nearly all of this time, I have
`
`worked at JEDEC, a standards-setting organization for the microelectronics
`
`industry, to edit, publish, and maintain JEDEC business records and standards
`
`developed by its numerous committees and subcommittees.
`
`3.
`
`I have been involved with the standardization and publication
`
`activities of JEDEC continuously since 1997. I was the Manager of Standards and
`
`Publications at JEDEC from February 1997 through June 2005. Since June 2005, I
`
`have continued to work for JEDEC as a Consultant where my responsibilities
`
`include the maintenance and publication of JEDEC documents and standards. In
`
`addition, I am familiar with JEDEC’s historical record-keeping and publication
`
`practices since at least 1992, based on my review of JEDEC’s business records
`
`since that time and my regular discussions with JEDEC employees and members.
`
`4.
`
`For over 50 years, JEDEC has been the global leader in developing
`
`and publishing open standards for the microelectronics industry. JEDEC’s
`
`membership consists of more than 3,000 volunteers representing nearly 300
`
`1
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 1
`
`

`

`member companies, and includes key technical individuals from most device,
`
`assembly, system and testing companies. JEDEC publications and standards are
`
`adopted worldwide. JEDEC is accredited by ANSI and maintains liaisons with
`
`numerous standards bodies throughout the world.
`
`5.
`
`Since at least 2000, JEDEC standards have been publicly available for
`
`download from the JEDEC website (https://www.jedec.org), where they are
`
`cataloged and indexed by keyword and technological subject matter. By 2000, the
`
`JEDEC website was publicly available and commonly used by manufactures,
`
`companies in the microelectronics industry, and other interested parties to access
`
`and obtain standards information pertaining to that industry. Anyone interested can
`
`join JEDEC online, at JEDEC.org.
`
`6.
`
`This declaration concerns two JEDEC standards. The first standard is
`
`JEDEC STANDARD, FBDIMM: Advanced Memory Buffer (AMB), JESD82-20
`
`(March 2007) (hereinafter, “JESD82-20 Standard”), which is a standard published
`
`by JEDEC. I have reviewed the JESD82-20 Standard. The copy of the JESD82-
`
`20 Standard attached to this declaration as Exhibit A is identical to the copy of the
`
`JESD82-20 Standard in JEDEC’s files. The second standard is JEDEC
`
`STANDARD, FBDIMM Specification: DDR2 SDRAM Fully Buffered DIMM
`
`(FBDIMM) Design Specification, JESD205 (March 2007) (hereinafter, “JESD205
`
`Standard”), which is a standard published by JEDEC. I have reviewed the
`
`2
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 2
`
`

`

`JESD205 Standard. The copy of the JESD205 Standard attached to this
`
`declaration as Exhibit B is identical to the copy of the JESD205 Standard in
`
`JEDEC’s files.
`
`7.
`
`The following statements on the public availability of the JESD82-20
`
`Standard and the JESD205 Standard as of March 2007 are based on personal
`
`knowledge. The development of all JEDEC documents follows the process set
`
`forth in JM21: JEDEC Manual of Organization and Procedure. According to that
`
`process, the date on the cover of a JEDEC document is the month the document
`
`was finalized, approved by legal, and posted to the website. For both the JESD82-
`
`20 Standard and the JESD205 Standard, the date on the cover (and thus the date it
`
`was posted to JEDEC’s website) is March 2007.
`
`8.
`
`I am familiar with the circulation and publication procedures used by
`
`JEDEC. Upon approval of the Board of Directors, the JEDEC publications
`
`department prepares documents for publication, and seeks final review and
`
`approval to publish from the JEDEC legal department. Once legal approval is
`
`received, the JEDEC publications department uploads the approved document to
`
`the JEDEC website with a brief description. An email announcement is then sent
`
`to the sponsoring committee and any approved resellers. By 2000, JEDEC made
`
`its published standards available for download from www.jedec.org, as mentioned
`
`above.
`
`3
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 3
`
`

`

`9.
`
`Based on my personal knowledge of JEDEC’s policies, both the
`
`JESD82-20 Standard and the JESD205 Standard were made publicly available in
`
`March 2007 for download from the JEDEC website (https://www.jedec.org),
`
`consistent with the dates on the cover pages of the JESD82-20 Standard and the
`
`JESD205 Standard. My knowledge of the procedures surrounding the creation of
`
`the date notation and publication is based on JEDEC’s policies and practices as I
`
`understand them through my work at JEDEC. I rely on these policies and practices
`
`in the course of my work. I have no reason to believe that JEDEC’s typical
`
`practice was not followed. I have no reason to believe that the JESD82-20
`
`Standard and the JESD205 Standard were not made publicly accessible in March
`
`2007.
`
`10.
`
`To further confirm my statements above, I have visited the Internet
`
`Archive to look at the first capture of the online catalog at www.jedec.org after
`
`March 2007 that contained both the JESD82-20 Standard and the JESD205
`
`Standard, which occurred on October 21, 2007:
`
`<http://web.archive.org/web/20071021053839/http://www.jedec.org:80/Catalog/di
`
`splay.cfm>. A printout of this capture is attached as Exhibit C and is consistent
`
`with my personal recollection of the JEDEC website. As can be seen from this
`
`capture on October 21, 2007, the JESD82-20 Standard was cataloged as “JESD 82-
`
`20,” indexed under the “CMOS Digital Logic” technical subject matter and under
`
`4
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 4
`
`

`

`the keywords “Advanced Memory Buffer,” “AMB,” “AMB Component
`
`Specification,” “DDR2,” “FB-DIMM,” “FBD,” and “FBDIMM,” and was
`
`available to the public by that date, consistent with my statements above. See
`
`Exhibit C at pages 41, 91, 95, 103, 107, 108. As can also be seen from this capture
`
`on October 21, 2007, the JESD205 Standard was cataloged as “JESD 205,”
`
`indexed under the “Fully Buffered DIMM’s” technical subject matter and under
`
`the keywords “Advanced Memory Buffer,” “AMB,” “FB-DIMM,” “FBD,”
`
`“FBDIMM,” and “Fully Buffered DIMM,” and was available to the public by that
`
`date, consistent with my statements above. See Exhibit C at pages 50, 94, 95, 107,
`
`110.
`
`11.
`
`Exhibit D is a printout of
`
`<http://web.archive.org/web/20070401184420/http://www.jedec.org:80/service_m
`
`embers/New_Members/memberco.cfm>, which is a capture on April 1, 2007, of
`
`the list of member companies on JEDEC’s website as of that date, which is
`
`consistent with my personal recollection of JEDEC’s membership. All of those
`
`member companies would have had access to both the JESD82-20 Standard and
`
`the JESD205 Standard attached as Exhibits A and B, respectively, no later than
`
`that date.
`
`5
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 5
`
`

`

`I, Julie Carlson, do hereby declare and state, that all statements made herein of my
`
`own knowledge are true and that all statements made on information and belief are
`
`believed to be true; and further that these statements were made with the knowledge
`
`that willful false statements and the like so made are punishable by fine or
`
`imprisonment, under Section 1001 of Title 18 of the United States Code.
`
`Executed on ___________
`3/25/2022
`
`
`
`___________________________________
`Julie D. Carlson
`Julie D. Carlson
`
`6
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 6
`
`

`

`Exhibit A
`Exhibit A
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 7
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 7
`
`

`

`JEDEC
`STANDARD
`
`FBDIMM:
`Advanced Memory Buffer (AMB)
`
`JESD82-20
`
`MARCH 2007
`
`SPECIAL DISCLAIMER: JEDEC has received information that
`certain patents or patent applications may be relevant to this
`standard, and, as of the publication date of this standard, no
`statements regarding an assurance or refusal to license such
`patents or patent applications have been provided.
`
`http://www.jedec.org/download/search/FBDIMM/Patents.xls
`
`JEDEC does not make any determination as to the validity or
`relevancy of such patents or patent applications. Prospective
`users of the standard should act accordingly.
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 8
`
`

`

`
`NOTICE
`
`JEDEC standards and publications contain material that has been prepared, reviewed, and approved
`through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC
`legal counsel.
`
`JEDEC standards and publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchasers, facilitating interchangeability and
`improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay
`the proper product for use by those other than JEDEC members, whether the standard is to be used
`either domestically or internationally.
`
`JEDEC standards and publications are adopted without regard to whether or not their adoption may
`involve patents or articles, materials, or processes. By such action JEDEC does not assume any
`liability to any patent owner, nor does it assume any obligation whatever to parties adopting the
`JEDEC standards or publications.
`
`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer viewpoint.
`Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may
`be further processed and ultimately become an ANSI standard.
`
`No claims to be in conformance with this standard may be made unless all requirements stated in the
`standard are met.
`
`Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication
`should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org
`
`Published by
`©JEDEC Solid State Technology Association 2007
`2500 Wilson Boulevard
`Arlington, VA 22201-3834
`
`This document may be downloaded free of charge; however JEDEC retains the
`copyright on this material. By downloading this file the individual agrees not to
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`
`PRICE: Please refer to the current
`Catalog of JEDEC Engineering Standards and Publications online at
`http://www.jedec.org/Catalog/catalog.cfm
`
`
`Printed in the U.S.A.
`All rights reserved
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 9
`
`

`

`
`
`
`
`
`
`
`
`
`PLEA SE!
`
`D O N ’T V IO LA TE
`TH E
`LA W !
`
`This docum ent is copyrighted by the JED EC Solid State Technology A ssociation
`and m ay not be reproduced w ithout perm ission.
`
`O rganizations m ay obtain perm ission to reproduce a lim ited num ber of copies
`through entering into a license agreem ent. For inform ation, contact:
`
`JED EC Solid State Technology A ssociation
`2500 W ilson Boulevard
`A rlington, V irginia 22201-3834
`or call (703) 907-7559
`
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`
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`
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`
`
`
`
`
`
`
`
`
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 10
`
`

`

`Special Disclaimer
`
`JEDEC has received information that certain patents or patent
`applications may be relevant to this standard, and, as of the
`publication date of this standard, no statements regarding an
`assurance or refusal to license such patents or patent applications
`have been provided.
`
`
`
`
`
`
`http://www.jedec.org/download/search/FBDIMM/Patents.xls
`
`JEDEC does not make any determination as to the validity or
`relevancy of such patents or patent applications. Prospective users
`of the standard should act accordingly.
`
`
`§
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 11
`
`

`

`JEDEC Standard No. 82-20
`
` Table of Contents
`Table of Contents ............................................................................................................................. i
`
`List of Tables ................................................................................................................................... v
`
`List of Figures ................................................................................................................................ vii
`
`1
`
`2
`
`3
`
`Introduction.........................................................................................................................1
`Advanced Memory Buffer Overview.............................................................................1
`Advanced Memory Buffer Functionality .......................................................................1
`1.2.1
`Advanced Memory Buffer ......................................................................................1
`1.2.2
`Transparent Mode for DRAM Test Support...........................................................1
`1.2.3 Debug and Logic Analyzer Interface .....................................................................2
`1.2.4 DDR SDRAM.........................................................................................................2
`Advanced Memory Buffer Block Diagram ....................................................................2
`Interfaces .....................................................................................................................4
`1.4.1
`FBD High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces ..................4
`1.4.2 DDR2 Channel ......................................................................................................4
`1.4.3
`SMBus Slave Interface ..........................................................................................4
`References...................................................................................................................5
`Glossary.......................................................................................................................5
`FBD Channel Interface .......................................................................................................9
`Advanced Memory Buffer Support for FBD Operating Modes .....................................9
`Channel Initialization ....................................................................................................9
`Channel Protocol..........................................................................................................9
`2.3.1 General..................................................................................................................9
`2.3.2
`Timeouts during TS0 .............................................................................................9
`2.3.3 Recalibrate state considerations ...........................................................................9
`2.3.4
`Address Mapping of DDR Commands to DRAMs ...............................................11
`2.3.5
`FBD L0s State .....................................................................................................11
`Reliability, Availability, and Serviceability...................................................................12
`2.4.1 General................................................................................................................12
`2.4.2 Channel Error Detection and Logging .................................................................12
`Channel Configuration ...............................................................................................12
`2.5.1 Re-sync and Resample Modes ...........................................................................12
`2.5.2 Other Channel Configuration Modes ...................................................................13
`2.5.3
`Lane to Lane Skew on a Channel .......................................................................13
`Repeater Mode ..........................................................................................................13
`Performance...............................................................................................................14
`2.7.1
`Idle Memory Read Latency..................................................................................14
`AMB Components of Channel Latency ......................................................................15
`2.8.1 Command to Data Delay Calculation...................................................................15
`2.8.2 Channel Throughput............................................................................................18
`DDR Interface...................................................................................................................19
`Advanced Memory Buffer DDR Interface Overview...................................................19
`Data Mapping.............................................................................................................19
`3.2.1 Data Mask ...........................................................................................................19
`Command / Address Outputs.....................................................................................20
`3.3.1 CKE Output Control.............................................................................................21
`3.3.2 Memory Controller / BIOS requirements..............................................................21
`DQS IO and DM Outputs ...........................................................................................21
`
`1.1
`1.2
`
`1.3
`1.4
`
`1.5
`1.6
`
`2.1
`2.2
`2.3
`
`2.4
`
`2.5
`
`2.6
`2.7
`
`2.8
`
`3.1
`3.2
`
`3.3
`
`3.4
`
`-i-
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 12
`
`

`

`JEDEC Standard No. 82-20
`
`3.5
`
`3.6
`3.7
`
`3.8
`
`3.9
`
`4.1
`
`4.2
`
`4.3
`4.4
`
`4.5
`4.6
`4.7
`
`5.1
`
`5.2
`
`5.3
`5.4
`
`6.1
`
`Refresh.......................................................................................................................22
`3.5.1
`Self-Refresh During Channel Reset ....................................................................22
`3.5.2
`Automatic Refresh ...............................................................................................23
`Back to Back Turnaround Time..................................................................................23
`DDR Calibration .........................................................................................................24
`3.7.1 DRAM Initialization and (E)MRS..........................................................................24
`3.7.2
`Automatic DDR Bus Calibration...........................................................................25
`3.7.3
`S3 Recovery Configuration Registers..................................................................25
`3.7.4 Receive Enable Calibration .................................................................................26
`3.7.5 DQS Delay Calibration ........................................................................................26
`DDR MEMBIST ..........................................................................................................26
`3.8.1 MEMBIST Features .............................................................................................27
`DIMM Organization ....................................................................................................29
`Electrical, Power, and Thermal.........................................................................................31
`Electrical DC Parameters...........................................................................................31
`4.1.1
`Absolute maximum ratings ..................................................................................31
`4.1.2 Normal Mode .......................................................................................................32
`4.1.3
`S3 current Specification.......................................................................................39
`FBD Channel Interface...............................................................................................40
`4.2.1
`FBD Electrical Timing Specifications...................................................................40
`4.2.2
`AMB Latency Parameters....................................................................................40
`DDR2 DRAM Interface Electrical Specifications ........................................................45
`DDR2 Electrical Output Timing Specifications ...........................................................46
`4.4.1 Description of DQ/DQS Alignment.......................................................................46
`4.4.2 Description of ADD/CMD/CNTL Outputs.............................................................46
`4.4.3
`Test Load Specification .......................................................................................46
`4.4.4
`tDVA and tDVB Parameter Description ...............................................................46
`4.4.5
`tjit and tjitHP Parameter Description....................................................................47
`4.4.6
`tCVA, tCVB, tECVA and tECVB Parameter Description......................................47
`4.4.7
`tDQSCK Timing Parameter Description ..............................................................48
`4.4.8 DQ and CB (ECC) Setup/Hold Relationships to/from DQS (Read Operation) ....48
`4.4.9 Write Preamble Duration .....................................................................................49
`4.4.10 Write Postamble Duration....................................................................................49
`4.4.11 Advance Memory Buffer Component Electrical Timing Summary.......................50
`4.4.12 Reference DDR2 Interface Package Trace Lengths ...........................................52
` SMBUS Interface ......................................................................................................53
`Misc I/O (1.5 CMOS Driver) .......................................................................................53
`Thermal Diode and Analog to Digital Converter (ADC)..............................................53
`4.7.1
`Thermal Sensor Effects on the Advanced Memory Buffer’s Functional Behavior54
`Error Handling ..................................................................................................................55
`Types of Errors and Responses.................................................................................55
`5.1.1
`FBD Link Errors ...................................................................................................55
`5.1.2 DDR Errors ..........................................................................................................56
`5.1.3 Host Protocol Errors ............................................................................................56
`5.1.4 Other Errors.........................................................................................................57
`Error Logging .............................................................................................................58
`5.2.1
`Error Logging Procedure .....................................................................................58
`Fail Over Mode Support .............................................................................................58
`Failback to Pass-Thru ................................................................................................58
`Transparent Mode ............................................................................................................59
`Transparent Mode......................................................................................................59
`
`4
`
`5
`
`6
`
`-ii-
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 13
`
`

`

`JEDEC Standard No. 82-20
`
`6.2
`
`7.1
`
`8.1
`8.2
`8.3
`8.4
`8.5
`8.6
`8.7
`8.8
`
`8.9
`
`9.1
`
`Block Diagram .....................................................................................................59
`6.1.1
`Transparent Mode Signal Definitions ..................................................................60
`6.1.2
`Transparent Mode to FBD Pin Mapping ..............................................................60
`6.1.3
`6.1.4 Clock Frequency and Core Timing ......................................................................61
`6.1.5
`Transparent mode timing.....................................................................................61
`6.1.6
`Error reporting .....................................................................................................66
`6.1.7
`Transparent mode IO specifications....................................................................68
`6.1.8
`IO implementation guidelines ..............................................................................69
`Transparent Mode Control and Status Registers.......................................................70
`SMBus Interface ...............................................................................................................71
`System Management Access.....................................................................................71
`7.1.1
`SMBus 2.0 Specification Compatibility ................................................................71
`7.1.2
`Supported SMBus Commands ............................................................................71
`7.1.3
`FBD AMB Register Access Protocols..................................................................72
`7.1.4
`SMBus Error Handling.........................................................................................75
`7.1.5
`SMBus Resets.....................................................................................................75
`Clocking............................................................................................................................77
`Advanced Memory Buffer Clock Domains .................................................................77
`PLL Clocks .................................................................................................................77
`Reference Clock.........................................................................................................77
`FBD Lane Frame Clocks............................................................................................77
`Clock Ratios ...............................................................................................................77
`DDR DRAM Clock Support ........................................................................................78
`Clock Pins ..................................................................................................................78
`. PLL Requirements ...................................................................................................78
`8.8.1
`Jitter.....................................................................................................................78
`8.8.2
`PLL Bandwidth Requirements .............................................................................79
`8.8.3
`External Reference..............................................................................................79
`8.8.4
`Spread Spectrum Support ...................................................................................79
`Analog Power Supply Pins.........................................................................................79
`Pin Descriptions................................................................................................................81
`Pin Description ...........................................................................................................81
`Reset ................................................................................................................................85
`10.1
`Introduction ................................................................................................................85
`10.2
`Platform Reset Functionality ......................................................................................85
`10.2.1 Platform RESET# Requirements.........................................................................85
`10.2.2 Advanced Memory Buffer RESET# Requirements..............................................85
`10.2.3 Power-Up and Suspend-to-RAM Considerations ................................................86
`10.3
`Reset Types...............................................................................................................86
`10.4
`Pads Controlling Reset ..............................................................................................86
`10.4.1 RESET# Pad .......................................................................................................86
`10.4.2 Primary FBD Link ................................................................................................86
`10.5
`Details ........................................................................................................................86
`10.5.1 Cold Power-Up Reset Sequence.........................................................................86
`10.6
`Timing Diagrams ........................................................................................................88
`10.7
`I/O Initialization...........................................................................................................88
`10.7.1 FBD Channel Initialization ...................................................................................88
` Registers .........................................................................................................................89
`11.1
`Access Mechanisms ..................................................................................................89
`
`7
`
`8
`
`9
`
`10
`
`11
`
`-iii-
`
`Samsung Electronics Co., Ltd.
`Ex. 1029, p. 14
`
`

`

`JEDEC Standard No. 82-20
`
`11.1.1 Conflict Resolution and Usage Model Limitations ...............................................89
`11.1.2 FBD Data on Configuration Read Returns ..........................................................89
`11.1.3 Non-Existent Register Bits...................................................................................89
`11.1.4 Register Attribute Definition.................................................................................90
`11.1.5 Binary Number Notation ......................................................................................90
`11.1.6 Function Mapping ................................................................................................90
`11.2
`PCI Standard Header Identification Registers (Function 0) .......................................99
`11.2.1 VID: Vendor Identification Register .....................................................................99
`11.2.2 DID: Device Identification Register....................................................................100
`11.2.3 RID: Revision Identification Register .................................................................100
`11.2.4 CCR: Class Code Register................................................................................100
`11.2.5 HDR: Header Type Register..............................................................................101
`11.3
`FBD Link Registers (Function 1) ..............................................................................101
`11.3.1 FBD Link Control and Status .............................................................................101
`11.3.2 Error Registers ..................................................................................................115
`11.3.3 PERSONALITY BYTES loaded from the SPD ..................................................117
`11.3.4 Advanced Memory Buffer Hardware Configuration Registers...........................119
`11.4
`Implementation Specific FBD Registers (Function 2) ..............................................121
`11.5
`DDR and Miscellaneous Registers (Function 3) ......................................................121
`11.5.1 Memory BIST Registers ....................................................................................121
`11.5.2 Memory Registers .............................................................................................130
`11.5.3 Thermal Sensor Registers.................................................................................136
`11.6
`Implementation Specific DDR Initialization and Calibration Registers (Function 4).139
`11.6.1 DDR Calibration.................................................................................................139
`11.7
`DFX Registers (Function 5)......................................................................................142
`11.7.1 Transparent Mode Registers ......................