US007724.604B2
`
`(12) United States Patent
`Amidi et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,724,604 B2
`May 25, 2010
`
`(54) CLOCK AND POWER FAULT DETECTION
`FOR MEMORY MODULES
`
`(75) Inventors: Mike H. Amidi, Lake Forest, CA (US);
`Satyadev Kolli, Milpitas, CA (US)
`
`(73) Assignee: SMART Modular Technologies, Inc.,
`N k, CA (US
`eWarK,
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 702 days.
`
`(*) Notice:
`
`5,495,435 A * 2/1996 Sugahara ..................... 365,52
`5,798.961 A * 8/1998 Heyden et al. ................ 365,52
`7,139.937 B1 * 1 1/2006 Kilbourne et al. ............. T14? 47
`7,143,298 B2 * 1 1/2006 Wells et al. ................. T13,300
`7.224,595 B2 *
`5/2007 Dreps et al. ................... 365.63
`2006/01 17152 A1* 6/2006 Amidi et al. ................ T11 154
`
`* cited by examiner
`Primary Examiner Dang TNguyen
`Assistant Examiner—Alexander Sofocleous
`(74) Attorney, Agent, or Firm Perkins Coie LLP
`
`(22) Filed:
`(65)
`
`Oct. 25, 2006
`Prior Publication Data
`
`May 1, 2008
`
`US 2008/O1 O1147 A1
`(51) Int. Cl
`(2006.01)
`Gic 5/14
`3.65/22936.5/51: 36.5/226.
`(52) U.S. Cl.
`"6s2 11.71 1/115. 71 1/154
`58) Field of Classification S
`h s
`s 36.5/228
`65 t
`g Stars 3 3.1.233.11. 711/10 5.
`(58) Fie
`s a us al- as
`s
`• us
`7 11 f1151 54
`1
`lication file f
`hhi
`s
`S
`ee application file for complete search history.
`References Cited
`U.S. PATENT DOCUMENTS
`
`(56)
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`A system, method and apparatus for clock and power fault
`detection for a memory module is provided. In one embodi
`ment, a system is provided. The system includes a Voltage
`detection circuit and a clock detection circuit. The system
`further includes a controller coupled to the voltage detection
`circuit and the clock detection circuit. The system also
`includes a memory control State machine coupled to the con
`troller. The system includes volatile memory coupled to the
`memory control state machine. The system further includes a
`battery and battery regulation circuitry coupled to the con
`troller and the memory control state machine. The battery,
`battery regulation circuitry, volatile memory, memory control
`state machine, controller, clock detection circuit and voltage
`detection circuit are all collectively included in a unitary
`memory module.
`
`4,383,184. A *
`
`5/1983 McFarland ................... 307/66
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`22 Claims, 15 Drawing Sheets
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`Battery charging
`circuitry
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`490
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`report circuitry
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`Complex
`programmable
`logic device
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`Clock
`generator
`circuitry
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`360
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`Samsung Electronics Co., Ltd.
`Ex. 1024, p. 1
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`U.S. Patent
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`May 25, 2010
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`Sheet 9 Of 15
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`Sheet 10 of 15
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`U.S. Patent
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`US 7,724,604 B2
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`Ex. 1024, p. 13
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`U.S. Patent
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`May 25, 2010
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`Sheet 13 of 15
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`In the case of poweror clock— loss,
`do notinitiate clock and powerfault
`detection method mode
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`Ex. 1024, p. 15
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`U.S. Patent
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`May 25, 2010
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`Ex. 1024, p. 16
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`

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`1.
`CLOCK AND POWER FAULT DETECTION
`FOR MEMORY MODULES
`
`2
`FIG.15 illustrates an alternate embodiment of a process for
`monitoring clock and power for a memory module.
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`US 7,724,604 B2
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`BACKGROUND
`
`DETAILED DESCRIPTION
`
`10
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`15
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`A system, method and apparatus is provided for a clock and
`power fault detection for a memory module. The specific
`embodiments described in this document represent examples
`or embodiments of the present invention, and are illustrative
`in nature rather than restrictive.
`Clock and power fault detection for a memory module may
`be provided in a variety of ways. For example, one may
`provide a system with a controller which detects voltage
`levels and clock signals, a state machine for operating a
`memory in backup mode, and a battery and Supporting cir
`cuitry for Supplying backup power. Similarly, one may pro
`vide a process which operates to detect Voltage and clock
`signals, initiate backup operations, maintain memory
`(through refresh, for example), and detect a recovery status.
`Providing Such a system or process within a memory module
`can be very helpful, as it avoids the need for system circuitry
`in a computer system or similar device which can maintain a
`memory module from outside the module. Moreover, such a
`system or process may be tuned to the specific memory mod
`ule, instead of requiring overhead to deal with many different
`types of memory modules, for example.
`In one embodiment, a system is provided. The system
`includes a Voltage detection circuit and a clock detection
`circuit. The system further includes a controller coupled to
`the Voltage detection circuit and the clock detection circuit.
`The system also includes a memory control state machine
`coupled to the controller. The system includes volatile
`memory coupled to the memory control State machine. The
`system further includes a battery and battery regulation cir
`cuitry coupled to the controller and the memory control state
`machine. The battery, battery regulation circuitry, volatile
`memory, memory control state machine, controller, clock
`detection circuit and Voltage detection circuit are all collec
`tively included in a unitary memory module.
`In the following description, for purposes of explanation,
`numerous specific details are set forth in order to provide a
`thorough understanding of the invention. It will be apparent,
`however, to one skilled in the art that the invention can be
`practiced without these specific details. In other instances,
`structures and devices are shown in block diagram form in
`order to avoid obscuring the invention.
`Reference in the specification to “one embodiment” or “an
`embodiment’ means that a particular feature, structure, or
`characteristic described in connection with the embodiment
`is included in at least one embodiment of the invention. The
`appearances of the phrase “in one embodiment in various
`places in the specification are not necessarily all referring to
`the same embodiment, nor are separate or alternative embodi
`ments mutually exclusive of other embodiments. Features
`and aspects of various embodiments may be integrated into
`other embodiments, and embodiments illustrated in this
`document may be implemented without all of the features or
`aspects illustrated or described.
`FIG. 1 illustrates an embodiment of a computer. Computer
`100 is a machine which includes some of the elements typi
`cally found in various types of computers. Such as desktop or
`laptop computers, personal digital assistants, or server com
`puters, for example. Not shown are some common Sub
`systems, such as a graphics accelerator or other video Sub
`system, for example.
`Computer 100 includes a processor 104 (such as a central
`processing unit) with a cache 108 coupled thereto. Host bus
`
`Computer systems operate in part using Volatile memory.
`Memory modules with Random Access Memory typically
`will not retain any data when power is not supplied. Such
`memory modules require power to maintain values which are
`stored in memory cells, and may also require periodic refresh
`of contents of memory cells. This differs from non-volatile
`memory such as various forms of Read Only Memory or other
`memory such as magnetic or optical memory. However,
`whereas non-volatile memory tends to have long-term Stor
`age capacity, it also tends to be slower, with read-only
`memory of various types often copied into Volatile random
`access memory during operation of computers and similar
`machines.
`AS Systems become more mission critical, the possibility of
`irreplaceable data being stored in Volatile memory increases.
`Similarly, failure analysis can be much simpler if information
`about the state of a system is available after a failure occurs.
`Moreover, some data may be useful for restarting a system
`after a failure, even though that information is not otherwise
`Vital for external purposes. Also, Some data may simply be
`desirable for retention purposes, but may also be most useful
`in Volatile memory.
`Thus, it may be useful to provide an option for keeping data
`in Volatile memory even when a surrounding system loses
`power. Moreover, it may also be useful to keep data in volatile
`memory when a Surrounding system suffers some form of an
`error which causes a clock to malfunction even though power
`is still supplied. Likewise, it may be useful to provide volatile
`memory which has non-volatile characteristics in short- or
`medium-term time periods.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The present invention is illustrated by way of example in
`the accompanying drawings. The drawings should be under
`stood as illustrative rather than limiting.
`FIG. 1 illustrates an embodiment of a computer.
`FIG. 2 illustrates an embodiment of a memory interface in
`a computer.
`FIG. 3 illustrates an embodiment of a top side of an unbuf
`fered clocked memory module.
`FIG. 4 illustrates an embodiment of a back or bottom side
`of an unbuffered clocked memory module.
`FIG. 5 illustrates an embodiment of a power management
`block.
`FIG. 6 illustrates an embodiment of the internals of a power
`management block.
`FIG. 7 illustrates an embodiment of a power switch multi
`plexer.
`FIG. 8 illustrates an embodiment of a voltage supervisory
`system.
`FIG. 9 illustrates an embodiment of clock circuitry.
`FIG.10 illustrates an embodiment of a processor system on
`a chip.
`FIG. 11 illustrates an embodiment of a state machine.
`FIG. 12 illustrates an embodiment of a memory control
`system.
`FIG. 13 illustrates an embodiment of a truth table.
`FIG. 14 illustrates an embodiment of a process of control
`ling power Supply and clock signals to a memory system.
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`3
`112 provides for an interface between processor 104 and
`components such as external cache 116, host-to-PCI bridge
`120 and other similar components. External cache 116 may
`provide for additional caching resources, such as a level two
`cache, for example. Host-to-PCI bridge 120 may provide a
`bridge to a PCI bus 128, and may also provide a datapath to a
`memory controller 124, for example. Thus, bridge 120 may
`serve as a memory hub, for example. Memory controller 124
`controls access to memory modules in sockets 184, 188, 192
`and 196.
`PCI bus 128 provides an interface with still more compo
`nents of the computer 100. Coupled to PCI bus 128 are
`PCI-to-ISA bridge 132 and Ethernet card 144. Bridge 132
`provides a bus bridge to ISA bus 152, and provides a datapath
`to components such as IDE storage subsystem 136 and USB
`interface 140, along with Ethernet card 144 and modem 148.
`ISA bus 152 provides a datapath to BIOS 156, parallel port
`160, serial port 164, infrared port 168, keyboard 172, mouse
`176 and floppy drive 180. As one may expect, other compo
`nents may be included and many of the components illus
`trated (such as the floppy disk 180 for example) may be
`omitted from Some embodiments.
`Memory sockets such as sockets 184, 188, 192 and 196
`may be populated with various types of memory modules.
`FIG. 2 illustrates an embodiment of a memory interface in a
`computer. The memory interface 200 provides for communi
`cation between a processor 210 and a memory module 230.
`Processor 210 provides control signals and (potentially) data
`to memory controller 220. Controller 220 then provides con
`trol signals to memory module 230. Thus, controller 220
`handles the sometimes complicated process of signaling
`module 230, providing address, control and command signals
`at the right times for the memory module 230, and either
`providing or receiving data and DQS signals as necessary.
`Similar address, control and command signals are provided
`by the processor 210 to the controller 220, but may not be
`provided with the timing required for module 230. In syn
`chronous systems, oscillator 250 and clock synthesizer 240
`provide clock signals to the various components.
`With a memory system in place, a memory module must be
`supplied as part of the system. FIG. 3 illustrates an embodi
`ment of a top side of an unbuffered clocked memory module.
`Memory in general is typically SDRAM synchronous
`dynamic random access memory, which is Volatile. If a
`memory system gets interrupted too much, the data stored in
`SDRAM can be lost. Thus, memory module 300 may be used
`as part of a system which maintains some of the data in
`SDRAM.
`In one embodiment, memory module 300 includes a
`memory card (e.g. a printed circuit board), memory chips,
`series termination resistors, PLL (Phase-Lock-Loop) and
`SPD (Serial Presence Detect) components, and a card inter
`face. Memory card 310 provides the base for the memory
`module 300, and provides traces for conductivity between
`components. Mounted on memory card 310 are memory
`chips 320 (320A-I as illustrated) and resistors 330 (330A-I as
`illustrated). Also provided are a PLL 340 and an SPD module
`350. Furthermore, some of the traces or conductors of
`memory card 310 connect to card interface 360, a set of
`printed conductors on an edge of the card which may mate
`with a slot or socket on a card to which memory module 300
`is connected. Thus, the front side of memory card 310 basi
`cally includes the memory components.
`The back side of memory card 310 may contain other
`components. FIG. 4 illustrates an embodiment of a back or
`bottom side of an unbuffered clocked memory module. The
`module is provided with clock and power fault detection
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`capabilities. Card interface 360 is present on this side as well,
`providing connectivity. Also included is an array of LDOS
`410, providing power regulation, a CPLD (Complex Pro
`grammable Logic Device) 420, providing logic Such as a state
`machine, a battery module 470, a logic signal multiplexer
`array 450, providing Switching capabilities for logic signals,
`a processor 440, providing a processor system on a chip, and
`a clock generator module 430, providing clock signals. Bat
`tery module 470 includes a battery 475, power supervisory
`module 480, battery charging circuitry 485 and battery status
`circuitry 490. Where it seems apparent that further descrip
`tion is needed, embodiments of these components are illus
`trated and described below.
`Part of a memory module is typically a power management
`block. FIG. 5 illustrates an embodiment of a power manage
`ment block. Power management block 500 includes the actual
`power management module 510, an incoming system Supply
`520, an incoming battery supply 530, and an outgoing
`memory power supply 540. Power management block 500
`may thus be used to attempt to ensure a stable power Supply
`even in the face of disruptions in system supply 520, for
`example.
`While a power management block 500 may be imple
`mented in a variety of ways, power management block 600
`provides one example of Such an implementation. FIG. 6
`illustrates an embodiment of the internals of a power man
`agement block. System supply 605 provides a system power
`supply to a boost power converter 610 and a power switch
`multiplexer 655.
`Boost converter 610 provides a power output 615 which
`powers battery charger 620 which in turn supplies battery
`630. If necessary, discharge circuitry 635 can discharge bat
`tery 630 on a command from a microprocessor. Moreover, gas
`gauge 645 can interpret battery output 625 to determine a
`rough charge status of battery 630. Additionally, battery out
`put 625 is provided to boost converter 680 to produce power
`supply 685 and boost/buck converter 690 to produce power
`supply 695. Also, battery output 625 provides power to buck
`converter 640 (when enabled by battery enable signal 670)
`which produces battery power 650 as an input to power switch
`multiplexer 655. Thus, power switch multiplexer 655 may
`switch between battery power 650 and system supply 605
`based on a signal 670.
`Signal 670 is controlled by voltage supervisory block 665,
`which receives system supply 605 and a reference voltage
`675, and compares the two. If system supply 605 has a greater
`magnitude than reference voltage 675, signal 670 causes
`power switch multiplexer 655 to choose system supply 605 as
`a source for memory supply 660. If system supply 605 has a
`magnitude lower than reference voltage 675, then signal 670
`causes power switch multiplexer 655 to choose battery power
`650 for memory supply 660. Reference voltage 675 is gener
`ated in one embodiment by a resistive Voltage divider using
`resistors 677 and 673 in series between a voltage rail and
`ground.
`Power switch multiplexer 655 may be implemented in a
`number of different ways. Generally, multiplexers are well
`known. However, multiplexing a power signal output may
`involve concerns not commonly found in other multiplexing
`situations. FIG.7 illustrates an embodiment of a power switch
`multiplexer. Multiplexer 700 uses a set of power transistors to
`provide conduction paths for the two input power Supply
`signals.
`System supply 710 is coupled to a first transistor 730,
`which in turn is coupled to a second transistor 730, which in
`turn is coupled to memory power output 760. The transistors
`730 in the path from supply 710 to memory supply 760 are
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`Samsung Electronics Co., Ltd.
`Ex. 1024, p. 18
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`US 7,724,604 B2
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`10
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`15
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`5
`controlled by a comparison signal 740. Additionally, the tran
`sistors 730 in this path are coupled at the drain side of the
`transistors 730, so that the parasitic diodes formed by each
`transistor 730 in the path are opposed to each other parasitic
`conduction for one transistor is blocked by a blocking path in
`the other transistor when the transistors are turned off. Thus,
`when the path between system supply 710 and memory sup
`ply 760 is shutoff, even parasitic conductance should be mini
`mal or Zero.
`A similar conduction path is provided between battery
`supply 720 and memory supply 760. Two transistors 730 are
`drain coupled in the path from battery supply 720 to memory
`supply 760, and the transistors of this path are controlled by
`comparison inverse signal 750. Signal 740 and signal 750 are
`complements of each other, so conduction should only occur
`along one path in multiplexer 700 at any give time. Addition
`ally, the opposing parasitic diodes of the transistors 730 in
`each conduction path should essentially block parasitic cur
`rent when a given conduction path is turned off. Note that
`transistors 730 are described as power Metal-Oxide Semicon
`ductor Field-Effect Transistor MOSFETs (e.g. transistors
`730 have drains), but other power transistors may be appro
`priate, provided that opposing parasitic components can be
`incorporated.
`Much of the functions involved in managing power Supply
`are handled by the voltage supervisory block of various
`embodiments. FIG. 8 illustrates an embodiment of a voltage
`supervisory system. While various embodiments may be
`used, voltage supervisory block 800 represents one embodi
`ment which may be useful for providing power to a memory
`module. Voltage supervisory block 800 compares a system
`voltage with a reference voltage, and generates output signals
`with various logic components to control other parts of the
`power Supply circuitry.
`Voltage supervisory circuitry 835 compares a system
`power signal 825 with a voltage reference signal 820 and
`provides a power fail signal 845. Voltage reference signal 820
`is produced from a voltage rail 805 and a resistive divider
`composed of a 50 kohm resistor 810 in series with a 27 kohm
`resistor 815 to ground. Presumably, voltage rail 805 is pow
`40
`ered from a secure power Supply Such as a battery power
`supply. Voltage supervisory circuitry 835 also is coupled to
`ground through a capacitor 850.
`The power fail signal 845 is pulled up to power rail 830
`through resistor 840, and feeds into inverter 855. This pro
`duces a voltage detection reset signal 885, and feeds into a
`buffer 860 to produce a voltage detection buffered signal 870.
`OR gate 865 evaluates signal 870 and a finite state machine
`signal 875 to produce comparison signal 858 and through an
`inverter 855 to produce inverted comparison signal 868.
`Comparison signal 858 and inverted comparison signal 868
`may be used as a logically paired set of signals to control a
`power multiplexer such as that of FIG. 7.
`Voltage detection reset signal 885 is fed into flip-flop 880
`which is clocked by clock signal 890. The output of flip-flop
`880 is fed to AND gate 895 along with an inverted version of
`signal 885 to produce a pulse at output 898. AND output 898
`is used as the chip enable signal to flip-flop. 888, which is also
`clocked with clock signal 890 and uses a power Supply signal
`825 as an input to produce finite state machine signal 875.
`One-Shot reset signal 878 resets flip-flop 888, thereby clear
`ing signal 875.
`While Voltage Supervisory circuitry provides signals to
`indicate what Voltage signal should be Supplied as a power
`Source, clock circuitry may be needed in Some systems to
`maintain synchronous operations, or just to drive periodic
`processes. FIG. 9 illustrates an embodiment of clock cir
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`30
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`6
`cuitry. Several different clock sub-circuits are illustrated. Cir
`cuit 910 uses a 25 MHz oscillator 915 which is enabled by
`enable 925 to produce a 25 MHz clock 920. Circuit 930 uses
`oscillator 955, coupled through capacitors 960 to voltage rail
`965, to produce an oscillating signal which is used by clock
`detector 935 in detecting system clock 940, and thereby pro
`ducing 166 MHZ clock 945, along with a safe/fail signal 950.
`Similarly, circuit 970 uses oscillator 975, coupled through
`bypass capacitors 960 to power rail 965 with clock detector
`985 to detect 25 MHz clock signal 925 and to produce 25
`MHz clock 990 along with safe/fail signal 980. A safe clock
`signal is produced by circuit 995, using 166 MHz clock 945,
`25 MHz clock 990 and safe/fail signal 950 to determine the
`output (safe clock 988) of programmable clock component
`993. Safe clock 988 provides an input to phase locked loop
`983, which produces PLL output signals 978 and uses a
`feedback loop to maintain a clock signal.
`A processor system on a chip may be used to provide
`various functionality, in particular generation of control sig
`nals for a finite state machine, for example. FIG. 10 illustrates
`an embodiment of a processor system on a chip. Processor
`system on a chip 1010 may be implemented as a Cypress
`processor System on a chip, or through other digital signal
`processors or similar devices.
`A debug port 1005 is provided, a reset input 1080 is pro
`vided, and a clock generator 1070 provides a clock 1075.
`Internally, PSOC (Programmable System On a Chip) 1010
`includes an embedded microprocessor module 1040, an I2C
`controller module 1050, peripheral interface 1015, local
`SRAM 1020, local FLASH ROM 1025, and two timers (TRP
`timer 1060 and TRF timer 1065), all of which are coupled
`through bus 1030. Processor module 1040 may be pro
`grammed to generate finite state machine control signals
`1085, and to control timers 1060 and 1065 to generate timer
`signals 1090. Similarly, an interface with an SMBUS may be
`provided through signals 1095. Moreover, I2C controller
`1050 allows for communication with a surrounding system.
`FLASH ROM 1025 may store code and SRAM 1020 may
`store local variables.
`Control of a state machine allows for a state machine to be
`implemented and operated, such as in a complex program
`mable logic device (e.g. a CPLD available from Xilinx). FIG.
`11 illustrates an embodiment of a state machine. State
`machine 1100 may be used to refresh SDRAM of a memory
`module when the SDRAM is not otherwise the subject of
`operations in a normal system mode. Essentially, one may
`expect that SDRAM will be properly refreshed when system
`power is present and a system operates normally, but if
`SDRAM is to retain memory in a power fail situation, refresh
`operations must be implemented without benefit of other
`parts of a system, requiring that the memory module trigger
`SDRAM refresh operations itself.
`State machine 1100 is initialized with a reset at idle state
`1110. When a system powers on, for example, one may expect
`the reset signal to cause the state machine 1100 to move to idle
`state 1110. This avoids unexpected operation due to transient
`signals, for example. When the system is armed, the enable
`signal moves state machine 1100 into ready state 1120. From
`here, the system may await a start signal, at which point it
`moves to start state 1130. From start state 1130, the state
`machine 1100 advances to wait state 1140, based on chip
`select and clock enable signals being asserted. At wait state
`1140, a trftimer (such as a timer of PSOC 1010) is started, and
`a signal from the trf timer results in an advance to precharge
`state 1150. From precharge state 1150, the state machine
`1100 advances automatically to another wait state 1160, with
`a trp timer (such as another timer of PSOC 1010) started. A
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`45
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`50
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`55
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`60
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`65
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`Samsung Electronics Co., Ltd.
`Ex. 1024, p. 19
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`US 7,724,604 B2
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`7
`signal from the trp timer advances the state machine 1100 to
`self-refresh entry state 1170, with self-refresh initiated for the
`memory module. The state machine then advances automati
`cally to self refresh state 1180, and stays there automatically
`self-refreshing the memory module. A reset signal or an exit 5
`signal will move the state machine 1100 back to idle state
`1110, ending the self-refresh process, such as when a system
`sufficiently recovers power.
`All of these components can be added up to a memory
`power control system—a system which controls a power 10
`Supply and clock provided to a memory module, and thereby
`provides backup power and clocking when system power and
`system clocks fail. FIG. 12 illustrates an embodiment of a
`memory control system. System 1200 includes a PSOC, a
`finite State machine, a signal multiplexer and a clock multi- 15
`plexer, and thereby receives and selects both clock and
`memory control and command bus signals.
`PSOC 1210 is a processor system on a chip or similar
`processor, including a UART (Universal Asynchronous
`Receiver, Transmitter) serial port 1260, timers 1270 and 20
`1280, and an IIC (I2C) controller 1250. Debug signals 1297
`may interface with UART 1260, clock and reset signals 1295
`are supplied to the PSOC, and system bus signals 1290 also
`interface with I2C controller 1250. This allows PSOC 1210 to
`produce finite state machine signals 1215 and timer signals 25
`1225. These signals are used to control finite state machine
`1230, which produces signals that control refresh of memory
`of a memory module. This also produces signal logic multi
`plexer select signal 1255, which selects an input for multi
`plexer 1240. Multiplexer 1240 is a logic signal multiplexer, 30
`accepting as input a set of system control and command bus
`signals 1235 and sets of finite state machine control and
`command bus signals 1245 to produce memory control and
`command bus signals
`During normal operation of the system with proper power 35
`and/or clock operation the system control and command bus
`input to signal logic multiplexer 1240 will be chosen by
`multiplexer select signal 1255. During either power interrup
`tion or system clock fault cycles the finite state machine
`control and command bus signals will be supplied as memory 40
`control and command bus signals through the other inputs of
`signal logic multiplexer 1240 and selected by multiplexer
`select signal 1255. A separate multiplex select signal 1275
`selects as input either a system clock 1277 or a 25 MHz clock
`1285 as inputs to clock multiplexer 1220 which provides as 45
`output a PLL input clock signal 1265. Clock multiplexer 1220
`operates to not only select a clock output signal, but also to
`make Sure that a Switch from one clock signal to another clock
`signal does not cause edges to come so quickly as to simulate
`a clock rate higher than that specified for the system and 50
`memory module.
`While a general approach to a clock and power fault detec
`tion system provides much insight, a truth table for a specific
`implementation may also be useful. FIG. 13 illustrates an
`embodiment of a truth table. Truth table 1300 represents the 55
`values of signals to memory components of a DDR2 SDRAM
`memory module as would be generated to control the clock
`and power fault detection system and the actual memory (for
`write protection and refresh purposes).
`Whether the embodiments illustrated in the various figures 60
`are used, or alternative embodiments are used to provide
`clock and power fault detection for a memory module, Vari
`ous processes may be implemented to control Such a clock
`and power fault detection system. FIG. 14 illustrates an
`embodiment of a process of controlling clock and power fault 65
`detection for a memory system. Process 1400 includes deter
`mining if clock and power fault detection is enabled, deter
`
`8
`mining if power and clock signals are