Docket No.: 062453-032
`
`FLASH-DRAM HYBRID MEMORY MODULE
`
`PRIORITY CLAIM
`
`[0001]
`
`This application is a continuation of U.S. Patent Application No. 13/559,476, filed
`
`July 26, 2012, titled , "FLASH-DRAM HYBRID MEMORY MODULE" which claims the
`
`benefit of provisional patent application serial no. 61/512,871, filed July 28, 2011, and is a
`
`continuation-in-part of US patent application serial no. 12/240,916, filed September 29, 2008
`
`which is a continuation of U.S. patent application serial no. 12/131,873, filed June 2, 2008,
`
`which claims the benefit of U.S. provisional patent application serial no. 60/941,586, filed June
`
`1, 2007, the contents of all of which are incorporated herein by reference in their entirety.
`
`[0002]
`
`This application may also be considered to be related to co-pending U.S. patent
`
`application serial no. 13/536,173, filed on June 28, 2012, and commonly owned herewith.
`
`TECHNICAL FIELD
`
`[0003]
`
`The present disclosure relates generally to computer memory devices, and more
`
`particularly, to devices that employ different types of memory devices such as combinations of
`
`Flash and random access memories.
`
`1
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 1
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`

`

`Docket No.: 062453-032
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`BACKGROUND
`
`[0004]
`
`As technology advances and the usage of portable computing devices, such as tablet
`
`notebook computers, increases, more data needs to be transferred among data centers and
`
`to/from end users. In many cases, data centers are built by clustering multiple servers that are
`
`networked to increase performance.
`
`[0005]
`
`Although there are many types of networked servers that are specific to the types
`
`applications envisioned, the basic concept is generally to increase server performance by
`
`dynamically allocating computing and storage resources. In recent years, server technology has
`
`evolved to be specific to particular applications such as `finance transactions' (for example,
`
`point-of-service, inter-bank transaction, stock market transaction), `scientific computation' (for
`
`example, fluid dynamic for automobile and ship design, weather prediction, oil and gas
`
`expeditions), `medical diagnostics' (for example, diagnostics based on the fuzzy logic, medical
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`data processing), `simple information sharing and searching' (for example, web search, retail
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`store website, company home page), `email' (information distribution and archive), `security
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`service', `entertainment' (for example, video-on-demand), and so on. However, all of these
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`applications suffer from the same information transfer bottleneck due to the inability of a high
`
`speed CPU (central processing unit) to efficiently transfer data in and out of relatively slower
`
`speed storage or memory subsystems, particularly since data transfers typically pass through the
`
`CPU input/output (I/O) channels.
`
`[0006]
`
`The data transfer limitations by the CPU are exemplified by the arrangement shown
`
`in FIG. 1, and apply to data transfers between main storage (for example the hard disk (HD) or
`
`2
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2
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`

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`Docket No.: 062453-032
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`solid state drive (SSD) and the memory subsystems (for example DRAM DIMM (Dynamic
`
`Random Access Memory Dual In-line Memory Module) connected to the front side bus (FSB)).
`
`In arrangements such as that of FIG. 1, the SSD/HD and DRAM DIMM of a conventional
`
`memory arrangement are connected to the CPU via separate memory control ports (not shown).
`
`FIG. 1 specifically shows, through the double-headed arrow, the data flow path between the
`
`computer or server main storage (SSD/HD) to the DRAM DIMMs. Since the SSD/HD data I/O
`
`and the DRAM DIMM data I/O are controlled by the CPU, the CPU needs to allocate its process
`
`cycles to control these I/Os, which may include the IRQ (Interrupt Request) service which the
`
`CPU performs periodically. As will be appreciated, the more time a CPU allocates to
`
`controlling the data transfer traffic, the less time the CPU has to perform other tasks. Therefore,
`
`the overall performance of a server will deteriorate with the increased amount of time the CPU
`
`has to expend in performing data transfer.
`
`[0007]
`
`There have been various approaches to increase the data transfer throughput rates
`
`from/to the main storage, such as SSD/HD, to local storage, such as DRAM DIMM. In one
`
`example as illustrated in FIG. 2, EcoRAMTM developed by Spansion provides a storage SSD
`
`based system that assumes a physical form factor of a DIMM . The EcoRAMTM is populated
`
`with Flash memories and a relatively small memory capacity using DRAMs which serve as a
`
`data buffer. This arrangement is capable of delivering higher throughput rate than a standard
`
`SSD based system since the EcoRAMTM is connected to the CPU (central processing unit) via a
`
`high speed interface, such as the HT (Hyper Transport) interface, while an SSD/HD is typically
`
`connected via SATA (serial AT attachment), USB (universal serial bus), or PCI Express
`
`(peripheral component interface express). For example, the read random access throughput rate
`
`of EcoRAMTM is near 3GB/s compared with 400MB/s for a NAND SSD memory subsystem
`
`3
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 3
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`

`

`Docket No.: 062453-032
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`using the standard PCI Express-based. This is a 7.5X performance improvement. However, the
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`performance improvement for write random access throughput rate is less than 2X (197MBs for
`
`the EcoRAM vs. 104MBs for NAND SSD). This is mainly due to the fact that the write speed is
`
`cannot be faster than the NAND Flash write access time. Figure 2 is an example of EcoRAMTM
`
`using SSD with the form factor of a standard DIMM such that it can be connected to the FSB
`
`(front side bus). However, due to the interface protocol difference between DRAM and Flash, an
`
`interface device, EcoRAM AcceleratorTM), which occupies one of the server's CPU sockets is
`
`used, and hence further reducing server's performance by reducing the number of available CPU
`
`sockets available, and in turn reducing the overall computation efficiency. The server's
`
`performance will further suffer due to the limited utilization of the CPU bus due to the large
`
`difference in the data transfer throughput rate between read and write operations.
`
`[0008]
`
`The EcoRAMTM architecture enables the CPU to view the Flash DIMM controller
`
`chip as another processor with a large size of memory available for CPU access.
`
`[0009]
`
`In general, the access speed of a Flash based system is limited by four items: the
`
`read/write speed of the Flash memory, the CPU's FSB bus speed and efficiency, the Flash
`
`DIMM controller's inherent latency, and the HT interconnect speed and efficiency which is
`
`dependent on the HT interface controller in the CPU and Flash DIMM controller chip.
`
`[0010]
`
`The published results indicate that these shortcomings are evident in that the
`
`maximum throughput rate is 1.56 GBs for the read operation and 104 MBs for the write
`
`operation. These access rates are 25% of the DRAM read access speed, and 1.7% of the DRAM
`
`access speed at 400MHz operation. The disparity in the access speed (15 to 1) between the read
`
`4
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 4
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`

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`Docket No.: 062453-032
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`operation and write operation highlight a major disadvantage of this architecture. The
`
`discrepancy of the access speed between this type of architecture and JEDEC standard DRAM
`
`DIMM is expected to grow wider as the DRAM memory technology advances much faster than
`
`the Flash memory.
`
`OVERVIEW
`
`[0011]
`
`Described herein is a memory module couplable to a memory controller of a host
`
`system. The memory module includes a non-volatile memory subsystem, a data manager
`
`coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data
`
`manager and operable to exchange data with the non-volatile memory subsystem by way of the
`
`data manager, and a controller operable to receive commands from the memory controller and to
`
`direct (i) operation of the non-volatile memory subsystem, (ii) operation of the volatile memory
`
`subsystem, and (iii) transfer of data between any two or more of the memory controller, the
`
`volatile memory subsystem, and the non-volatile memory subsystem based on at least one
`
`received command from the memory controller.
`
`[0012]
`
`Also described herein is a method for managing a memory module by a memory
`
`controller, the memory module including volatile and non-volatile memory subsystems. The
`
`method includes receiving control information from the memory controller, wherein the control
`
`information is received using a protocol of the volatile memory subsystem. The method further
`
`includes identifying a data path to be used for transferring data to or from the memory module
`
`using the received control information, and using a data manager and a controller of the memory
`
`module to transfer data between any two or more of the memory controller, the volatile memory
`
`5
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 5
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`

`

`subsystem, and the non-volatile memory subsystem based on at least one of the received control
`
`information and the identified data path.
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`Docket No.: 062453-032
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`[0013]
`
`Also described herein is a memory module wherein the data manager is operable to
`
`control one or more of data flow rate, data transfer size, data buffer size, data error monitoring,
`
`and data error correction in response to receiving at least one of a control signal and control
`
`information from the controller.
`
`[0014]
`
`Also described herein is a memory module wherein the data manager controls data
`
`traffic between any two or more of the memory controller, the volatile memory subsystem, and
`
`the non-volatile memory subsystem based on instructions received from the controller.
`
`[0015]
`
`Also described herein is a memory module wherein data traffic control relates to any
`
`one or more of data flow rate, data transfer size, data buffer size, data transfer bit width,
`
`formatting information, direction of data flow, and the starting time of data transfer.
`
`[0016]
`
`Also described herein is a memory module wherein the controller configures at least
`
`one of a first memory address space of the volatile memory subsystem and a second memory
`
`address space of the non-volatile memory subsystem in response to at least one of a received
`
`command from the memory controller and memory address space initialization information of
`
`the memory module.
`
`6
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 6
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`

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`Docket No.: 062453-032
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`[0017]
`
`Also described herein is a memory module wherein the data manager is configured as
`
`a bi-directional data transfer fabric having two or more sets of data ports coupled to any one of
`
`the volatile and non-volatile memory subsystems.
`
`[0018]
`
`Also described herein is a memory module wherein at least one of the volatile and
`
`non-volatile memory subsystems comprises one or more memory segments.
`
`[0019]
`
`Also described herein is a memory module wherein each memory segment comprises
`
`at least one memory circuit, memory device, or memory die.
`
`[0020]
`
`Also described herein is a memory module wherein the volatile memory subsystem
`
`comprises DRAM memory.
`
`[0021]
`
`Also described herein is a memory module wherein the non-volatile memory
`
`subsystem comprises flash memory.
`
`[0022]
`
`Also described herein is a memory module wherein at least one set of data ports is
`
`operated by the data manager to independently and/or concurrently transfer data to or from one
`
`or more memory segments of the volatile or non-volatile memory subsystems.
`
`[0023]
`
`Also described herein is a memory module wherein the data manager and controller
`
`are configured to effect data transfer between the memory controller and the non-volatile
`
`memory subsystem in response to memory access commands received by the controller from the
`
`memory controller.
`
`7
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 7
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`

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`Docket No.: 062453-032
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`[0024]
`
`Also described herein is a memory module wherein the volatile memory subsystem is
`
`operable as a buffer for the data transfer between the memory controller and non-volatile
`
`memory.
`
`[0025]
`
`Also described herein is a memory module wherein the data manager further includes
`
`a data format module configured to format data to be transferred between any two or more of the
`
`memory controller, the volatile memory subsystem, and the non-volatile memory subsystem
`
`based on control information received from the controller.
`
`[0026]
`
`Also described herein is a memory module wherein the data manager further includes
`
`a data buffer for buffering data delivered to or from the non-volatile memory subsystem.
`
`[0027]
`
`Also described herein is a memory module wherein the controller is operable to
`
`perform one or more of memory address translation, memory address mapping, address domain
`
`conversion, memory access control, data error correction, and data width modulation between
`
`the volatile and non-volatile memory subsystems.
`
`[0028]
`
`Also described herein is a memory module wherein the controller is configured to
`
`effect operation with the host system in accordance with a prescribed protocol.
`
`[0029]
`
`Also described herein is a memory module wherein the prescribed protocol is selected
`
`from one or more of DDR, DDR2, DDR3, and DDR4 protocols.
`
`8
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 8
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`

`

`Docket No.: 062453-032
`
`[0030]
`
`Also described herein is a memory module wherein the controller is operable to
`
`configure memory space in the memory module based on at least one of a command received
`
`from the memory controller, a programmable value written into a register, a value corresponding
`
`to a first portion of the volatile memory subsystem, a value corresponding to a first portion of the
`
`non-volatile memory subsystem, and a timing value.
`
`[0031]
`
`Also described herein is a memory module wherein the controller configures the
`
`memory space of the memory module using at least a first portion of the volatile memory
`
`subsystem and a first portion of the non-volatile memory subsystem, and the controller presents a
`
`unified memory space to the memory controller.
`
`[0032]
`
`Also described herein is a memory module wherein the controller configures the
`
`memory space in the memory module using partitioning instructions that are application-specific.
`
`[0033]
`
`Also described herein is a memory module wherein the controller is operable to copy
`
`booting information from the non-volatile to the volatile memory subsystem during power up.
`
`[0034]
`
`Also described herein is a memory module wherein the controller includes a volatile
`
`memory control module, a non-volatile memory control module, data manager control module, a
`
`command interpreter module, and a scheduler module.
`
`[0035]
`
`Also described herein is a memory module wherein commands from the volatile
`
`memory control module to the volatile memory subsystem are subordinated to commands from
`
`the memory controller to the controller.
`
`9
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 9
`
`

`

`[0036]
`
`Also described herein is a memory module wherein the controller effects pre-fetching
`
`of data from the non-volatile to the volatile memory.
`
`Docket No.: 062453-032
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`[0037]
`
`Also described herein is a memory module wherein the pre-fetching is initiated by the
`
`memory controller writing an address of requested data into a register of the controller.
`
`[0038]
`
`Also described herein is a memory module wherein the controller is operable to
`
`initiate a copy operation of data of a closed block in the volatile memory subsystem to a target
`
`block in the non-volatile memory subsystem.
`
`[0039]
`
`Also described herein is a memory module wherein, if the closed block is re-opened,
`
`the controller is operable to abort the copy operation and to erase the target block from the non-
`
`volatile memory subsystem.
`
`[0040]
`
`Also described herein is a method for managing a memory module wherein the
`
`transfer of data includes a bidirectional transfer of data between the non-volatile and the volatile
`
`memory subsystems.
`
`[0041]
`
`Also described herein is a method for managing a memory module further comprising
`
`operating the data manager to control one or more of data flow rate, data transfer size, data width
`
`size, data buffer size, data error monitoring, data error correction, and the starting time of the
`
`transfer of data.
`
`10
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 10
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`

`

`Docket No.: 062453-032
`
`[0042]
`
`Also described herein is a method for managing a memory module further comprising
`
`operating the data manager to control data traffic between the memory controller and at least one
`
`of the volatile and non-volatile memory subsystems.
`
`[0043]
`
`Also described herein is a method for managing a memory module wherein data
`
`traffic control relates to any one or more of data transfer size, formatting information, direction
`
`of data flow, and the starting time of the transfer of data.
`
`[0044]
`
`Also described herein is a method for managing a memory module wherein data
`
`traffic control by the data manager is based on instructions received from the controller.
`
`[0045]
`
`Also described herein is a method for managing a memory module further comprising
`
`operating the data manager as a bi-directional data transfer fabric with two or more sets of data
`
`ports coupled to any one of the volatile and non-volatile memory subsystems.
`
`[0046]
`
`Also described herein is a method for managing a memory module wherein at least
`
`one of the volatile and non-volatile memory subsystems comprises one or more memory
`
`segments.
`
`[0047]
`
`Also described herein is a method for managing a memory module wherein each
`
`memory segment comprises at least one memory circuit, memory device, or memory die.
`
`[0048]
`
`Also described herein is a method for managing a memory module wherein the
`
`volatile memory subsystem comprises DRAM memory.
`
`11
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 11
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`

`

`[0049]
`
`Also described herein is a method for managing a memory module wherein the non-
`
`volatile memory subsystem comprises Flash memory.
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`Docket No.: 062453-032
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`[0050]
`
`Also described herein is a method for managing a memory module further comprising
`
`operating the data ports to independently and/or concurrently transfer data to or from one or
`
`more memory segments of the volatile or non-volatile memory subsystems.
`
`[0051]
`
`Also described herein is a method for managing a memory module further comprising
`
`directing transfer of data bi-directionally between the volatile and non-volatile memory
`
`subsystems using the data manager and in response to memory access commands received by the
`
`controller from the memory controller.
`
`[0052]
`
`Also described herein is a method for managing a memory module further comprising
`
`buffering the data transferred between the memory controller and non-volatile memory
`
`subsystem using the volatile memory subsystem.
`
`[0053]
`
`Also described herein is a method for managing a memory module further comprising
`
`using the controller to perform one or more of memory address translation, memory address
`
`mapping, address domain conversion, memory access control, data error correction, and data
`
`width modulation between the volatile and non-volatile memory subsystems.
`
`[0054]
`
`Also described herein is a method for managing a memory module further comprising
`
`using the controller to effect communication with a host system by the volatile memory
`
`subsystem in accordance with a prescribed protocol.
`
`12
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 12
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`

`

`[0055]
`
`Also described herein is a method for managing a memory module wherein the
`
`prescribed protocol is selected from one or more of DDR, DDR2, DDR3, and DDR4 protocols.
`
`Docket No.: 062453-032
`
`[0056]
`
`Also described herein is a method for managing a memory module further comprising
`
`using the controller to configure memory space in the memory module based on at least one of a
`
`command received from the memory controller, a programmable value written into a register, a
`
`value corresponding to a first portion of the volatile memory subsystem, a value corresponding
`
`to a first portion of the non-volatile memory subsystem, and a timing value.
`
`[0057]
`
`Also described herein is a method for managing a memory module wherein the
`
`controller configures the memory space of the memory module using at least a first portion of the
`
`volatile memory subsystem and a first portion of the non-volatile memory subsystem, and the
`
`controller presents a unified memory space to the memory controller.
`
`[0058]
`
`Also described herein is a method for managing a memory module wherein the
`
`controller configures the memory space in the memory module using partitioning instructions
`
`that are application-specific.
`
`[0059]
`
`Also described herein is a method for managing a memory module further comprising
`
`using the controller to copy booting information from the non-volatile to the volatile memory
`
`subsystem during power up.
`
`[0060]
`
`Also described herein is a method for managing a memory module wherein the
`
`controller includes a volatile memory control module, the method further comprising generating
`
`13
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 13
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`

`

`commands by the volatile memory control module in response to commands from the memory
`
`controller, and transmitting the generated commands to the volatile memory subsystem.
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`Docket No.: 062453-032
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`[0061]
`
`Also described herein is a method for managing a memory module further comprising
`
`pre-fetching of data from the non-volatile memory subsystem to the volatile memory subsystem.
`
`[0062]
`
`Also described herein is a method for managing a memory module wherein the pre-
`
`fetching is initiated by the memory controller writing an address of requested data into a register
`
`of the controller.
`
`[0063]
`
`Also described herein is a method for managing a memory module further comprising
`
`initiating a copy operation of data of a closed block in the volatile memory subsystem to a target
`
`block in the non-volatile memory subsystem.
`
`[0064]
`
`Also described herein is a method for managing a memory module further comprising
`
`aborting the copy operation when the closed block of the volatile memory subsystem is re-
`
`opened, and erasing the target block in the non-volatile memory subsystem.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0065]
`
`The accompanying drawings, which are incorporated into and constitute a part of
`
`this specification, illustrate one or more examples of embodiments and, together with the
`
`description of example embodiments, serve to explain the principles and implementations of the
`
`embodiments.
`
`14
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 14
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`

`

`Docket No.: 062453-032
`
`[0066]
`
`In the drawings:
`
`FIG. 1 is a block diagram illustrating the path of data transfer, via a CPU, of a
`
`conventional memory arrangement;
`
`FIG. 2 is a block diagram of a known EcoRAMTM architecture;
`
`FIGS. 3A and 3B are block diagrams of a non-volatile memory DIMM or
`
`NVDIMM;
`
`FDHDIMM;
`
`FIGS. 4A and 4B are block diagrams of a Flash-DRAM hybrid DIMM or
`
`FIG. 5A is a block diagram of a memory module 500 in accordance with certain
`
`embodiments described herein;
`
`FIG. 5B is a block diagram showing some functionality of a memory module such
`
`as that shown in FIG. 5A;
`
`FIG. 6 is a block diagram showing some details of the data manager (DMgr);
`
`FIG. 7 is a functional block diagram of the on-module controller (CDC);
`
`FIG. 8A is a block diagram showing more details of the prior art Flash-DRAM
`
`hybrid DIMM (FDHDIMM) of FIGS. 4A and 4B;
`
`FIG. 8B is a block diagram of a Flash-DRAM hybrid DIMM (FDHDIMM) in
`
`accordance with certain embodiments disclosed herein;
`
`FIG. 9 is a flow diagram directed to the transfer of data from Flash memory to
`
`DRAM memory and vice versa in an exemplary FDHDIMM;
`
`FIG. 10 is a block diagram showing an example of mapping of DRAM address
`
`space to Flash memory address space; and
`
`15
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 15
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`

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`Docket No.: 062453-032
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`FIG. 11 is a table showing estimates of the maximum allowed closed blocks in a
`
`queue to be written back to Flash memory for different DRAM densities using various average
`
`block use time.
`
`DESCRIPTION OF EXAMPLE EMBODIMENTS
`
`[0067]
`
`Example embodiments are described herein in the context of a system of
`
`computers, servers, controllers, memory modules, hard disk drives and software. Those of
`
`ordinary skill in the art will realize that the following description is illustrative only and is not
`
`intended to be in any way limiting. Other embodiments will readily suggest themselves to such
`
`skilled persons having the benefit of this disclosure. Reference will now be made in detail to
`
`implementations of the example embodiments as illustrated in the accompanying drawings. The
`
`same reference indicators will be used to the extent possible throughout the drawings and the
`
`following description to refer to the same or like items.
`
`[0068]
`
`In the interest of clarity, not all of the routine features of the implementations
`
`described herein are shown and described. It will, of course, be appreciated that in the
`
`development of any such actual implementation, numerous implementation-specific decisions
`
`must be made in order to achieve the developer's specific goals, such as compliance with
`
`application- and business-related constraints, and that these specific goals will vary from one
`
`implementation to another and from one developer to another. Moreover, it will be appreciated
`
`that such a development effort might be complex and time-consuming, but would nevertheless be
`
`16
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 16
`
`

`

`a routine undertaking of engineering for those of ordinary skill in the art having the benefit of
`
`this disclosure.
`
`Docket No.: 062453-032
`
`[0069]
`
`In accordance with this disclosure, the components, process steps, and/or data
`
`structures described herein may be implemented using various types of operating systems,
`
`computing platforms, computer programs, and/or general purpose machines. In addition, those
`
`of ordinary skill in the art will recognize that devices of a less general purpose nature, such as
`
`hardwired devices, field programmable gate arrays (FPGAs), application specific integrated
`
`circuits (ASICs), or the like, may also be used without departing from the scope and spirit of the
`
`inventive concepts disclosed herein. Where a method comprising a series of process steps is
`
`implemented by a computer or a machine and those process steps can be stored as a series of
`
`instructions readable by the machine, they may be stored on a tangible medium such as a
`
`computer memory device (e.g., ROM (Read Only Memory), PROM (Programmable Read Only
`
`Memory), EEPROM (Electrically Eraseable Programmable Read Only Memory), Flash memory,
`
`Jump Drive, and the like), magnetic storage medium (e.g., tape, magnetic disk drive, and the
`
`like), optical storage medium (e.g., CD-ROM, DVD-ROM, paper card, paper tape and the like)
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`and other types of program memory.
`
`[0070]
`
`The term "exemplary" where used herein is intended to mean "serving as an
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`example, instance or illustration." Any embodiment described herein as "exemplary" is not
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`necessarily to be construed as preferred or advantageous over other embodiments.
`
`[0071]
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`Disclosed herein are arrangements for improving memory access rates and addressing
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`the high disparity (15 to 1 ratio) between the read and write data throughput rates. In one
`
`17
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 17
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`

`

`arrangement, a Flash-DRAM-hybrid DIMM (FDHDIMM) with integrated Flash and DRAM is
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`used. Methods for controlling such an arrangement are described.
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`Docket No.: 062453-032
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`[0072]
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`In certain embodiments, the actual memory density (size or capacity) of the DIMM
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`and/or the ratio of DRAM memory to Flash memory are configurable for optimal use with a
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`particular application (for example, POS, inter-bank transaction, stock market transaction,
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`scientific computation such as fluid dynamics for automobile and ship design, weather
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`prediction, oil and gas expeditions, medical diagnostics such as diagnostics based on the fuzzy
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`logic, medical data processing, simple information sharing and searching such as web search,
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`retail store website, company home page, email or information distribution and archive, security
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`service, and entertainment such as video-on-demand).
`
`[0073]
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`In certain embodiments, the device contains a high density Flash memory with a low
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`density DRAM, wherein the DRAM is used as a data buffer for read/write operation. The Flash
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`serves as the main memory. Certain embodiments described herein overcome the needs of
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`having a long separation period between an Activate command (may be referred to as RAS) and
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`a corresponding read or write command (may be referred to as first CAS command).
`
`[0074]
`
`In accordance with one embodiment, described with reference to FIGS. 3A and 3B, a
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`memory system 300 includes a non-volatile (for example Flash) memory subsystem 302 and a
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`volatile (for example DRAM) memory subsystem 304. The examples of FIGS. 3A and 3B are
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`directed to architectures of a non-volatile DIMM (NVDIMM) NVDIMM system that may use a
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`power subsystem (not shown) that can include a battery or a capacitor as a means for energy
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`storage to copy DRAM memory data into Flash memory when power loss occurs, is detected, or
`
`18
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 18
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`

`

`Docket No.: 062453-032
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`is anticipated to occur during operation. When normal power is restored, a restore NVDIMM
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`operation is initiated and the data stored in the Flash memory is properly restored to the DRAM
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`memory. In this architecture, the density of the Flash is about the same as the DRAM memory
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`size or within a few multiples, although in some applications it may be higher. This type of
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`architecture may also be used to provide non-volatile storage that is connected to the FSB (front
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`side bus) to support RAID (Redundant Array of Independent Disks) based systems or other type
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`of operations. An NVDIMM controller 306 receives and interprets commands from the system
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`memory controller hub (MCH). The NVDIMM controller 306 control the NVDIMM DRAM
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`and Flash memory operations. In FIG. 3A, the DRAM 304 communicates data with the MCH,
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`while an internal bus 308 is used for data transfer between the DRAM and Flash memory
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`subsystems. In FIG. 3B, the NVDIMM controller 306' of NVDIMM 300' monitors events or
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`commands and enables data transfer to occur in a first mode between the DRAM 304' and Flash
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`302' or in a second mode between the DRAM and the MCH.
`
`[0075]
`
`In accordance with one embodiment, a general architecture for a Flash and DRAM
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`hybrid DIMM (FDHDIMM) system 400 is shown in FIG. 4A. The FDHDIMM interfaces with
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`an MCH (memory controller hub) to operate and behave as a high density DIMM, wherein the
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`MCH interfaces with the non-volatile memory subsystem (for example Flash) 402 is controlled
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`by an FDHDIMM controller 404. Although the MCH interfaces with the Flash via the
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`FDHDIMM controller, the FDHDIMM overall performance is governed by the Flash access
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`time. The volatile memory subsystem (for example DRAM) 406 is primarily used as a data
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`buffer or a temporary storage location such that data from the Flash memory 402 is transferred to
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`the DRAM 406 at the Flash access speed, and buffered or collected into the DRAM 406, which
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`then transfers the buffered data to the MCH based on the access time of DRAM. Similarly,
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`19
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 19
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`

`

`Docket No.: 062453-032
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`when the MCH transfers data to the DRAM 406, the FDHDIMM controller 404 manages the
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`data transfer from the DRAM 406 to the Flash 402. Since the Flash memory access speed (both
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`read and write) is relatively slower than DRAM, (e.g. for example a few hundred microseconds
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`for read access), the average data throughput rate of FDHDIMM 400 is limited by the Flash
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`access speed. The DRAM 406 serves as a data buffer stage that buffers the MCH read or write
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`data. Thus, the DRAM 406 serves as a temporary storage for the data to be transferred from/to
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`the Flash 402. Furthermore, in accordance with one embodiment, the MCH recognizes the
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`physical density of an FDHDIMM operating as a high density DIMM as the density of Flash
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`alone.
`
`[0076]
`
`In accordance with one embodiment, a read operation can be performed by the MCH
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`by sending an activate command (may be si