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`
`

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`PTO/SB/14 (07-07)
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`

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`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 4
`
`

`

`NETL.096PR
`
`PATENT
`
`HIGH DENSITY DIMMS
`
`BACKGROUND
`
`[0001]
`
`As technology advances and the usage of tablet notebook computer
`
`increases, more data needs to be transferred among the data centers and to/from the end users.
`
`In many cases, the data centers are built by clustering many servers that are networked to
`
`increase the performance.
`
`[0002]
`
`Although there are many types of networking that are based on the
`
`applications, the basic concept is to increase the performance by dynamically allocating the
`
`computing resources. In recent years, the server technology has been evolved to serve many
`
`specific applications such as `finance transaction' (e.g., POS, inter-bank transaction, stock
`
`market transaction), `scientific computation' (e.g., fluid dynamic for automobile and ship
`
`design, weather prediction, oil and gas expeditions), `medical diagnostics' (e.g., diagnostics
`
`based on the fuzzy logic, medical data processing), `simple information sharing and
`
`searching' (e.g., web search, retail store website, company home page), `email' (information
`
`distribution and archive), `security service', `entertainment' (e.g., video-on-demand), etc.
`
`However, all these applications share the same information transfer bottleneck, which resides
`
`in the CPU efficiently being able to transfer the data. This is because all data transfers are
`
`going though the CPU I/O channels.
`
`[0003]
`
`The data transfer limitation by the CPU also applies to the data transfer
`
`from/to either HD or SSD to/from the memory subsystem that is connected to the FSB (Front
`
`Side Bus).
`
`[0004]
`
`There have been various configurations to increase the data transfer
`
`from/to the main storage, such as HD or DDS, to the local DRAMs for the faster data
`
`throughput rate. Especially, the EMM that is supported with EcoRAM (Spansion) (see,
`
`Appendix B) presents an idea of constructing a fast SSD that assumes the physical form
`
`factor of a DIMM. Spansion populates the EcoRAM with a large quantity of Flash memories
`
`and a limited amount of DRAMs that serves as a data buffer. This arrangement delivers a
`
`much higher throughput rate than standard SSD since this EcoRAM is connected to the CPU
`
`via the HT interface while SSD is connected via SATA or USB. The read random access
`
`-1-
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 5
`
`

`

`throughput rate of EcoRAM is near 3GB/s compared with the standard PCIe-based NAND
`SSD which is about 400MB/s. This gives a 7.5X improvement. The write random access
`throughput rate of EcoRAM over the standard PCIe-based NAND SSD is less than 2X
`
`(197MBs vs. 104MBs) due to the fact that the write speed is predominated by the Flash write
`
`access time. The idea of EcoRAM is to build a SSD with the form factor of a standard
`DIMM such that it can be connected to the Front Side bus. However, due to the interface
`protocol difference between DRAM and Flash, Spansion developed a new interface device
`(Spansion EcoRAM Accelerator) that occupies one of the CPU sockets. Spansion EcoRAM
`is well suited for the "Read Access Intensive" applications, such as `medical diagnostics,
`simple information sharing and searching, and entertainment. However, it does not fit to
`serve the applications that require extensive data manipulations, such as `scientific
`
`computation', `security service' and `finance transactions'.
`As it has been stated in the previous paragraphs, the two deficiencies of
`[0005]
`EcoRAM are: 1) it requires an interface device that occupies a CPU socket, thus less CPU,
`and in turn it reduces the overall computation efficiency; and 2) the high disparity in the
`throughput rate between read and write operations limits the utilization of this solution.
`In addition to these deficiencies, the throughput rate of EcoRAM is much
`[0006]
`lower than DRAM, such that the read access throughput rate is only 25% of the DRAM read
`access rate; the write access throughput rate is less than 2% of the DRAM access rate.
`SUMMARY
`
`[0007]
`
`This application presents certain embodiments that overcome the
`
`shortcomings of the prior art: the significantly slower access time compare to the DRAM, and
`the high parity in the throughput rate between read and write throughput rate (15 to 1 ratio).
`This application discloses certain embodiments of a Flash-DRAM-hybrid
`
`[0008]
`
`DIMM with integrated address spaces of Flash and DRAM. The application also presents a
`method of controlling such devices. In certain embodiments, the device is able to configure
`the actual memory density of the DIMM and/or the ratio of DRAM memory to Flash memory
`
`for optimal use with a particular application (e.g., POS, inter-bank transaction, stock market
`
`transaction, `scientific computation,' such as fluid dynamics for automobile and ship design,
`
`weather prediction, oil and gas expeditions, `medical diagnostics,' such as diagnostics based
`
`-2-
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 6
`
`

`

`on the fuzzy logic, medical data processing, `simple information sharing and searching,' such
`
`as web search, retail store website, company home page, `email' or information distribution
`
`and archive, `security service,' entertainment,' such as video-on-demand).
`
`[0009]
`
`In certain embodiments, the device contains a high density Flash memory
`
`with a low density DRAM, where DRAM is used as a data buffer for read/write operation.
`
`The Flash serves as the main memory.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0010]
`
`Figure 1 shows the data path in a conventional memory arrangement.
`
`[0011]
`
`Figure 2 shows the general architecture of existing non-volatile memory
`
`module products. A part of SSD/HD is migrated into the Front Side Bus (FSB) to support the
`
`RAID (Redundant Array of Independent Disks) operation.
`
`[0012]
`
`Figure 3 shows a currently available concept of connecting a Flash DIMM
`
`to the FSB.
`
`[0013]
`
`Figure 4 shows the general architecture of a currently available product
`
`that uses the Flash DIMM with a DIMM controller.
`
`[0014]
`
`Figure 5 shows an example memory module that contains DRAMs, Flash,
`
`and Central DIMM Controller (CDC), Data Manager (DMgr) in accordance with certain
`
`embodiments disclosed herein. The CDC provides two main functions: the standard RDIMM
`
`register function, and the data transfer management function between DRAM and Flash.
`
`[0015]
`
`Figure 6 shows an example connection of the CDC to the register and
`
`DMgr, to MCH, DRAM, and Flash in accordance with certain embodiments described
`
`herein.
`
`[0016]
`
`Figure 7 shows an example of the functional blocks in the CDC in
`
`accordance with certain embodiments described herein.
`
`[0017]
`
`Figure 8A shows the general concept of an existing Flash-DRAM hybrid
`
`DIMM.
`
`[0018]
`
`Figure 8B shows example functional blocks in a DRAM controller that is
`
`in the CDC in accordance with certain embodiments described herein.
`
`-3-
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 7
`
`

`

`[0019]
`
`Figure 9 shows an example state diagram of data transfer between the
`
`Flash memory and the DRAM memory in accordance with certain embodiments described
`
`herein.
`
`[0020]
`
`Figure 10 shows an example of how the MCH addresses the Flash area in
`
`accordance with certain embodiments described herein.
`
`[0021]
`
`Figure 11 is a table that shows example amounts of DRAMs that are used
`
`to support different applications in accordance with certain embodiments described herein.
`
`[0022]
`
`Figures 12A-12C show a conventional NVDIMM, a conventional
`
`FDHDIMM, and an example FDHDIMM compatible with certain embodiments described
`
`herein, respectively, to illustrate some differences between the three modules.
`
`BRIEF DESCRIPTION OF THE APPENDICES
`
`[0023]
`
`Appendix A: "HyperVault: Multi-Terra Bytes of FSB Memory for HPC,"
`
`description regarding example device in accordance with certain embodiments described
`
`herein.
`
`[0024]
`
`Appendix B: "Spansion® EcoRAMTM Solution: IOZone Solution
`
`Performance White Paper," Version 0.4, description of currently available product.
`
`DETAILED DESCRIPTION
`
`[0025]
`
`A Flash and DRAM hybrid DIMM (FDHDIMM) that interfaces with
`
`MCH operates in two modes; as a standard DDR DIMM with SSD, or as a high density
`
`DIMM.
`
`[0026]
`
`As a standard DDR DIMM with SSD, the FDHDIMM supports two views
`
`to the MCH. First, the MCH views the FDHDIMM as a combination of DRAM DIMM and
`
`SSD. In this case the MCH needs to manage two address spaces, one for the DRAMs and one
`
`for the Flash. The advantage of this mode is that the CPU does not need to be in the data path
`
`when data is moved from Flash to DRAM or vice versa. Second, the MCH views the
`
`FDHDIMM as an On-DIMM Flash with the SSD in an extended memory space that is behind
`
`the DRAM space.
`
`[0027]
`
`Thus, for the normal standard DDR DIMM with SSD operation, the MCH
`
`physically fetches data from the SSD to the DDR. This action will be much quicker than the
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 8
`
`

`

`data going through the CPU, which happens when the current data move from SSD to
`
`DIMMs occurs, since all data movement occurs on a DIMM.
`
`[0028]
`
`In the high density DIMM mode, the MCH recognizes the physical density
`
`of DIMM, which is the density of Flash alone. The DRAM serves as a data buffer that buffers
`
`read data, and serves as a temporary storage for the write date. The MCH has two options to
`
`execute a read operation.
`
`[0029]
`
`The first read option is to send an active command (actually RAS) for the
`
`FDHDIMM to pre-fetch the read data from the Flash to the DRAMs, where the pre-fetch size
`
`is a page (1KB or 2KB, optional). This option will allow the data to transfer from the Flash to
`
`DRAMs, and provides the data latency and the throughput rate that is the same as any DRAM
`
`operation as long as the operations are done onto the pages that are opened with the pre-
`
`active command. However, this option requires much a longer separation period between the
`
`RAS and the first CAS command.
`
`[0030]
`
`The other read option is executing the RAS and CAS (active and
`
`read/write) commands just as the standard DRAM. However, this option requires the initial
`
`Flash read time after the first CAS command (i.e. extensive CAS latency). This option
`
`supports the same throughput rate as the standard DRAM DIMM as long as the accesses
`
`occur from the open pages.
`
`[0031]
`
`Certain embodiments described herein overcome the shortcomings of
`
`having the long separation period between the RAS and the first CAS command, and of
`
`having the extensive CAS latency.
`
`[0032]
`
`In Figure 1, the SSD/HD and DRAM DIMM of a conventional memory
`
`arrangement are connected to CPU via separated memory control ports. This figure shows the
`
`data flow path between the server main memory (SSD or HD) to the DRAM DIMMs. Since
`
`the SSD/HD data I/O and the DRAM DIMM data I/O are controlled by the CPU, the CPU
`
`needs to allocate its process cycles to control these I/Os, which includes the IRQ (Interrupt)
`
`service that the CPU performs periodically. Furthermore, since all the data traffic goes
`
`through the CPU, the data move from/to SSD/HD to/from the DRAM DIMM occupies the
`
`CPU internal data bus, thus further hindering the overall CPU performance.
`
`-5-
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 9
`
`

`

`[0033]
`
`Figure 2 shows the general architecture of a non-volatile memory module
`
`that is currently being exercised. Non-Volatile DIMM (NVDIMM) is a Flash-DRAM hybrid
`
`DIMM (FDHDIMM), which uses a backup power (either battery or charged capacitor) to
`
`copy the data in the DRAM memory into the Flash memory when power loss occurs while
`
`the system in operation. In this architecture, a part of SSD/HD is migrated into the FSB in the
`
`form of Flash. However, the density of the Flash is rather low since the Flash memory size
`
`does not have to be any larger than the DRAM memory size. The purpose of this type of
`
`architecture is to provide a non-volatile storage that is connected to the FSB to support the
`
`RAID (Redundant Array of Independent Disks) type of operation.
`
`[0034]
`
`Figure 3 shows the system level architecture of a currently available
`
`product, which includes a Flash DIMM controller chip and Flash DIMM. In this figure, the
`
`Flash DIMM controller chip occupies a CPU socket and communicates with the CPU via HT
`
`(Hyper Transport). Although this product utilizes the HT interface, the actual interconnection
`between the controller chip and CPU is not limited to HT. Although this architecture does
`
`not address the shortcomings that associate with the traditional way (Figure 1) of connecting
`the SSD/HD and DRAM DIMMs, it allows increase of the density of non-volatile memory
`space that is connected to the virtual FSB since the CPU views the Flash DIMM controller
`chip as another processor with a large density of memory on its FSB.
`
`[0035]
`
`There are two shortcomings with this architecture. First, it occupies one or
`
`two CPU sockets. Thus, it reduces the utilization of the server Mother Board (MB). Second,
`the Flash access speed is limited by 4 items: 1) the read/write speed of the Flash memory, 2)
`the FSB bus size, 3) the Flash DIMM controller chip latency, and 4) the HT interconnect
`
`efficiency, which is dependent on the HT interface controller in the CPU and Flash DIMM
`
`controller chip.
`
`[0036]
`
`The published results indicate that these shortcomings are evident in that
`
`the maximum throughput rate is 1.56 GBs for the read operation and 104 MBs for the write
`
`operation. These access rates are 25% of the DRAM read access speed, and 1.7% of the
`
`DRAM access speed at 400MHz operation. The parity in the access speed (15 to 1) between
`the read operation and write operation clearly shows that this architecture is limited by the
`
`read/write speed of the Flash memory. The discrepancy of the access speed between this type
`
`-6-
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 10
`
`

`

`of architecture and JEDEC standard DIMM grows wider as the memory technology
`
`advances, since as the memory technology advances, the Flash access rate stays relatively
`
`constant while the DRAM access speed increases.
`
`[0037]
`
`Figure 4 shows the general architecture of the currently available
`
`FDHDIMM product, which receives two sets of control signals from the MCH/CPU while a
`
`single data bus interfaces with the MCH. In this architecture, since the MCH/CPU does not
`
`have a view to the data path between the DRAM memory and the Flash memory, it requires
`
`extra complication in designing the MCH.
`
`[0038]
`
`Figure 5 shows the basic structure of an example memory module in
`
`accordance with certain embodiments described herein.
`
`[0039]
`
`One major difference from the prior art is that the example memory
`
`module contains two on-DIMM controllers: the Central DIMM Controller (CDC) and the
`
`Data Manager (DMgr) to manage the interface between Flash, DRAM, and the MCH. This
`
`architecture addresses all the shortcomings that are associated with the prior art, such as the
`
`MCH views of the example memory module as a very high density DRAM DIMM.
`
`[0040]
`
`The CDC controls the read/write access to/from the Flash memory to the
`
`DRAM memory, and DRAM memory to MCH/CPU. Since there is no direct access from the
`
`MCH/CPU to the Flash memory, the Flash access speed has very minimal impact to the
`
`overall access speed. The CDC performs the memory address translation/mapping and
`
`address domain conversion, Flash access control, error correction, data width modulation
`
`between the Flash memory and DRAM, etc. The CDC ensures that the example memory
`
`module operates with the industry standard DDR, DDR2, DDR3, DDR4 protocols.
`
`[0041]
`
`The DMgr controls the data flow rate, the data transfer size, data buffer
`
`size, error monitoring and correction.
`
`[0042]
`
`Figure 6 shows an example interoperability among the components of
`
`certain embodiments described herein. After the initialization, the CDC receives a command
`
`from CPU to prepare for a certain memory space, which is configurable or programmable by
`
`the CPU. The CPU can partition or parse the memory space in various ways that are optimum
`
`for the particular application that it needs to execute. The CDC maps the actual physical
`
`DRAM and Flash memory space to support the CPU view of the memory space. The CDC
`
`-7-
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 11
`
`

`

`also manages to support any booting operation by copying the necessary information from the
`
`Flash memory to the DRAM memory during system power up. This activity may utilize the
`
`CDC to initiate a data copying operation from the Flash memory to the DRAM memory just
`
`as the CPU copies the boot information from the SSD/HD to the DRAM memory. The
`
`DMgr controls the data traffic between the Flash memory and the DRAM memory. The
`
`DMgr receives the data transfer size, formatting information (540), direction of data flow
`
`(511, 512, 521, 522), and the starting time of the actual data transfer from CDC. The DMgr
`
`also receives the data flow path from the CDC to correctly establish the data transfer fabric.
`
`The DMgr also functions as a bi-directional data transfer fabric such that it has more than 2
`
`sets of data ports facing the Flash and the DRAM memory. The multiplexors 511 and 512
`
`provide the data paths from the DRAMs (DRAM-A and DRAM-B) to the MCH and the
`Flash memory, the multiplexors 521 and 522 provide the data paths from the MCH and the
`
`Flash memory to the DRAMs (e.g., DRAM-A and DRAM-B).
`
`Two sets of multiplexors (511, 512, 521, 522) allow independent data
`[0043]
`transfer to the Flash memory from the DRAM memory. For example, the DMgr transfers
`data from DRAM-A to the MCH (via 511) at the same time as DRAM-B to the Flash
`memory (via 512), or it transfers data from DRAM-B to the MCH (via 511) at the same time
`as the Flash memory to DRAM-A (via 521). This special arrangement of data transfer
`connect also allows direct data transfer from the MCH to the Flash memory (e.g., via 521 and
`512), and allows direct data transfer from the Flash memory to the MCH (e.g., via 521 and
`
`511).
`
`The Data Format (540) also contains a data buffer to support a wide data
`[0044]
`bus facing the Flash memory, and to match the data flow between the DRAM memory and
`
`the Flash memory.
`
`[0045]
`
`Figure 7 shows example functional blocks of the CDC in accordance with
`
`certain embodiments described herein. The CDC has four major functional blocks: DRAM
`
`control block (DRAMCtrl), Flash control block (FlashCtrl), MCH/CPU command interpreter
`
`(CmdInt), DRAM-Flash interface scheduler (Scheduler), and the DMgr control block
`
`(DMgrCtrl).
`
`-8-
`
`Samsung Electronics Co., Ltd.
`Ex. 1008, p. 12
`
`

`

`[0046]
`
`DRAMCtrl (710) generates DRAM commands that are independent from
`
`the DRAM commands from the MCH. However, if the MCH initiates a read/write operation
`
`from/to the same DRAM that is currently executing a command from the DRAMCtrl (710),
`
`the DRAMCtrl (710) aborts the operation. The FlashCtrl (720) generates Flash commands
`
`for the proper read/write operations. The Cmdlnt (730) constantly intercepts the MCH
`
`command and provides the correct interpretation. For example, Cmdlnt issues an interrupt
`
`signal to the DRAMCtrl (710) if the MCH issues a command that collides (conflicts) with the
`
`currently executing or pending commands that DRAMCtrl initiated. The Scheduler (740)
`
`schedules the Flash —DRAM interface operation such that there is no resource conflict in the
`
`DMgr. The Scheduler assigns the time slots for the DRAMCtrl, FlashCtrl operation based on
`
`the current status and the command from the MCH. The DMgrCtrl (750) controls the data
`
`paths between the DRAM memory and the Flash memory, between the DRAM memory and
`
`the MCH, and between the MCH and the Flash memory.
`
`[0047]
`
`The memory space mapping in Figure 8A for an existing Flash-DRAM
`
`hybrid DIMM shows two separate and independent address spaces, one for the Flash memory
`
`and the other for the DRAM memory. The CPU treats these two address spaces no differently
`
`than the conventional address spaces of DRAM and SSD/HD. The memory in each address
`
`space is controlled by the conventional method of controlling the DRAM and SSD/HD.
`
`However, the on-DIMM data path between Flash and DRAM allows direct data transfer to
`
`occur between the Flash memory and the DRAM memory. This method of transferring data
`
`bypasses the conventional method of transferring data from SSD/HD to the FSB memory via
`
`the CPU, thus reducing the data transfer time. Since this method also removes the CPU from
`
`the data path, it allows the over efficiency of the CPU usage, and thus improves the overall
`
`system performance. However, the shortcoming of this method are that: 1) the MCH needs to
`
`manage two address space