Trials@uspto.gov
`571-272-7822
`
`Paper 10
`Date: December 7, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`
`
`
`
`
`
`
`Before JON M. JURGOVAN, DANIEL J. GALLIGAN, and
`NABEEL U. KHAN, Administrative Patent Judges.
`
`
`
`
`
`JURGOVAN, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`I.
`
`INTRODUCTION
`
`Samsung Electronics Co., Ltd. (“Petitioner”) filed a Petition (Paper 1,
`
`“Pet.”) to institute an inter partes review of claims 1–30 of U.S. Patent
`
`11,016,918 B2, issued on May 25, 2021 (Ex. 1001, “the ’918 patent”).
`
`Netlist, Inc. (“Patent Owner”) filed a Preliminary Response (Paper 7,
`
`“Prelim. Resp.”) to the Petition.
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`IPR2022-00996
`Patent 11,016,918 B2
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`Institution of an inter partes review is authorized when “the
`
`information presented in the petition . . . and any response . . . shows that
`
`there is a reasonable likelihood that the petitioner would prevail with respect
`
`to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`Based on the current record, and for the reasons explained below, we
`
`determine that Petitioner has established a reasonable likelihood that it
`
`would prevail with respect to at least one challenged claim, and we institute
`
`an inter partes review as to all the challenged claims and grounds raised in
`
`the Petition.
`
`II. BACKGROUND
`
`A.
`
`Real Parties in Interest
`
`Petitioner identifies Samsung Electronics Co., Ltd. and Samsung
`
`Semiconductor, Inc. as the real parties in interest. Pet. 1. Patent Owner
`
`identifies itself as the sole real party in interest. Paper 4, 1.
`
`B.
`
`Related Matters
`
`The parties advise that the ’918 patent is related to Samsung
`
`Electronics Co., Ltd., et al. v. Netlist, Inc., IPR2022-00999 (U.S. Patent No.
`
`11,232,054 B2; Netlist, Inc. v. Samsung Electronics Co., Ltd., et al., Case
`
`No. 2-21-cv-00463 (E.D. Tex.); Samsung Electronics Co., Ltd. v. Netlist,
`
`Inc., Case No. 1:21-cv-01453 (D. Del.); and U.S. Appl. No. 17/582,797.
`
`Pet. 1; Paper 4, 1.
`
`The parties advise that the ’918 patent is related to the following legal
`
`proceeding, which is no longer pending: SK hynix Inc. v. Netlist, Inc.,
`
`IPR2017-00692 (U.S. Patent No. 8,874,831 B2). Pet. 1; Paper 4, 1.
`
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`Patent 11,016,918 B2
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`C.
`
`The ’918 Patent (Ex. 1001)
`
`The ’918 patent is titled “Flash-DRAM Hybrid Memory Module.”
`
`Ex. 1001, code (54). Figure 12 of the ’918 patent is reproduced below.
`
`
`
`Figure 12 shows an example memory system 1010 of the ’918 patent.
`
`Id. at 21:14–16. The memory system 1010 includes a volatile memory
`
`subsystem 1030, a non-volatile memory subsystem 1040, and a controller
`
`1062 operatively coupled to the volatile memory subsystem 1030 and
`
`selectively coupled to the non-volatile memory subsystem 1040. Id. at
`
`21:16–22. Volatile memory 1030 may comprise elements 1032 of two or
`
`more dynamic random access memory (DRAM) elements such as double
`
`data rate (DDR), DDR2, DDR3, and synchronous DRAM (SDRAM). Id. at
`
`22:16–19. Non-volatile memory 1040 may comprise elements 1042 of flash
`
`memory elements such as NOR, NAND, ONE-NAND flash and multi-level
`
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`cell (MLC). Id. at 22:35–40. Memory system 1010 may comprise a
`
`memory module or printed circuit board (PCB) 1020. Id. at 21:24–26.
`
`Memory system 1010 has an interface 1022 for power voltage, data, address,
`
`and control signal transfer between memory system 1010 and a host system.
`
`Id. at 22:3–6.
`
`
`
`Controller 1062 may include microcontroller unit 1060 and FPGA
`
`logic 1070, either as separate devices or integrated together. Id. at 24:35–37,
`
`23:19–22, Fig. 14. Microcontroller 1060 may transfer data between the
`
`volatile memory 1030 and non-volatile memory 1040. Id. at 24:35–41.
`
`Logic element 1070 provides signal level translation and address translation
`
`between the volatile memory and the non-volatile memory. Id. at 24:45–56.
`
`When the system is operating normally, controller 1062 controls
`
`switch 1052 to decouple the volatile memory 1030 from controller 1062 and
`
`the non-volatile memory 1040 (the ’918 patent refers to this as the “first
`
`state.”). Id. at 24:60–25:7. In response to a power interruption, for example,
`
`controller 1062 controls switch 1052 to couple the volatile memory 1030 to
`
`itself and non-volatile memory 1040, and transfers data from the volatile
`
`memory to the non-volatile memory to prevent its loss (the ’918 patent
`
`refers to this as the “second state”). Id. at 25:9–20.
`
`
`
`Memory system 1010 may comprise a voltage monitor 1050 to
`
`monitor voltage supplied from the host system via interface 1022. Id. at
`
`25:8–10. When the voltage monitor 1050 detects a low voltage condition,
`
`the voltage monitor transmits a signal to the controller 1062 to indicate the
`
`detected condition. Id. at 25:11–15.
`
`
`
`Power may be supplied from a first power supply (e.g. a system power
`
`supply) when the memory system 1010 is in the first state and from a second
`
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`power supply 1080 when the memory system 1010 is in the second state. Id.
`
`at 25:54–58. Second power supply 1080 may comprise step-up transformer
`
`1082, step-down transformer 1084, and capacitor bank 1086 with one or
`
`more capacitors. Id. at 26:3–13.
`
`The memory system 1010 further has a third state in which controller
`
`1062 is decoupled from the volatile memory system 1030 and power is
`
`supplied to the volatile memory subsystem 1030 from a third power supply
`
`(not shown). Id. at 25:62–69. “[T]he third power supply may provide
`
`power to the volatile memory subsystem 1030 when the memory system
`
`1010 detects that a trigger condition is likely to occur but has not yet
`
`occurred.” Id. at 25:66–26:3.
`
`Figure 16 of the ’918 patent is reproduced below.
`
`Figure 16 shows power module 1100 of memory system 1010. Id. at
`
`27:59–61. Power module 1100 comprises conversion element 1120, first
`
`power element 1130, and second power element 1140. Id. at 28:7–15,
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`28:20–22. Conversion element 1120 comprises sub-blocks 1122, 1124,
`
`1126 comprised of various converter circuits such as buck converters, boost
`
`converters, and buck-boost converters for providing various voltages 1102,
`
`1104, 1105, 1107 from the outputs of the first and second power elements
`
`1130, 1140. Id. at 29:18–54. The first power element 1130 may comprise a
`
`pulse-width modulation power controller generating voltage 1110 from
`
`voltages 1106, 1108. Id. at 28:13–15. Second power element 1140 may
`
`comprise capacitor array 1142, buck-boost converter 1144 receiving
`
`voltages 1106, 1108 and adjusting the voltage for charging the capacitor
`
`array, and voltage/current limiter 1146, which limits charge current to the
`
`capacitor array and stops charging the capacitor array 1142 when it reaches a
`
`certain charge voltage. Id. at 28:62–67. “[P]ower module 1100 provides
`
`power to [ ] components of the memory system 1010 using different
`
`elements based on a state of the memory system 1010 in relation to a trigger
`
`condition.” Id. at 27:61–65.
`
`Specifically, “[i]n a first state, first voltage 1102 is provided to
`
`memory system 1010 from input 1106 and fourth voltage 1110 is provided
`
`to the conversion element 1120 from the first power element 1130.” Id. at
`
`28:27–31. “In a second state, the fourth voltage 1110 is provided to the
`
`conversion element 1120 from the first power element 1130 and the first
`
`voltage 1102 is provided to the memory system 1010 from the conversion
`
`element 1120.” Id. at 28:32–37. “In the third state, the fifth voltage 1112 is
`
`provided to conversion element 1120 from second power element 1140 and
`
`the first voltage 1104 is provided to memory system 1010 from conversion
`
`element 1120.” Id. at 28:34–38. Transition from the first state to the second
`
`state may occur when power module 1100 detects a power failure is about to
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`occur, and transition from the second state to the third state may occur when
`
`it detects a power failure has occurred. Id. at 28:39–47.
`
`D.
`
`Illustrative Claim
`
`Of the challenged claims, claims 1, 16, and 23 are independent.
`
`Independent claim 1, reproduced below with brackets noting Petitioner’s
`
`identifiers, is illustrative of the claimed subject matter.
`
`1. [1.a] A memory module comprising:
`[1.b] a printed circuit board (PCB) having an interface
`configured to fit into a corresponding slot connector of a host
`system, the interface including a plurality of edge connections
`configured to couple power, data, address and control signals
`between the memory module and the host system;
`[1.c] a first buck converter configured to provide a first
`regulated voltage having a first voltage amplitude;
`[1.d] a second buck converter configured to provide a second
`regulated voltage having a second voltage amplitude;
`[1.e] a third buck converter configured to provide a third
`regulated voltage having a third voltage amplitude;
`[1.f] a converter circuit configured to provide a fourth
`regulated voltage having a fourth voltage amplitude; and
`[1.g] a plurality of components coupled to the PCB, each
`component of the plurality of components coupled to one or more
`regulated voltages of the first, second, third and fourth regulated
`voltages, the plurality of components comprising:
`[1.h] a plurality of synchronous dynamic random access
`memory (SDRAM) devices coupled to the first regulated
`voltage, and
`[1.i] [1.i.1] at least one circuit coupled between a first portion
`of the plurality of edge connections and the plurality of SDRAM
`devices, [1.i.2] the at least one circuit operable to (i) receive a
`first plurality of address and control signals via the first portion
`of the plurality of edge connections, and (ii) output a second
`plurality of address and control signals to the plurality of
`SDRAM devices, [1.i.3] the at least one circuit coupled to both
`the second regulated voltage and the fourth regulated voltage,
`[1.i.4] wherein a first one of the second and fourth voltage
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`amplitudes is less than a second one of the second and fourth
`voltage amplitudes.
`
`Ex. 1001, 38:19–44.
`
`E.
`
`Evidence
`
`Petitioner relies on the following references (see Pet. 3, 10–14), as
`
`well as the Declaration of Dr. Andrew Wolfe (Ex. 1003).
`
`Reference Exhibit No.
`
`Patent/Printed Publication
`
`1023
`
`1024
`
`1025
`
`U.S. Patent Pub. No. 2006/0174140 A1 to
`Harris, published August 3, 2006
`U.S. Patent No. 7,724,604 B2, issued May 25,
`2010
`U.S. Patent Pub. No. 2006/0080515 A1,
`published Apr. 13, 2006
`1027, 1028 JESD82-20 and JESD205 standards published
`March 2007
`U.S. Patent No. 6,856,556 B1 to Hajeck, issued
`Feb. 15, 2005
`
`Harris
`
`Amidi
`
`Spiers
`
`FBDIMM
`Standards
`Hajeck
`
`
`
`F.
`
`1038
`
`Prior Art and Asserted Grounds
`
`Petitioner asserts that claims 1–30 are unpatentable on the following
`
`Grounds (Pet. 4):
`
`Claims Challenged 35 U.S.C. §
`1–3, 8, 14, 15, 23
`103(a)
`1–30
`103(a)
`
`1–30
`
`1–30
`1–30
`
`
`
`103(a)
`
`103(a)
`103(a)
`
`References
`Harris, FBDIMM Standards
`Harris, FBDIMM Standards, Amidi
`Harris, FBDIMM Standards, Amidi,
`Hajeck
`Spiers, Amidi
`Spiers, Amidi, Hajeck
`
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`III. ANALYSIS OF CHALLENGED GROUNDS
`
`We turn now to Petitioner’s asserted grounds of unpatentability and
`
`Patent Owner’s arguments in its Preliminary Response to determine whether
`
`Petitioner has met the threshold standard of 35 U.S.C. § 314(a).
`
`A claim is unpatentable under 35 U.S.C. § 103(a) if “the differences
`
`between the subject matter sought to be patented and the prior art are such
`
`that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`(2007). The question of obviousness is resolved on the basis of underlying
`
`factual determinations, including: (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of skill in the art; and (4) objective evidence of nonobviousness,
`
`i.e., secondary considerations.1 See Graham v. John Deere Co., 383 U.S. 1,
`
`17–18 (1966).
`
`A patent claim “is not proved obvious merely by demonstrating that
`
`each of its elements was, independently, known in the prior art.” KSR, 550
`
`U.S. at 418. An obviousness determination requires finding “both ‘that a
`
`skilled artisan would have been motivated to combine the teachings of the
`
`prior art references to achieve the claimed invention, and that the skilled
`
`artisan would have had a reasonable expectation of success in doing so.’”
`
`Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359,
`
`1367–68 (Fed. Cir. 2016) (citation omitted); see also KSR, 550 U.S. at 418.
`
`Further, an assertion of obviousness “cannot be sustained by mere
`
`
`1 Neither party has identified any objective evidence of nonobviousness on
`the record to be considered at this time.
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`conclusory statements; instead, there must be some articulated reasoning
`
`with some rational underpinning to support the legal conclusion of
`
`obviousness.” KSR, 550 U.S. at 418; In re NuVasive, Inc., 842 F.3d 1376,
`
`1383 (Fed. Cir. 2016) (a finding of a motivation to combine “must be
`
`supported by a ‘reasoned explanation’”).
`
`“In an [inter partes review], the petitioner has the burden from the
`
`onset to show with particularity why the patent it challenges is
`
`unpatentable.” Harmonic, 815 F.3d at 1363 (citing 35 U.S.C. § 312(a)(3));
`
`see also Intelligent Bio-Sys., 821 F.3d at 1369 (“It is of the utmost
`
`importance that petitioners in the IPR proceedings adhere to the requirement
`
`that the initial petition identify ‘with particularity’ the ‘evidence that
`
`supports the grounds for the challenge to each claim.’” (quoting 35 U.S.C.
`
`§ 312(a)(3))). Therefore, to prevail in an inter partes review, Petitioner must
`
`explain how the proposed combinations of prior art would have rendered the
`
`challenged claims unpatentable. At this preliminary stage, we determine
`
`whether the information presented in the Petition shows there is a reasonable
`
`likelihood that Petitioner would prevail in establishing that at least one of the
`
`challenged claims would have been obvious over the proposed combinations
`
`of prior art.
`
`A.
`
`Level of Ordinary Skill in the Art
`
`Petitioner asserts a person of ordinary skill in the art “would have had
`
`an advanced degree in electrical or computer engineering, or a related field,
`
`and two years working or studying in the field of design or development of
`
`memory systems, or a bachelor’s degree in such engineering disciplines and
`
`at least three years working in the field.” Pet. 8–9 (citing Ex. 1003 ¶ 67).
`
`Petitioner contends that additional training can substitute for educational or
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`research experience, and vice versa. Id. at 8. Petitioner asserts that such a
`
`hypothetical person would have been familiar with the JEDEC industry
`
`standards, and knowledgeable about the design and operation of
`
`standardized DRAM and SDRAM memory devices and memory modules
`
`and how they interacted with a memory controller and other parts of a
`
`computer system, including standard communication busses and protocols,
`
`such as PCI and SMBus busses and protocols. Id. at 8–9. Petitioner further
`
`contends that such “a hypothetical person would also have been familiar
`
`with the structure and operation of circuitry used to access and control
`
`computer memories, including sophisticated circuits such as ASICs, FPGAs,
`
`and CPLDs, and more low-level circuits such as tri-state buffers.” Id. at 9.
`
`Petitioner further asserts that such “a hypothetical person would further have
`
`been familiar with voltage supply requirements of such structures (e.g.,
`
`memory modules, memory devices, memory controller, and associated
`
`access and control circuitry), including voltage conversion and voltage
`
`regulation circuitry.” Id.
`
`In the Preliminary Response, Patent Owner applies the level of
`
`ordinary skill in the art proposed by Petitioner. Prelim. Resp. 6.
`
`Among the factors that may be considered in determining the level of
`
`ordinary skill in the art are “the type of problems encountered in the art;
`
`prior art solutions to those problems; rapidity with which innovations are
`
`made; sophistication of the technology; and educational level of active
`
`workers in the field.” In re GPAC, Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`
`(citing Custom Accessories, Inc. v. Jeffrey-Allan Indus., Inc., 807 F.2d 955,
`
`962–63 (Fed. Cir. 1986)). The evidence presented mostly applies to the
`
`educational level of workers in the field, but also touches upon other factors
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`as well. We find Petitioner’s proposal is consistent with the level of
`
`ordinary skill in the art reflected by the ’918 patent and the prior art of
`
`record, and we, therefore, adopt Petitioner’s proposed level of ordinary skill
`
`in the art, with the exception of the open-ended language “at least,” for
`
`purposes of this Decision.
`
`B.
`
`Claim Construction
`
`We construe each claim “in accordance with the ordinary and
`
`customary meaning of such claim as understood by one of ordinary skill in
`
`the art and the prosecution history pertaining to the patent,” the same
`
`standard used to construe the claim in a civil action. 37 C.F.R. § 42.100(b).
`
`Petitioner contends that “no express constructions are needed for this
`
`proceeding” but notes that Patent Owner has broadly interpreted some claim
`
`terms for purposes of infringement even though a narrower interpretation
`
`may be more reasonable. Pet. 9 (citing Ex. 1071, 39–46; Ex. 1073, 46–63;
`
`Ex. 1003 ¶ 128). Petitioner further contends it is not necessary to determine
`
`whether claim terms are governed by § 112, 6th paragraph because at least
`
`one of the prior art combinations matches the disclosure of the ’918 patent.
`
`Id.
`
`At this stage in the proceeding, we need only construe the claims to
`
`the extent necessary to determine whether to institute inter partes review.
`
`See Realtime Data, LLC v. Iancu, 912 F.3d 1368, 1375 (Fed. Cir. 2019)
`
`(“The Board is required to construe ‘only those terms . . . that are in
`
`controversy, and only to the extent necessary to resolve the controversy.’”
`
`(quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`
`(Fed. Cir. 1999))). We determine that, at this stage of this proceeding, there
`
`is no need to expressly construe any claim terms in order to determine
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`whether or not to institute review because the parties do not dispute the
`
`claimed terms’ meanings, and their ordinary and customary meanings
`
`suffice for our analysis. However, we do invite the parties to construe the
`
`term “pre-regulated voltage” at trial for reasons explained in Section III.D.4,
`
`infra.
`
`C. Ground 1: Obviousness Over Harris and FBDIMM Standards
`
`Petitioner contends claims 1–3, 8, 14, 15, and 23 would have been
`
`obvious over the combination of Harris and FBDIMM Standards and relies
`
`on the Declaration of Dr. Andrew Wolfe (Ex. 1003) in support. Pet. 14–51.
`
`For the reasons that follow, we are persuaded that the evidence, including
`
`Dr. Wolfe’s testimony, sufficiently supports Petitioner’s arguments and,
`
`therefore, establishes a reasonable likelihood of prevailing with respect to
`
`this ground at this stage of the proceeding.
`
`1.
`
`Harris (Ex. 1023)
`
`Harris is titled “Voltage Distribution System and Method for a
`
`Memory Assembly.” Ex. 1023, code (54). Harris was published as U.S.
`
`Patent Pub. No. 2006/0174140 A1 on August 3, 2006. Petitioner contends
`
`Harris is prior art under § 102(a). Pet. 10.
`
`Harris’s Figure 1A is reproduced below.
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`As shown in Figure 1A, Harris discloses a memory module 100A including
`
`on-board regulator 102 for converting an externally supplied voltage 104 to
`
`appropriate local voltage levels 106 (Vcc), 108 (Vdd), such as 0.5V to 3.5V.
`
`Ex. 1023, code (57), ¶¶ 9–10. Voltage 106 is supplied to buffer/logic
`
`component 112 which may be connected to a memory controller via
`
`interface 114 and daisy-chained with other memory assemblies via interface
`
`116. Id. ¶ 9. Voltage 108 powers memory devices 110-1 to 110-N. Id. The
`
`memory module 100A may be a Dual In-Line Memory Modules (DIMM)
`
`wherein each of the memory devices 100-1 to 100-N comprises a Double
`
`Data Rate (DDR), DDR2, or DDR3 device. Id. The memory module 100A
`
`may be an unbuffered, registered or fully buffered DIMM. Id.
`
`2.
`
`FBDIMM Standards (Exs. 1027, 1028)
`
`In March 2007, the Joint Electron Device Engineering Council
`
`(JEDEC) published standards for Fully Buffered DIMM (FBDIMM)
`
`memory modules titled “JESD82-20” (Ex. 1027) and “JESD205”
`
`(Ex. 1028). Ex. 1029 ¶¶ 134–137. Petitioner refers to these standards
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`collectively as the “FBDIMM Standards.” Pet. 11. Petitioner contends the
`
`FBDIMM Standards are prior art under § 102(a). Id.
`
`The FBDIMM Standards specify voltages for components on the
`
`memory module as follows:
`
`Ex. 1028, 9. The above table shows values for supply voltages including
`
`DRAM VDD, AMB VCC, DRAM interface VT T, and VDDSPD. The
`
`FBDIMMM Standards further specify the following voltages for various
`
`power supplies:
`
`
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`Ex. 1027, 83. The table above sets voltage levels for power supplies VCC,
`
`
`
`VCCFBD, VDD, VSS, and VDDSPD.
`
`3. Motivation to Combine
`
`Petitioner contends that a person of ordinary skill in the art would
`
`have been motivated to combine Harris with the FBDIMM Standards with a
`
`reasonable expectation of success because Harris states that its Figure 1A
`
`may be a “fully buffered DIMM” (FBDIMM or FBD). Pet. 16. Petitioner
`
`contends that a person of ordinary skill in the art would have understood that
`
`this type of DIMM is standardized in JEDEC’s FBDIMM Standards and
`
`thus, would naturally look to them for more details about the “fully buffered
`
`DIMM” that Harris describes as compatible with his on-board voltage
`
`regulator module (VRM). Id.
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`Patent Owner does not dispute Petitioner’s motivation to combine
`
`Harris and the FBDIMM Standards. See Prelim. Resp.
`
`Petitioner has sufficiently shown that a person of ordinary skill in the
`
`art would have combined Harris and the FBDIMM Standards since Harris
`
`states that its memory module may include fully buffered DIMMs (FBDs).
`
`Ex. 1023 ¶ 9. We agree that one of ordinary skill in the art would have
`
`recognized this as a standard and looked to the FBDIMM Standards for
`
`information concerning the voltage values standardized for use in an
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`FBDIMM. Ex. 1027, 83; Ex. 1028, 9. Petitioner has shown sufficiently that
`
`one of ordinary skill in the art would have combined Harris and the
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`FBDIMM Standards with a reasonable expectation of success.
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`4.
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`Analysis of Independent Claim 1
`
`a)
`
`Limitation 1.a: “A memory module comprising:”
`
`Petitioner asserts that Harris’s memory module 100A in Figure 1A or
`
`memory module 306-1 in Figure 3 corresponds to the claimed “memory
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`module.” Pet. 19–20 (citing Ex. 1023 ¶¶ 9, 17, 20, Figs. 1A, 3; Ex., 1003
`
`¶¶ 217–223; Ex. 1028, 38). Harris does indeed disclose a memory module
`
`with multiple memory devices such as DRAMs 110-1 to 110-N in Figure 1A
`
`or 306-1, for example, in Figure 3.
`
`Patent Owner does not specifically respond to Petitioner’s contention
`
`for this limitation. See Prelim. Resp.
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`Based on our review and consideration of the current record, we
`
`determine that Petitioner has adequately shown that Harris teaches the
`
`preamble for purposes of institution.2
`
`b)
`Limitation 1.b: “a printed circuit board (PCB)
`having an interface configured to fit into a corresponding
`slot connector of a host system, the interface including a
`plurality of edge connections configured to couple
`power, data, address and control signals between the
`memory module and the host system”
`
`Petitioner asserts that Harris and the FBDIMM Standards disclose this
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`limitation. Pet. 20–25. Petitioner contends that Harris and the FBDIMM
`
`standard disclose printed circuit boards (PCBs). Pet. 20 (citing Ex. 1023
`
`¶ 13, Figs. 1A, 3). Petitioner also contends that a PCB may be referred to as
`
`a ‘memory board’ or ‘raw card.’ Id. at 20–21 (citing Ex. 1023 ¶ 9, Ex. 1028,
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`10, 38, 84; Ex. 1003 ¶¶ 223–225).
`
`As for the PCB “having an interface configured to fit into a
`
`corresponding slot connector of a host system,” Petitioner notes that Harris’s
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`Figure 3 shows that each memory module 306-1 to 306-M includes an edge
`
`connection for fitting into a corresponding slot of a host system. Pet. 21
`
`(citing Ex. 1023 ¶¶ 2, 12, 13, 19, Figs. 3, 4; Ex. 1028, 38, 84; Ex. 1003
`
`¶¶ 227–228).
`
`Petitioner further contends that Harris, consistent with the FBDIMM
`
`Standards, discloses that the edge connections are “configured to couple
`
`power, data, address and control signals between the memory module and
`
`
`2 Neither party argues whether the preamble limits claim 1. Although we
`find that the evidence supports that the prior art teaches the preamble, we
`make no determination at this stage of the proceeding that the preamble of
`claim 1 is limiting.
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`the host system.” Pet. 21–25. Petitioner contends that the power signal
`
`corresponds to Harris’s voltage 104 in Figure 1A. Id. at 21 (citing Ex. 1023
`
`¶¶ 10, 12, 19). Petitioner contends that Harris’s buffer 112 in Figure 1A is
`
`called “AMB” (Advanced Memory Buffer) in the FBDIMM Standards.
`
`Pet. 23–24. Petitioner indicates that Harris’s buffer 112 receives data,
`
`address, and control signals via memory controller interface 114 and
`
`transmits these signals to DRAMs 110-1 to 110-N in Figure 1A. Pet. 22–25
`
`(citing Ex. 1023 ¶ 9 (“buffer/logic component 112 is provided for buffering
`
`command/address (C/A) space as well as data space at least for a portion of
`
`memory devices 110-1 through 110-N”). In addition, Petitioner argues that
`
`the FBDIMM Standards indicate that buffer AMB receives data signals
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`DQ0–DQ63; address signals A0–A15; and control signals RAS, CAS, WE,
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`CS, etc. Pet. 22–23 (citing Ex. 1028, 13).
`
`Patent Owner argues that Petitioner has not made a prima facie case
`
`that Harris discloses a memory module having a PCB interface that receives
`
`power from the host system. Prelim. Resp. 14–20. Harris states, however,
`
`that DRAM devices may be “powered from system board or main board
`
`voltage sources.” Ex. 1023 ¶ 2. Harris also discloses that “external voltage
`
`sources may comprise any combination of known or heretofore unknown
`
`voltage supplies, either regulated or unregulated, and even including variable
`
`voltages.” Ex. 1023 ¶ 14 (emphasis added). Patent Owner does not argue
`
`that voltage supplied by a host system is not a “known” voltage supply as
`
`referenced by Harris. Furthermore, Petitioner indicates that the FBDIMM
`
`Standards show that the buffer AMB may be connected to a host, suggesting
`
`that the FBDIMM may derive its power from the host. Pet. 24 (showing
`
`figure at Ex. 1027, 4). These facts point to the conclusion that Harris’s
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`external voltage source may be the host system notwithstanding Patent
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`Owner’s arguments to the contrary.
`
`Based on our review and consideration of the current record, we
`
`determine that Petitioner has adequately shown that the combination of
`
`Harris and the FBDIMM Standards teaches this limitation for purposes of
`
`institution.
`
`c)
`Limitations 1.c to 1.f: “a first buck converter
`configured to provide a first regulated voltage having a
`first voltage amplitude; a second buck converter
`configured to provide a second regulated voltage having
`a second voltage amplitude; a third buck converter
`configured to provide a third regulated voltage having a
`third voltage amplitude; a converter circuit configured to
`provide a fourth regulated voltage having a fourth
`voltage amplitude;”
`
`Petitioner contends that Harris and the FBDIMM Standards disclose
`
`limitations 1.c to 1.f. Pet. 26–31. Petitioner relies on an annotated version
`
`of Harris’s Figure 1A, shown below.
`
`
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`Above is Harris’s Figure 1A annotated with information one would have
`
`obtained from the FBDIMM Standards according to Petitioner. Pet. 26
`
`(citing Pet. 14–19; Ex. 1003 ¶¶ 232–243, 250–257, 262–276, 281–287).
`
`Specifically, the above figure shows voltage mappings A, B, and C of four
`
`voltages specified by Harris and the FBDIMM Standards. Petitioner
`
`contends the voltage range described in Harris (0.5V–3.5V) is the same
`
`range as the voltages described in the FBDIMM Standards. Id. at 27 (citing
`
`Ex. 1023 ¶ 9). Petitioner contends the voltages would be “regulated”
`
`because Harris indicates “tightly regulated power” is a problem to be solved,
`
`and proposes “at least one on-board voltage regulator” that is “capable of
`
`generating tightly-controlled voltage levels” as the solution. Id. at 28 (citing
`
`Ex. 1023 ¶¶ 2, 3, 9–11; Ex. 1003 ¶ 234).
`
`
`
`Petitioner further contends that Harris teaches using “buck converters”
`
`to provide the four regulated voltages. Id. (citing Ex. 1003 ¶¶ 236, 237, 252,
`
`264, 286). Specifically, Petitioner contends that Harris discloses “replacing
`
`[the prior art] power supply interface pins with as few as six +12V pins
`
`(from an external voltage source)” and then using “a high-frequency
`
`switching voltage converter capable of generating tightly-controlled voltage
`
`levels” to provide each needed on-board regulated voltage. Id. (alteration by
`
`Petitioner; emphasis omitted; citing Ex. 1023 ¶¶ 10, 12). Petitioner contends
`
`that a “buck converter” was a conventional device for implementing such a
`
`“voltage-reducing switching converter.” Id. (emphasis omitted; citing
`
`Ex. 1030, 2:41–43). Although the claim states that a converter circuit
`
`generates the fourth voltage, Petitioner notes that a buck converter would be
`
`an obvious way to implement a converter circuit. Id. at 28, n.2. Petitioner
`
`further contends a buck converter would have been an obvious way to step
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`down a higher input voltage of 12V to a lower output voltage of 3.5V or
`
`less, and that there would have been a reasonable expectation of success
`
`because buck converters were well-known switching devices commonly
`
`used to step down the voltage between input and output, as had long been
`
`taught in textbooks. Id. at 28–29 (citing Ex. 1003 ¶¶ 146–149, 236–237;
`
`Ex. 1058, 3, 5, 12–16; Ex. 1032, 161, 164; Ex. 1024, Fig. 6; Ex. 1050, 1:21).
`
`
`
`Petitioner further notes that “buck converters” were well-known as a
`
`highly-efficient way to step down voltages without generating excess heat or
`
`requiring large cooling devices, providing further motivation to use buck
`
`converters. Id. at 29–30 (citing Ex. 1003 ¶ 237; Ex. 1040, 1, 23, 24,
`
`Figs. 22–25; Ex. 1041, 1, 13; Ex. 1048, 3; Ex. 1058, 5; Ex. 1059, 5:23–30;
`
`Ex. 1062, 11; Ex. 1064 ¶ 101).
`
`
`
`Petitioner further contends that it would have been obvious to use at
`
`least four converters in Harris given the need for four different voltages
`
`(e.g., 0.9V, 1.5V, 1.8V, 3.3V) in the FBDIMM Standards. Id. at 30 (citing
`
`Pet. 14–19). Petitioner asserts that it would have been obvious to use four
`
`converters because the voltages at the same level in Petitioner’s voltage
`
`mappings A and B are described as separate voltages with separate pins that
`
`are separately controllable in the FBDIMM Standards. Id. at 30–31 (citing
`
`Ex. 1028, 17–20, 30–32; Ex. 1026, 9; Ex. 1003 ¶¶ 242, 256; Ex. 1062, 13).
`
`
`
`Patent Owner argues that Harris req