`
`Paper No. 45
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`SAMSUNG ELECTRONICS CO., LTD., MICRON TECHNOLOGY, INC.,
`MICRON SEMICONDUCTOR PRODUCTS, INC., and
`MICRON TECHNOLOGY TEXAS LLC,†
`
`Petitioner,
`v.
`NETLIST, INC.,
`Patent Owner
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`
`
`
`
`PETITIONER’S OPPOSITION TO NETLIST’S MOTION TO SUBMIT
`SUPPLEMENTAL INFORMATION PURSUANT TO 37 C.F.R. § 42.123(b)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`† Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron
`Technology Texas LLC filed a motion for joinder and a petition in IPR2023-00406
`and have been joined as petitioners in this proceeding.
`
`

`

`
`
`TABLE OF CONTENTS
`
`Page
`INTRODUCTION ........................................................................................... 1
`I.
`FACTS ............................................................................................................. 1
`II.
`III. ARGUMENT ................................................................................................... 1
`A.
`The late supplemental information is not “relevant” ............................ 1
`B.
`The late supplemental information is inadmissible ............................... 3
`C.
`Consideration of the late supplemental information is not in the
`interests of justice .................................................................................. 5
`IV. CONCLUSION ................................................................................................ 5
`
`
`
`
`ii
`
`
`
`

`

`
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`Interactive Brokers LLC v. Chart Trading Dev., LLC,
`CBM2016-00039, Paper 51 (PTAB Aug. 18, 2017) .............................................. 3
`Phillips v. AWH Corp,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ..........................................................2, 4
`PNC Bank N.A. v. USAA,
`IPR2021-01077, Paper 73 (PTAB Jan. 20, 2023) ..............................................2, 5
`Statutes
`35 U.S.C. § 24 ............................................................................................................ 4
`Regulations
`37 C.F.R. § 42.123(a)(2) ............................................................................................ 2
`37 C.F.R. § 42.123(b) ............................................................................................1, 5
`37 C.F.R. § 42.123(c) ................................................................................................. 2
`37 C.F.R. § 42.53 ....................................................................................................... 4
`Rules
`Fed. R. Civ. P. 30(b)(6) .............................................................................................. 1
`Fed. R. Evid. 403 ....................................................................................................... 4
`Fed. R. Evid. 804(a) ................................................................................................... 4
`Fed. R. Evid. 804(a), (b) ............................................................................................ 4
`Fed. R. Evid. 804(b)(3) .............................................................................................. 3
`
`
`
`
`
`iii
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`EXHIBIT LIST
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`U.S. Patent No. 11,016,918
`
`File History of U.S. Patent No. 11,016,918
`
`Declaration of Dr. Andrew Wolfe
`
`Curriculum Vitae of Dr. Andrew Wolfe
`
`File History of U.S. Provisional Application No. 60/941,586
`
`File History of U.S. Patent Application No. 12/131,873
`
`File History of U.S. Patent Application No. 12/240,916
`
`File History of U.S. Provisional Application No. 61/512,871
`
`File History of U.S. Patent Application No. 13/559,476
`
`File History of U.S. Patent Application No. 14/489,269
`
`File History of U.S. Patent Application No. 14/840,865
`
`File History of U.S. Patent Application No. 15/934,416
`
`[Intentionally Omitted]
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 1 (PTAB
`June 20, 2014) (833 Patent IPR Petition)
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 8 (PTAB
`Dec. 16, 2014) (833 Patent Institution Decision)
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 8 (PTAB Sept. 22, 2014) (833 Patent IPR Corrected Petition)
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 13 (PTAB Mar. 13, 2015) (833 Patent Institution Decision)
`
`iv
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`1018
`
`1019
`
`1020
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 1
`(PTAB Jan. 13, 2017) (833 Patent IPR Petition)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 7
`(PTAB July 24, 2017) (833 Patent Institution Decision)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 1
`(PTAB Jan. 17, 2017) (831 Patent IPR Petition)
`
`1021
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 25
`(PTAB July 5, 2018) (831 Patent Final Written Decision)
`1022 Micron Tech., Inc. et al. v. Netlist, Inc., IPR2022-00418, Paper No. 2
`(PTAB Jan. 14, 2022) (833 Patent IPR Petition)
`
`1023
`
`U.S. Patent Application Publication No. 2006/0174140 to Harris et
`al.
`
`1024
`
`U.S. Patent No. 7,724,604 to Amidi et al.
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`U.S. Patent Application Publication No. 2006/0080515 to Spiers et
`al.
`
`JEDEC Standard, DDR2 SDRAM Specification, JESD79-2B
`(January 2005) (“JESD79-2B”)
`
`JEDEC Standard, FBDIMM: Advanced Memory Buffer (AMB),
`JESD82-20 (March 2007) (“JESD82-20”)
`
`JEDEC Standard, FBDIMM Specification: DDR2 SDRAM Fully
`Buffered DIMM (FBDIMM) Design Specification, JESD205 (March
`2007) (“JESD205”)
`
`Declaration of Julie Carlson for JESD82-20 and JESD205
`
`U.S. Patent No. 7,719,866 to Boldo
`
`PCI Local Bus Specification Revision 2.2 (1998)
`
`v
`
`
`
`

`

`
`
`
`
`Exhibit #
`Description
`1032 Mohan et al., Power Electronics: Converters, Applications, and
`Design (2d ed. 1995)
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`U.S. Patent No. 7,721,130 to Prete et al.
`
`U.S. Patent No. 6,798,709 to Sim et al.
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0238536 to Hayashi et
`al.
`
`1038
`
`U.S. Patent No. 6,856,556 to Hajeck
`
`1039
`
`U.S. Patent Application Publication No. 2010/0257304 to Rajan et
`al.
`
`1040
`
`Texas Instruments, TPS51020 Datasheet (December 2003)
`
`1041
`Fairchild Semiconductor, FAN5026 Datasheet (October 2005)
`1042 Murata Power Supply Reference Guide for Xilinx FPGAs
`(September 2006)
`1043 Murata Power Supply Reference Guide for Altera FPGAs (February
`2008)
`
`1044
`
`1045
`
`1046
`
`U.S. Patent Application Publication No. 2010/0205470 to Moshayedi
`et al.
`
`JEDEC Standard, Double Data Rate (DDR) SDRAM Specification,
`JESD79 (June 2000) (“JESD79”)
`
`JEDEC Standard, DDR3 SDRAM, JESD79-3A (September 2007)
`(“JESD79-3A”)
`
`1047
`
`U.S. Patent No. 7,023,187 to Shearon et al.
`
`vi
`
`
`
`

`

`
`
`
`
`Exhibit #
`Description
`1048 Murata, DC-DC Converter Specification (DRAFT), MPD4S014S
`Datasheet (Jan. 21, 2008)
`
`1049 Micron, NAND Flash Memory Datasheet (January 2006)
`
`1050
`
`1051
`
`1052
`
`1053
`
`1054
`
`1055
`
`1056
`
`1057
`
`1058
`
`1059
`
`1060
`
`1061
`
`1062
`
`1063
`
`1064
`
`U.S. Patent No. 7,692,938 to Petter
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0101147 to Amidi
`
`U.S. Patent No. 5,563,839 to Herdt et al.
`
`U.S. Patent No. 6,693,840 to Shimada et al.
`
`Lenk, John D., Simplified Design of Switching Power Supplies
`(1995)
`
`U.S. Patent No. 7,061,214 to Mayega et al.
`
`U.S. Patent No. 5,630,096 to Zuravleff et al.
`
`Analog Devices, ADM1066 Datasheet (2006)
`
`Alan Moloney, Power-Supply Management—Principles, Problems,
`and Parts, Analog Dialogue (May 2006)
`
`National Semiconductor, LMC6953 PCI Local Bus Power
`Supervisor Datasheet (October 1996)
`
`U.S. Patent Application Publication No. 2007/0136523 to Bonella et
`al.
`
`1065
`
`U.S. Patent Application Publication No. 2009/0034354 to Resnick
`
`vii
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`1066
`
`1067
`
`1068
`
`1069
`
`1070
`
`1071
`
`1072
`
`1073
`
`1074
`
`1075
`
`1076
`
`1077
`
`1078
`
`U.S. Patent No. 10,672,458 to Shaeffer et al.
`
`LatticeXP Family Data Sheet (March 2006)
`
`Complaint for Declaratory Judgment of Non-Infringement and
`Unenforceability; Breach of Contract, Samsung Electronics Co., Ltd.
`et al. v. Netlist, Inc., No. 1:21-cv-01453 (D. Del. filed Oct. 15, 2021)
`
`First Amended Complaint for Declaratory Judgment of Non-
`Infringement and Unenforceability; Breach of Contract, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Jan. 18, 2022)
`
`Netlist’s motion to dismiss the First Amended Complaint, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Feb. 16, 2022)
`
`Complaint in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Dec. 20, 2021)
`
`Answer in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Apr. 12, 2022)
`
`Amended Complaint in Netlist, Inc. v. Samsung Electronics Co., Ltd.
`et al., No. 2:21-cv-00463 (E.D. Tex. filed May 3, 2022)
`
`Email from counsel for Samsung to counsel for Patent Owner re:
`stipulation not to pursue certain invalidity defenses if an IPR
`proceeding is instituted
`
`Transcript of deposition of William Mangione-Smith, Ph.D. (June
`12, 2023)
`
`Redline comparing Dr. Mangione-Smith’s declaration in IPR2022-
`00996 (EX2031) to his declaration in IPR2022-00999 (EX2061)
`
`Netlist’s Technology Tutorial
`
`Datasheet for ADP1821 Step-Down DC-to-DC Controller
`
`viii
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`1079
`
`2001
`
`2002
`
`2003
`
`2004
`
`Petitioner’s Demonstratives for Oral Argument on September 11,
`2023
`
`Declaration of Dr. Sunil P. Khatri
`
`U.S. 8,301,833
`
`Belloni, M. et al., A 4-Output Single-Inductor DC-DC Buck
`Converter with Self-Boosted Switch Drivers and 1.2A Total Output
`Current, ISSCC 2008, Session 24.6
`
`Ma, Dongsheng et al., Single-Inductor Multiple-Output Switching
`Converters With Time-Multiplexing Control in Discontinuous
`Conduction Mode, IEEE J. of Solid-State Circuits, 38(1) (Jan. 2003)
`
`2005
`U.S. 6,067,2451
`2006 Micron Technical Note, TN-47-05 DDR2 Power Solutions for
`Notebooks Overview (2004)
`
`2007
`
`Texas Instruments, LP29996-N, LP2296A DDR Termination
`Regulator (Nov. 2002-Revised Dec. 2016)
`
`2008
`
`2009
`
`2010
`
`National Semiconductor, LP2996 DDR Termination Regulator (June
`2006), downloaded from https://datasheet.octopart.com/LP2996MR-
`NOPB-Texas-Instruments-datasheet-7837571.pdf (last visited
`09/08/2022
`
`National Semiconductor, LP2997 DDR-II Termination Regulator
`(June 2006), downloaded from
`https://www.jameco.com/Jameco/Products/ProdDS/843930.pdf (last
`visited 09/08/2022)
`
`National Semiconductor, LP2998 DDR-II and DDR-I Termination
`Regulator (Dec. 12, 2007), downloaded from
`https://www.semiee.com/file/backup/INTERSIL-LP2998.pdf (last
`visited 09/08/2022)
`
`2011
`
`Bergveld, H. J., Battery Management Systems Design by Modeling,
`Royal Philips Electronics N.V. (2001)
`
`ix
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`2012
`
`2013
`
`2014
`
`2015
`
`2016
`
`2017
`
`2018
`
`2019
`
`Description
`Romo, Joaquin, DDR Memories: Comparison and overview, NXP
`technical note, downloaded from
`https://www.nxp.com/docs/en/supporting-
`information/BeyondBits2article17.pdf (last access 09/08/2022). As
`downloaded the file shows the following meta data:
`
`
`JEDEC Standard No. 21-C, PC133 SDRAM Unbuffered SODIMM
`Reference Design Specification Rev. 1.02 (2001)
`
`Qimonda HYB39SC256[80/16]0FE, HYI39SC256[80/16]OFF
`datasheet (June 2007), downloaded from
`https://pdf.dzsc.com/200810211/200809251204372352.pdf (last
`visited 09/08/2022)
`
`Siemens HYS64/72V2200GU-8/-10, HYS64/72V4220GU-8/-10
`datasheet (June 1998), downloaded from
`https://cdn.datasheetspdf.com/pdf-down/P/C/6/PC66-222-
`920_SiemensSemiconductorGroup.pdf (last visited 09/08/2022)
`
`EURESYS, PCI Bus Variation Technical Note (2006), downloaded
`from PCI Bus Variation - Technology Note (euresys.com) (last
`accessed 09/08/2022)
`
`Qimonda HY[B/I]39S256[40/80/16]0FT(L) etc. datasheet
`(September 2007), downloaded from
`https://cms.nacsemi.com/content/AuthDatasheets/QMDAS00628-
`1.pdf (last visited 09/08/2022)
`
`Transcend, What is the difference between SDRAM, DDR1, DDR2,
`DDR3 and DDR4? Downloaded from https://www.transcend-
`info.com/support/faq-296#:~:text=DDR3 (last visited 09/08/2022)
`
`Transcend company profile, https://us.transcend-
`info.com/about/company (last visited 09/08/2022)
`
`2020
`
`Brown, M., Power Supply Cookbook, Newnes (2d.) (2001)
`
`x
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`2021
`
`2022
`
`2023
`
`2024
`
`2025
`
`2026
`
`Texas Instruments, Low Dropout Operation in a Buck Converter
`(SLUA928A, December 2018 — revised March. 2019), downloaded
`from Low Dropout Operation in a Buck Converter (Rev. A) (last
`visited 09/08/2022)
`
`Electronic Design, Simple Soft-Start Circuitry Provides Long Startup
`Times (June 22, 1998), downloaded from
`https://www.electronicdesign.com/powermanagement/
`article/21801244/simple-softstart-circuitry-provides- long-startup-
`times (last visited 09/08/2022)
`
`Micron Technical Note, TN-04-30, Various Methods of DRAM
`Refresh (1999), downloaded from DT30 (reactivemicro.com) (last
`visited 09/08/2022)
`
`Schmid, Patrick, Understanding Hard Drive Performance (March 5,
`2007), downloaded from
`https://www.tomshardware.com/reviews/understanding-hard-drive-
`performance,1557-5.html (last visited 09/08/2022)
`
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/datasheet/dram/256mb_sdr.
`pdf (last visited 09/08/2022)
`
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/datasheet/dram/64mb_x4x8
`x16_sdram.pdf (last visited 09/08/2022)
`
`2027
`
`Transcend, DDR2 SO-DIMM datasheet
`
`2028
`
`Micron Technical Note TN-41-13, DDR3 Point-to-Point Design
`Support Introduction (2013), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/technicalnote/dram/tn4113_
`ddr3_point_to_point_design.pdf (last visited 09/08/2022)
`
`xi
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`2029
`
`Description
`
`PCI Technology Overview (Feb. 2003) downloaded from
`https://web.archive.org/web/20040721012143/http://www.cs.unc.edu
`/Research/stc/FAQs/pci-overview.pdf (Wayback Machine
`(archive.org)) (last visited 09/08/2022)
`
`2030
`
`Deposition transcripts of Dr. Andrew Wolfe with errata (March 16-
`17, 2023)
`
`2031
`Declaration of Dr. William Henry Mangione-Smith
`2032 Markman Order, Netlist, Inc. v. Samsung Electronics Co., Ltd., Civ.
`Action 2:21-cv-00463-JRG, Dkt. 114 (E.D. Tex. filed Dec. 14, 2022)
`
`2033
`
`2034
`
`2035
`
`2036
`
`2037
`
`2038
`
`Samsung’s Objections to Claim Construction Memorandum Order,
`Netlist, Inc. v. Samsung Electronics Co., Ltd., Civ. Action 2:21-cv-
`00463-JRG, Dkt. 136 (E.D. Tex. filed Dec. 29, 2022)
`
`Bruce Jacob et al., Memory Systems: Cache, DRAM, Disk (2008)
`
`Netlist Presentation (excerpt)
`
`AgigA Tech et al., “NVDIMM Hands on Lab,” Flash Memory
`Summit 2014 (Aug. 5-6, 2014), downloaded from
`https://www.snia.org/sites/default/files/FMS%20NVDIMM%20Dem
`o%20SIG%20HOL%20Aug'14%20final.pdf.
`
`Intel, Power Supply Design Guide for Desktop Platform Form
`Factors, Rev. 1.1 (March, 2007), downloaded from
`https://web.archive.org/web/20100601215705/http://www.formfactor
`s.org/developer%5Cspecs%5CPSU_DG_rev_1_1.pdf
`
`Intel, ATX12V, Power Supply Design Guide, Version 2.2 (March
`2005), downloaded from
`https://web.archive.org/web/20070403181612/http://www.formfactor
`s.org/developer/specs/ATX12V_PSDG_2_2_public_br2.pdf
`
`xii
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`2039
`
`2040
`
`2041
`
`2042
`
`2043
`
`2044
`
`2045
`
`IDT, IDTAMB0480 Product Brief (“Advanced Memory Buffer for
`Fully Buffered DIMM Modules) (April 2006), downloaded from
`https://pdf1.alldatasheet.com/datasheetpdf/view/199557/IDT/IDTA
`MB0480.html
`
`Ganesh, B. et. al., Fully-Buffer DIMM Memory Architectures:
`Understanding Mechanisms, Overheads and Scaling, HPCA2007
`
`Chang, K. K. et al., Understanding Reduced-Voltage Operation in
`Modern DRAM Chips: Characterization, Analysis, and Mechanisms,
`arXiv:1705.10292v1 [cs.AR] (May 29, 2017)
`
`Kingston Technology, KVR667D2D4F5/2G FBDIMM datasheet
`(4/14/06), downloaded from
`https://www.kingston.com/dataSheets/KVR667D2D4F5_2G.pdf.
`
`Samsung, Samsung Unveils New Power Management Solutions for
`DDR5 Modules, downloaded from
`https://semiconductor.samsung.com/newsroom/news/samsungunveils
`-new-power-management-solutions-for-ddr5-modules/
`
`Micron, 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2
`SDRAM RDIMM Features (2003), downloaded from https://media-
`www.micron.com/-
`/media/client/global/documents/products/datasheet/modules/rdimm/h
`tf9c32_64_128x72.pdf?rev=ca2587e210f14889ad6fe88e3511e938
`
`Micron, 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM
`SODIMM Features (2008), downloaded from
`https://mediawww.micron.com/-
`/media/client/global/documents/products/datasheet/modules/sodimm/
`htf16c128_256_512x64hz.pdf?rev=2b5a707721a24f4facccd8c86aad
`dfc7
`
`2046
`
`JEDEC Standard No. 21C, 4.20.11 – 200-Pin DDR2 SDRAM
`Unbuffered SO-DIMM Design Specification, Rev. 2.5 (Release 18)
`
`xiii
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`2047
`
`2048
`
`2049
`
`Smart Modular Technologies, SG5127FBD225652-SA FBDIMM
`Datasheet (March 20, 2007), downloaded from
`https://datasheet.ciiva.com/8371/sg5127fbd225652-sa-8371204.pdf
`
`Micron, 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB x72)
`Features (2005), downloaded from
`https://datasheet.octopart.com/MT18HTF12872FDY-667B5E3-
`Micron-datasheet-20608.pdf
`
`Samsung Electronics, DDR2 Fully Buffered DIMM, 240pin
`FBDIMMs based on 1Gb C-Die, Rev. 1.52 (April 2008),
`downloaded from
`https://www.compuram.biz/documents/datasheet/143851ds_ddr2_1g
`b_c-die_based_fbdimm_rev152.pdf
`
`2050
`
`Texas Instruments, TPS51116 Datasheet (2008)
`
`2051
`
`2052
`
`2053
`
`2054
`
`Texas Instruments, Serial Presence Detect (1998), downloaded from
`http://www.ti.com/lit/pdf/smmu001
`
`Mikhaylov, K., Evaluation of Power Efficiency for Digital Serial
`Interfaces of Microcontrollers, 2012 5th Int’l Conference on New
`Technologies, Mobility and Security (NTMS)
`
`Dell Perc H700 G5V20 SAS PCIe x8 RAID Controller 1GB NV
`Cache Adapter (image)
`
`“TI ATI unveils next-generation 3-A DDR termination regulator,”
`downloaded from https://www.electronicproducts.com/ti-unveils-
`next-generation-3-a-ddr-termination-regulatorlinear-regulator-
`supports-ddr3-power-requirements-for/
`
`2055
`
`JEDEC, TG401_1, VR on DIMM TG Report (Dec. 2011)
`
`2056
`
`Deposition transcripts of Dr. Andrew Wolfe with errata (March
`January 4, 2023)
`
`xiv
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`2057
`
`2058
`
`2059
`
`2060
`
`2061
`
`2062
`
`2063
`
`2064
`
`2065
`
`2066
`
`Micron DDR5: Key Module Features, downloaded from
`https://media-www.micron.com/-
`/media/client/global/documents/products/technical-
`marketingbrief/ddr5_key_module_features_tech_brief.pdf?la=zhtw&
`rev=f3ca96bed7d9427ba72b4c192dfacb56
`
`EPA, Report to Congress on Server and Data Center Energy
`Efficiency (Aug. 2, 2007), downloadable from
`https://www.osti.gov/servlets/purl/929723-4d6s1A/
`
`Intel, Fully Buffered DIMM Server Memory Architecture: Capacity,
`Performance, Reliability and Longevity (Feb. 18, 2004), downloaded
`from
`https://www.bestor.spb.ru/v3/Content/pdf/OSA_S008_FBDIMM-
`Arch.pdf
`
`Declaration of Jason Sheasby iso PHV Motion
`
`Reserved
`
`Reserved
`
`Patent Owner’s Demonstratives
`
`Patent Owner’s Demonstratives as served 9.1.23
`
`Declaration of Boe Holbrook iso Micron's Opposed Motion to
`Transfer Venue under 28 U.S.C. § 1404(a), Civ. Action 1:22-cv-
`00136-DII, Dkt. 32-1 (W.D. Tex. filed Nov. 24, 2021)
`
`Plaintiff Netlist, Inc.'s First Notice of Deposition of Defendants
`Micron Technology, Inc., Micro Semiconductor Products, Inc., and
`Micron Technology Texas, Civ. Action 2:22-CV-203-JRG (E.D.
`Tex. May 15, 2023)
`
`2067
`
`Email from Petitioner re Micron's updated 30(b)(6) designations
`(Aug. 9, 2023)
`
`2068
`
`Email from Petitioner re Deposition Dates (Aug. 3, 2023)
`
`xv
`
`
`
`

`

`
`
`
`
`
`
`
`Exhibit #
`
`2069
`
`2070
`
`2071
`
`Description
`
`Email from Patent Owner re De-Designation Request
`
`Boe Holbrook's LinkedIn Resume
`
`[Corrected] Complaint, Civ. Action 2:22-CV-203-JRG-RSP, Dkt.
`#004 (E.D. Tex., June 10, 2022)
`
`2101
`
`Wolfe Deposition exhibit, FB-DIMM Design Considerations (Feb.
`18, 2004), downloaded from
`https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=e
`1c8e931ff9f54dc673973af4b1044daec6883e8
`2102 Wolfe Deposition exhibit, Linear Technology PCI Express Power
`and Mini Card Solutions
`
`
`
`xvi
`
`
`
`

`

`
`
`
`
`CLAIM LISTING
`
`Ref. #
`1.a
`
`1.b
`
`1.c
`
`1.d
`
`1.e
`
`1.f
`
`1.g
`
`1.h
`
`1.i
`
`2
`
`Listing of Challenged Claims
`1. A memory module comprising:
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`a first buck converter configured to provide a first regulated voltage
`having a first voltage amplitude;
`a second buck converter configured to provide a second regulated
`voltage having a second voltage amplitude;
`a third buck converter configured to provide a third regulated voltage
`having a third voltage amplitude;
`a converter circuit configured to provide a fourth regulated voltage
`having a fourth voltage amplitude; and
`a plurality of components coupled to the PCB, each component of the
`plurality of components coupled to one or more regulated voltages of
`the first, second, third and fourth regulated voltages, the plurality of
`components comprising:
`a plurality of synchronous dynamic random access memory (SDRAM)
`devices coupled to the first regulated voltage, and
`[1] at least one circuit coupled between a first portion of the plurality of
`edge connections and the plurality of SDRAM devices,
`[2] the at least one circuit operable to (i) receive a first plurality of
`address and control signals via the first portion of the plurality of edge
`connections, and (ii) output a second plurality of address and control
`signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated voltage
`and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`2. The memory module of claim 1, wherein the first and third buck
`converters are further configured to operate as a dual buck converter.
`
`xvii
`
`
`
`

`

`
`
`
`
`Ref. #
`3
`
`4
`5.a
`
`5.b
`
`6
`
`7
`
`8.a
`
`8.b
`
`9
`
`10.a
`
`10.b
`
`Listing of Challenged Claims
`3. The memory module of claim 1, wherein the first voltage amplitude
`is 1.8 volts.
`4. The memory module of claim 1, wherein the second, third, and fourth
`voltage amplitudes are 2.5 volts, 1.2 volts, and 3.3 volts, respectively.
`5. The memory module of claim 1, further comprising:
`a voltage monitor circuit configured to monitor a power input voltage
`received via a second portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a trigger signal in
`response to the power input voltage having a voltage amplitude that is
`greater than a first threshold voltage.
`6. The memory module of claim 5, wherein the voltage monitor circuit
`is further configured to produce the trigger signal in response to the
`power input voltage having a voltage amplitude that is less than a
`second threshold voltage.
`7. The memory module of claim 6, wherein the second threshold voltage
`corresponds to a voltage level that is ten percent less than a specified
`operating voltage.
`8. The memory module of claim 1, the plurality of components further
`comprising:
`[1] one or more registers coupled to one of the first, second, third and
`fourth regulated voltages,
`[2] the one or more registers configured to register, in response to a
`clock, the first plurality of address and control signals,
`[3] wherein the one of the first, second, third and fourth regulated
`voltages is selectively switched off to turn power off to the one or more
`registers while one or more components of the plurality of components
`are powered on.
`9. The memory module of claim 5, wherein the first threshold voltage
`corresponds to a voltage level that is ten percent greater than a specified
`operating voltage.
`The memory module of claim 5, the plurality of components further
`comprising:
`a logic element including a non-volatile memory, the non-volatile
`memory is configured to store configuration information.
`
`xviii
`
`
`
`

`

`
`
`
`
`Ref. #
`
`11
`
`12.a
`12.b
`
`12.c
`
`13
`
`14
`
`15.a
`
`15.b
`
`Listing of Challenged Claims
`11. The memory module of claim 10, wherein, in response to the trigger
`signal, the logic element writes information into the non-volatile
`memory.
`12. The memory module of claim 5, the plurality of components further
`comprising:
`a non-volatile memory; and
`a controller configured to receive the trigger signal, wherein, in
`response to the trigger signal, the controller performs a write operation
`to the non-volatile memory.
`13. The memory module of claim 5, wherein the power input voltage is
`coupled to the first, second, and third buck converters and the converter
`circuit.
`14. The memory module of claim 8, wherein, in response to selectively
`switching on the one of the first, second, third and fourth regulated
`voltages to the one or more registers, the one or more registers is
`configured to output the registered first plurality of address and control
`signals to the plurality of SDRAM devices.
`15. The memory module of claim 1, the plurality of components further
`comprising:
`a logic element including one or more integrated circuits and discrete
`electrical elements, the one or more integrated circuit including an
`internal non-volatile memory, wherein the non-volatile memory is
`configured to store configuration information.
`16.a A memory module comprising:
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`first, second, and third buck converters configured to receive a pre-
`regulated input voltage and to produce first, second and third regulated
`voltages, respectively;
`
`16.b
`
`16.c
`
`xix
`
`
`
`

`

`
`
`
`
`Ref. #
`
`16.d
`
`16.e
`
`16.f
`
`17
`
`18.a
`
`18.b
`
`19
`
`20
`
`21.a
`
`Listing of Challenged Claims
`[1] a converter circuit configured to reduce the pre-regulated input
`voltage to provide a fourth regulated voltage,
`[2] wherein the first, second, third and fourth regulated voltages have
`first, second, third, and fourth voltage amplitudes, respectively;
`a plurality of components coupled to the PCB, the plurality of
`components including a plurality of synchronous dynamic random
`access memory (SDRAM) devices, each component of the plurality of
`components coupled to one or more regulated voltages of the first,
`second, third and fourth regulated voltages; and
`a voltage monitor circuit configured to monitor an input voltage
`received via a first portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a signal in response to the
`input voltage having a voltage amplitude that is greater than a first
`threshold voltage.
`17. The memory module of claim 16, wherein the second and third buck
`converters are configured to operate as a dual buck converter.
`18. The memory module of claim 16, the plurality of components
`further including:
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein the controller executes a write operation in
`response to the signal.
`19. The memory module of claim 18, wherein the write operation
`includes writing data information into non-volatile memory.
`20. The memory module of claim 16, wherein the plurality of SDRAM
`devices are configured to receive at least one of the first, second, third
`and fourth regulated voltages having a voltage amplitude of 1.8 volts.
`21. The memory module of claim 16, the plurality of components
`further including:
`
`xx
`
`
`
`

`

`
`
`
`
`Ref. #
`
`21.b
`
`Listing of Challenged Claims
`[1] at least one circuit coupled between the interface and the plurality of
`SDRAM devices,
`[2] the at least one circuit operable to receive a first plurality of address
`and control signals via a second portion of the plurality of edge
`connections and to output a second plurality of address and control
`signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated voltage
`and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`22. The memory module of claim 16, the plurality of components
`further including:
`a logic element including an internal non-volatile memory, wherein the
`non-volatile memory is configured to store configuration information,
`wherein the configuration information is used to program the logic
`element.
`23.a A memory module comprising:
`
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`[1] a plurality of components coupled to the PCB, each component of
`the plurality of components coupled to one or more regulated voltages
`of first, second, third and fourth regulated voltages,
`[2] the plurality of components including a plurality of synchronous
`dynamic random access memory (SDRAM) devices and one or more
`registers, the plurality of SDRAM devices coupled to the first regulated
`voltage, the one or more registers coupled to (i) the second regulated
`voltage, (ii) a portion of the plurality of edge connections, and (iii) the
`plurality of SDRAM devices,
`[3] wherein a plurality of address and control signals are coupled to the
`one or more registers via the portion of the plurality of edge
`connections;
`first, second, and third buck converters configured to provide the first,
`second and third regulated voltages, respectively; and
`
`22.a
`
`22.b
`
`23.b
`
`23.c
`
`23.d
`
`xxi
`
`
`
`

`

`
`
`
`
`Ref. #
`23.e
`
`23.f
`
`23.g
`
`23.h
`
`24.a
`
`24.b
`
`25.a
`
`25.b
`
`26
`
`27
`
`28
`
`29
`
`Listing of Challenged Claims
`a converter circuit configured to provide the fourth regulated voltage,
`wherein the second regulated voltage is configured to be selectively
`switched on or off to the one or more registers while at least the plurality
`of SDRAM devices are powered on,
`wherein if the second regulated voltage is switched on while at least the
`plurality of SDRAM devices are powered on, the one or more registers
`are configured to couple the first plurality of address and control signals
`to the plurality of SDRAM devices, and
`wherein if the second regulated voltage is switched off while the
`plurality of SDRAM devices are powered on, the one or more registers
`are configured to decouple the plurality of SDRAM devices from the
`first plurality of address and control signals.
`24. The memory module of claim 23, further comprising:
`a voltage monitor circuit configured to monitor an input voltage
`received from the host system via the interface, the voltage monitor
`circuit configured to produce a signal in response to the input voltage
`having a voltage amplitude that is greater than a first threshold voltage.
`25. The memory module of claim 24, the plurality of components
`further including:
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein, in response to the signal, the controller
`executes a write operation.
`26. The memory module of claim 25, wherein the write operation
`includes writing data information to non-volatile memory.
`27. The memory module of claim 24, wherein the voltage monitor
`circuit is further configured to produce the signal in response to the
`input voltage having a voltage amplitude that is less than a second
`thresho