`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`NETLIST, INC.
`
`Plaintiff,
`
`
`
`v.
`
`MICRON TECHNOLOGY, INC.,
`MICRON SEMICONDUCTOR
`PRODUCTS, INC., MICRON
`TECHNOLOGY TEXAS LLC,
`
`Defendants.
`
`JURY TRIAL DEMANDED
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`COMPLAINT
`
`1.
`
`Plaintiff Netlist, Inc. (“Netlist”), by its undersigned counsel, for its Complaint
`
`against defendants Micron Technology Inc. (“Micron Technology”), Micron Semiconductor
`
`Products, Inc. (“Micron Semiconductor”), and Micron Technology Texas, LLC (“Micron Texas”)
`
`(collectively, “Micron” or “Defendants”), states as follows, with knowledge as to its own acts, and
`
`on information and belief as to the acts of others:
`
`2.
`
`This action involves six of Netlist’s patents: U.S. Patent Nos. 10,860,506 (the “’506
`
`Patent,” Ex. 1), 10,949,339 (the “’339 Patent,” Ex. 2), 11,016,918 (the “’918 Patent,” Ex. 3),
`
`11,232,054 (the “’054 Patent,” Ex. 4), 8,787,060 (the “’060 Patent,” Ex. 5), and 9,318,160 (the
`
`“’160 Patent,” Ex. 6) (collectively, the “Patents-in-Suit”).
`
`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 2 of 71 PageID #: 462
`
`I.
`
`THE PARTIES
`
`3.
`
`Plaintiff Netlist is a corporation organized and existing under the laws of the State
`
`of Delaware, having a principal place of business at 111 Academy Drive, Suite 100, Irvine, CA
`
`92617.
`
`4.
`
`On information and belief, Micron makes dynamic random-access memory
`
`(“DRAM”), NAND Flash, and NOR Flash memory, and other memory products in semiconductor
`
`fabrication plants in the United States and other countries throughout the world. On information
`
`and belief, Micron sells its products to customers, including customers in this District, in the
`
`computer, networking and storage, consumer electronics, solid-state drives and mobile
`
`telecommunications markets.
`
`5.
`
`On information and belief, Micron Technology is a corporation organized and
`
`existing under the laws of Delaware. On information and belief, Micron Technology has a regular
`
`and established place of business at 805 Central Expressway South, Suite 100, Allen, Texas 75013.
`
`On information and belief, Micron Technology is registered to do business in the State of Texas,
`
`and can be served through its registered agent, The Corporation Service Company, 211 E. 7th
`
`Street, Suite 620, Austin, Texas 78701-3218.
`
`6.
`
`On information and belief, Micron Semiconductor is a corporation organized and
`
`existing under the laws of Idaho. On information and belief, Micron Semiconductor has a regular
`
`and established place of business at 805 Central Expressway South, Suite 100, Allen, Texas 75013.
`
`On information and belief, Micron Semiconductor is registered with the Texas Secretary of State
`
`to do business in Texas. On information and belief, Micron Semiconductor can be served through
`
`its registered agent, The Corporation Service Company, 211 E. 7th Street, Suite 620, Austin, Texas
`
`78701-3218.
`
`- 2 -
`
`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 3 of 71 PageID #: 463
`
`7.
`
`On information and belief, Micron Texas is a corporation organized and existing
`
`under the laws of Idaho. On information and belief, Micron Texas has a regular and established
`
`place of business at 805 Central Expressway South, Suite 100, Allen, Texas 75013. On
`
`information and belief, Micron Texas also has a regular and established place of business at 950
`
`West Bethany Drive, Suite 120, Allen, Texas 75013-3837. On information and belief, Micron
`
`Texas is registered with the Texas Secretary of State to do business in Texas. On information and
`
`belief, Micron Texas can be served through its registered agent, The Corporation Service
`
`Company, 211 E. 7th Street, Suite 620, Austin, Texas, 78701-3218.
`
`8.
`
`On information and belief, Micron Semiconductor and Micron Texas are wholly
`
`owned subsidiaries of Micron Technology. On information and belief, Micron Technology does
`
`not separately report revenue from Micron Semiconductor or Micron Texas in its filings to the
`
`Securities Exchange Commission, but rather reports combined revenue from its various products
`
`and subsidiaries.
`
`9.
`
`On information and belief, Defendants have semiconductor fabrication plants in the
`
`United States and other countries throughout the world and manufacture memory products such as
`
`DRAM, NAND Flash, and NOR Flash at those plants. On information and belief, Defendants also
`
`use, sell, and offer for sale in the United States, import into the United States and/or export from
`
`the United States memory products, including DDR4 load reduced dual in-line memory modules
`
`(“LRDIMMs”), DDR5 dual in-line memory modules (“DIMMs”), HBM2E memory components,
`
`and other high bandwidth memory products and components, or unfinished versions thereof
`
`(“Accused Instrumentalities”). On information and belief, Defendants have at least used, sold, or
`
`offered to sell products and services, including the Accused Instrumentalities, in this judicial
`
`district, e.g., through sales and distribution channels managed by Micron Texas.
`
`- 3 -
`
`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 4 of 71 PageID #: 464
`
`10.
`
`On information and belief, Defendants place, have placed, and contributed to
`
`placing Accused Instrumentalities into the stream of commerce via an established distribution
`
`channel knowing or understanding that such products would be sold and used in the United States,
`
`including in this judicial district. On information and belief, Defendants have also derived
`
`substantial revenues from infringing acts in this judicial district, including from the sale and use
`
`of the Accused Instrumentalities.
`
`II.
`
`JURISDICTION AND VENUE
`
`11.
`
`The Court has subject matter jurisdiction under 28 U.S.C. § 1338, in that this action
`
`arises under federal statute, the patent laws of the United States (35 U.S.C. §§ 1, et seq.).
`
`12.
`
`Each Defendant is subject to this Court’s personal jurisdiction consistent with the
`
`principles of due process and/or the Texas Long Arm Statute.
`
`13.
`
`Personal jurisdiction exists generally over the Defendants because each Defendant
`
`has sufficient minimum contacts and/or has engaged in continuous and systematic activities in the
`
`forum as a result of business conducted within the State of Texas and the Eastern District of Texas.
`
`Personal jurisdiction also exists over each Defendant because each, directly or through
`
`subsidiaries, makes, uses, sells, offers for sale, imports, advertises, makes available, and/or
`
`markets products within the State of Texas and the Eastern District of Texas that infringe one or
`
`more claims of the Patents-in-Suit. Further, on information and belief, Defendants have placed or
`
`contributed to placing infringing products into the stream of commerce knowing or understanding
`
`that such products would be sold and used in the United States, including in this District.
`
`14.
`
`Venue is proper in this Court pursuant to 28 U.S.C. §§ 1391(b) and (c) and/or
`
`1400(b) because Defendants (1) have committed and continue to commit acts of patent
`
`infringement in this District by, among other things, directly and/or indirectly making, using,
`
`selling, offering to sell, or importing products that infringe one or more claims of the Patents-in-
`
`- 4 -
`
`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 5 of 71 PageID #: 465
`
`Suit, and (2) have done and continue to do business in this District by maintaining regular and
`
`established places of business, including at least at 805 Central Expressway South, Suite 100,
`
`Allen, Texas 75013.
`
`III.
`
`FACTUAL ALLEGATIONS
`
`Background
`
`15.
`
`Since its founding in 2000, Netlist has been a leading innovator in high-
`
`performance memory module technologies. Netlist designs and manufactures a wide variety of
`
`high-performance products for the cloud computing, virtualization and high-performance
`
`computing markets. Netlist’s technology enables users to derive useful information from vast
`
`amounts of data in a shorter period of time. These capabilities will become increasingly valuable
`
`as the volume of data continues to dramatically increase.
`
`16.
`
`Netlist has a long history of being the first to market with disruptive new products
`
`such as the first LRDIMM, HyperCloud®, based on Netlist’s distributed buffer architecture later
`
`adopted by the industry for DDR4 LRDIMM. Netlist was also the first to bring NAND flash to
`
`the memory channel with its NVvault® NVDIMM. These innovative products built on Netlist’s
`
`early pioneering work in areas such as embedding passives into printed circuit boards to free up
`
`board real estate, doubling densities via quad-rank double data rate (“DDR”) technology, and other
`
`off-chip technology advances that result in improved performance and lower costs compared to
`
`conventional memory.
`
`17.
`
`In many commercial products, a memory module is a printed circuit board that
`
`contains, among other components, a plurality of individual memory devices (such as DRAMs).
`
`The memory devices are typically arranged in “ranks,” which are accessible by a processor or
`
`memory controller of the host system. A memory module is typically installed into a memory slot
`
`on a computer motherboard.
`
`- 5 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 6 of 71 PageID #: 466
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`18. Memory modules are designed for, among other things, use in servers such as those
`
`supporting cloud-based computing and other data-intensive applications (e.g. scaled data
`
`manipulation and aggregation, on-demand tracking, AI-based image analysis, weather patterning,
`
`etc.). The structure, function, and operation of memory modules is defined, specified, and
`
`standardized by the JEDEC Solid State Technology Association (“JEDEC”), the standard-setting
`
`body for the microelectronics industry. Memory modules are typically characterized by, among
`
`other things, the generation of DRAM on the module (e.g., DDR5, DDR4, DDR3) and the type of
`
`module (e.g., RDIMM, LRDIMM).
`
`19.
`
`High bandwidth memory (“HBM”) is a type of high-speed computer memory
`
`technology that relies in part on vertically stacked memory dies. In end products incorporating
`
`HBMs, a memory host such as a CPU and/or GPU is interconnected to a logic/driver/buffer die at
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`the bottom of each memory die stack. The combined system of CPU/GPU and the memory stack
`
`is then mounted on a substrate for use, as illustrated below. This format substantially shortens the
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`signal length between the host and the memory, which enables shorter communication time,
`
`smaller format, higher performance and lower power consumption.
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`- 6 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 7 of 71 PageID #: 467
`
`
`Ex. 9 (Micron Technical Brief “Integrating and Operating HBM2E Memory”) at 3 (annotations in
`
`original); see also, e.g., Ex. 11 (Micron white paper titled “The Demand for High-Performance
`
`Memory”) at 2:
`
`
`
`The Asserted Netlist Patents
`
`The ’506 Patent
`
`20.
`
`The ’506 Patent is entitled “Memory Module With Timing-Controlled Data
`
`Buffering.” Netlist owns the ’506 Patent by assignment from the listed inventors Hyun Lee and
`
`Jayesh R. Bhakta. The ’506 Patent was filed as Application No. 16/391,151 on April 22, 2019,
`
`issued as a patent on December 8, 2020, and claims priority to, among others, a utility application
`
`filed on July 27, 2013 (No. 13/952,599) and a provisional application filed on July 27, 2012 (No.
`
`61/676,883).
`
`21. Micron has had actual knowledge of the ’506 Patent no later than April 28, 2021
`
`via Exhibit A to Netlist’s April 28, 2021 letter to Micron, and as of the filing of this Complaint.
`
`22.
`
`As described in the ’506 Patent, in conventional memory modules, the “distribution
`
`of control signals and a control clock signal in the memory module is subject to strict constraints”
`
`to ensure that memory devices on the memory module can be properly accessed. Ex. 1 at 2:18-
`
`20. For example, in some conventional memory modules, “control wires are routed so there is an
`
`equal length to each memory component, in order to eliminate variation of the timing of the control
`
`
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`- 7 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 8 of 71 PageID #: 468
`
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`signals and the control clock signal between different memory devices in the memory modules.”
`
`Id. at 2:20-24. But as noted in the ’506 Patent, “[t]he balancing of the length of the wires to each
`
`memory devices compromises system performance, limits the number of memory devices, and
`
`complicates their connections.” Id. at 2:24-27. In yet other conventional memory systems, the
`
`memory controller includes mechanisms such as read or write leveling for compensating for
`
`unbalanced wire lengths on the memory module. Id. at 2:28-32. However, with increasing
`
`memory operating speed and memory density “such leveling mechanisms are also insufficient to
`
`ensure proper timing of the control and/or data signals received and/or transmitted by the memory
`
`modules.” Id. at 2:32-36.
`
`23.
`
`The ’506 Patent discloses a memory module operable in a memory system with a
`
`memory controller that includes memory devices, a module control circuit, and a plurality of buffer
`
`circuits coupled between respective sets of data signal lines in a data bus and respective sets of the
`
`memory devices. As summarized in the Abstract, “[e]ach respective buffer circuit is configured
`
`to receive the module control signals and the module clock signal, and to buffer a respective set of
`
`data signals in response to the module control signals and the module clock signal. Each respective
`
`buffer circuit includes a delay circuit configured to delay the respective set of data signals by an
`
`amount determined based on at least one of the module control signals.” Id., Abstract.
`
`
`
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`- 8 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 9 of 71 PageID #: 469
`
`
`
`24.
`
`The buffer circuits (118, highlighted below) are associated with respective groups
`
`of memory devices and are distributed across the memory module at positions corresponding to
`
`the respective groups of memory devices as illustrated in the exemplary configuration of Figure
`
`2A.
`
`
`
`25.
`
`However, because the buffer circuits—or “isolation devices”—are distributed
`
`across the memory module, at high speeds of operation, the same set of module control signals
`
`sent by the module control circuit in the module may reach different buffer circuits at different
`
`times across one cycle of the system clock. Id. at 9:51-62 (“Because the isolation devices 118 are
`
`distributed across the memory module 110, during high speed operations, it may take more than
`
`one clock cycle time of the system clock MCK for the module control signals to travel along the
`
`module control signals lines 230 from the module control device 116 to the farthest positioned
`
`isolation devices 118, such as isolation device ID-1 and isolation device ID-(n−1) in the exemplary
`
`configuration shown in FIG. 2.”). The ’506 Patent discloses an embodiment wherein “each
`
`isolation devices includes signal alignment circuits that determine, during a write operation, a time
`
`
`
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`- 9 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 10 of 71 PageID #: 470
`
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`interval between a time when one or more module control signals are received from the module
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`control circuit 116 and a time when a write strobe or write data signal is received from the MCH
`
`101. This time interval is used during a subsequent read operation to time the transmission of read
`
`data to the MCH 101, such that the read data follows a read command by a read latency value
`
`associated with the system 100.” Id. at 10:11-21.
`
`The ’339 Patent
`
`26.
`
`The ’339 Patent is entitled “Memory Module With Controlled Byte-Wise Buffers.”
`
`Netlist owns the ’339 Patent by assignment from the listed inventors Hyun Lee and Jayesh R.
`
`Bhakta. The ’339 Patent was filed as Application No. 15/470,856 on March 27, 2017, issued as a
`
`patent on March 16, 2021, and claims priority to U.S. Patent Application No. 12/504,131 filed on
`
`July 16, 2009, U.S. Patent Application No. 12/761,179 filed on April 15, 2010 and U.S.
`
`Application No. 13/970,606 filed on August 20, 2013.
`
`27. Micron has had actual knowledge of the ’339 Patent no later than April 28, 2021
`
`via Exhibit A to Netlist’s April 28, 2021 letter to Micron, and as of the filing of this Complaint.
`
`28.
`
`As described in the ’339 Patent, in optimizing performance of memory subsystems
`
`(e.g. memory modules) “consideration is always given to memory density, power dissipation (or
`
`thermal dissipation, speed, and cost.” Ex. 2 at 2:5-7. The ’339 Patent further explains that
`
`“[g]enerally, these attributes are not orthogonal to each other, meaning that optimizing one
`
`attribute may detrimentally affect another attribute. For example, increasing memory density
`
`typically causes higher power dissipation, slower operational speed, and higher costs.” Id. at 2:7-
`
`12. The ’339 Patent is generally directed to a memory module optimized to reduce the load
`
`experienced by a system memory controller via the use of configurable data transmission circuits.
`
`29.
`
`The ’339 Patent discloses a memory module configured to communicate with a
`
`memory controller that includes DDR DRAM devices arranged in multiple ranks each of the same
`
`
`
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`- 10 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 11 of 71 PageID #: 471
`
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`width as the memory module, and a module controller configured to receive and register input
`
`control signals for a read or write operation from the memory controller and to output registered
`
`address and control signals. As summarized in the Abstract, “[t]he registered address and control
`
`signals selects one of the multiple ranks to perform the read or write operation. The module
`
`controller further outputs a set of module control signals in response to the input address and
`
`control signals. The memory module further comprises a plurality of byte-wise buffers controlled
`
`by the set of module control signals to actively drive respective byte-wise sections of each data
`
`signal associated with the read or write operation between the memory controller and the selected
`
`rank.” Id., Abstract.
`
`30.
`
`Figure 3A illustrates an example of a memory subsystem consistent with
`
`embodiments disclosed in the ’339 Patent.
`
`31.
`
`As shown above, Figure 3A depicts a memory subsystem 400 including memory
`
`modules 402 comprising memory devices 412, data transmission circuits 416 (highlighted above),
`
`and module control circuits 430. The data transmission circuits 416 operate to reduce the load
`
`
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`- 11 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 12 of 71 PageID #: 472
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`experienced by the memory controller 420 to improve performance of a read or write operation.
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`Id. at 17:14-44 (“Referring again to FIG. 3A, when the memory controller 420 executes read or
`
`write operations, each specific operation is targeted to a specific one of the ranks A, B, C, and D
`
`of a specific memory module 402. The data transmission circuit 416 on the specifically targeted
`
`one of the memory modules 402 functions as a bidirectional repeater/multiplexor, such that it
`
`drives the data signal when connecting from the system memory controller 420 to the memory
`
`devices 412. The other data transmission circuits 416 on the remaining memory modules 402 are
`
`disabled for the specific operation. . . . Thus, the memory controller 420, when there are four four-
`
`rank memory modules, sees four load-reducing switching circuit loads, instead of sixteen memory
`
`device loads. The reduced load on the memory controller 420 enhances the performance and
`
`reduces the power requirements of the memory system . . . .”). In certain embodiments, “the data
`
`transmission circuit 416 comprises or functions as a byte-wise buffer. In certain such
`
`embodiments, each of the one or more data transmission circuits 416 has the same bit width as
`
`does the associated memory devices 412 per rank to which the data transmission circuit 416 is
`
`operatively coupled.” Id. at 13:31-36.
`
`The ’918 Patent
`
`32.
`
`The ’918 Patent is entitled “Flash-DRAM Hybrid Memory Module.” Netlist owns
`
`the ’918 Patent by assignment from the listed inventors Chi-She Chen, Jeffrey C. Solomon, Scott
`
`H. Milton, and Jayesh Bhakta. The ’918 Patent was filed as Application No. 17/138,766 on
`
`December 30, 2020, issued as a patent on May 25, 2021, and claims priority to, among others, U.S.
`
`Application No. 13,559,476 filed on July 26, 2012; U.S. Application No. 12/240,916 filed on
`
`September 29, 2008; U.S. Application No. 12/131,873 filed on June 2, 2008; as well as to two
`
`provisional applications, filed on June 1, 2007 (No. 60/941,586) and July 28, 2011 (No.
`
`61/512,871).
`
`
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`- 12 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
`
`
`
`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 13 of 71 PageID #: 473
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`
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`33. Micron has had actual knowledge of the ’918 Patent since at least the filing of this
`
`Complaint.
`
`34.
`
`As summarized in the Abstract, the ’918 Patent discloses a memory module that
`
`includes a printed circuit board with an interface that couples it to a host system for provision of
`
`power, data, address and control signals, and additionally features “[f]irst, second, and third buck
`
`converters [that] receive a pre-regulated input voltage and produce first, second and third regulated
`
`voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated
`
`voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or
`
`more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage
`
`monitor circuit monitors an input voltage and produces a signal in response to the input voltage
`
`having a voltage amplitude that is greater than a threshold voltage.” Ex. 3, Abstract.
`
`35.
`
`The ’918 Patent discloses, inter alia, a power module that provides power to various
`
`components of the memory system as depicted in Figure 16, shown below.
`
`
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
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`
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`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 14 of 71 PageID #: 474
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`36.
`
`The ’918 Patent explains that “[t]he power module 1100 provides a plurality of
`
`voltages to the memory system 1010 comprising non-volatile and volatile memory subsystems
`
`1030, 1040. The plurality of voltages comprises at least a first voltage 1102 and a second voltage
`
`1104. The power module 1100 comprises an input 1106 providing a third voltage 1108 to the
`
`power module 1100 and a voltage conversion element 1120 configured to provide the second
`
`voltage 1104 to the memory system 1010. The power module 1100 further comprises a first power
`
`element 1130 configured to selectively provide a fourth voltage 1110 to the conversion element
`
`1120. In certain embodiments, the first power element 1130 comprises a pulse-width modulation
`
`power controller.” Id. at 28:3-15. “The conversion element 1120 can comprise one or more buck
`
`converters and/or one or more buck-boost converters.” Id. at 29:18-19.
`
`37.
`
`The ’918 Patent also provides for voltage monitor circuit that, in response to
`
`detected over-voltage or under-voltage conditions, produces a trigger signal, which may in turn
`
`cause a logic element to write information into a non-volatile memory that is configured to store
`
`configuration information. See, e.g., id. at 38:61-39:5, 39:23-36. As explained in the ’918 Patent,
`
`in certain embodiments, “the non-volatile memory subsystem 1040 may backup the volatile
`
`memory subsystem 1030 in the event of a trigger condition, such as, for example, a power failure
`
`or power reduction or a request from the host system,” or where “the memory system 1010 detects
`
`that the system voltage is below [or above] a certain threshold voltage,” e.g. ten percent below or
`
`above a specified operating voltage. See, e.g., id. at 24:9-32, 39:6-8, 39:19-22.
`
`38.
`
`This design represents a fundamental and innovative departure from prior
`
`generations of DDR modules for which the voltage regulation was provided by power management
`
`units located on motherboards, external to the DDR modules. In contrast, the ’918 Patent (as well
`
`as its continuation, the ’054 Patent, discussed below), moves the voltage regulation and many other
`
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`- 14 -
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`Netlist EX2071
`Samsung v Netlist
`IPR2022-00996
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`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 15 of 71 PageID #: 475
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`power management functions into the DDR modules themselves, therefore allowing for more
`
`precise and accurate regulation of voltages and more efficient power management.
`
`39.
`
`The inventions of the ’918 Patent provide for the effective operation of DDR5
`
`memory modules, by enabling, among other benefits, greater power efficiency than previous
`
`generations of DDR technology. The DDR5 standard is characterized by the use of an on-module
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`power management system.
`
`The ’054 Patent
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`40.
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`The ’054 Patent is entitled “Flash-DRAM Hybrid Memory Module.” Netlist owns
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`the ’054 Patent by assignment from the listed inventors Chi-She Chen, Jeffrey C. Solomon, Scott
`
`H. Milton, and Jayesh Bhakta. The ’054 Patent was filed as Application No. 17/328,019 on May
`
`24, 2021, issued as a patent on January 25, 2022, and claims priority to, among others, U.S.
`
`Application No. 13,559,476 filed on July 26, 2012; U.S. Application No. 12/240,916 filed on
`
`September 29, 2008; U.S. Application No. 12/131,873 filed on June 2, 2008; as well as to two
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`provisional applications, filed on June 1, 2007 (No. 60/941,586) and July 28, 2011 (No.
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`61/512,871).
`
`41.
`
`Defendants have had actual knowledge of the ’054 Patent since at least the filing of
`
`this Complaint.
`
`42.
`
`As summarized in the Abstract, the ’054 Patent discloses a memory module that
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`includes a printed circuit board with an interface that couples it to a host system for provision of
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`power, data, address and control signals, and additionally features “[f]irst, second, and third buck
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`converters [that] receive a pre-regulated input voltage and produce first, second and third regulated
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`voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated
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`voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or
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`more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage
`
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`IPR2022-00996
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`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 16 of 71 PageID #: 476
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`monitor circuit monitors an input voltage and produces a signal in response to the input voltage
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`having a voltage amplitude that is greater than a threshold voltage.” Ex. 4, Abstract.
`
`43.
`
`The ’054 Patent discloses, inter alia, a power module that provides power to various
`
`components of the memory system as depicted in Figure 16, shown below.
`
`
`
`44.
`
`Like the inventions of the ’918 Patent, the inventions of the ’054 Patent provide for
`
`the effective operation of DDR5 memory modules, by enabling, among other benefits, greater
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`power efficiency than previous generations of DDR technology. See supra, ¶¶ 36-39.
`
`The ’060 and ’160 Patents
`
`45.
`
`The ’060 Patent is entitled “Method and Apparatus for Optimizing Driver Load in
`
`a Memory Package.” Netlist owns the ’060 Patent by assignment from listed inventor Hyun Lee.
`
`The ’060 Patent was filed as Application No. 13/288,850 on November 3, 2011, issued as a patent
`
`on July 22, 2014, and claims priority to a provisional application filed on November 3, 2010 (No.
`
`61/409,893).
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`IPR2022-00996
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`
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`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 17 of 71 PageID #: 477
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`
`
`46.
`
`The ’160 Patent is a continuation of the ‘060 patent and is entitled “Memory
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`Package with Optimized Driver Load and Method of Operation.” Netlist owns the ’160 Patent by
`
`assignment from listed inventor Hyun Lee. The ’160 Patent was filed as Application No.
`
`14/337,168 on July 21, 2014, issued as a patent on April 19, 2016, and claims priority to, among
`
`others, a utility application filed on November 3, 2011 (No. 13/288,850, which issued as the ‘060
`
`patent) and a provisional application filed on November 3, 2010 (No. 61/409,893).
`
`47.
`
`Defendants have had actual knowledge of the ’060 and ’160 Patents since at least
`
`the filing of this Complaint.
`
`48.
`
`The ’060 and ’160 Patents disclose systems and methods for optimizing a load in a
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`memory package featuring a control die, array dies, and numerous die interconnects. In contrast
`
`to traditional DDR modules in which different DRAM devices are packaged individually and then
`
`assembled on a common printed circuit boards, the inventions of the ’060 and ’160 Patents are
`
`directed to DDR packages each having multiple vertically stacked DRAM devices interconnected
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`to a common control circuit, all packaged in the same package.
`
`49.
`
`For example, as summarized in the Abstract, the memory package features at least
`
`two die interconnects, where “[t]he first die interconnect is in electrical communication with a data
`
`port of a first array die and a data port of a second array die and not in electrical communication
`
`with data ports of a third array die. The second die interconnect is in electrical communication
`
`with a data port of the third array die and not in electrical communication with data ports of the
`
`first array die and the second array die.” Ex. 5, Abstract; Ex. 6, Abstract. The memory package’s
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`control die includes “a first data conduit configured to transmit a data signal to the first die
`
`interconnect and not to the second die interconnect, and at least a second data conduit configured
`
`to transmit the data signal to the second die interconnect and not to the first die interconnect.” Id.
`
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`Samsung v Netlist
`IPR2022-00996
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`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 18 of 71 PageID #: 478
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`50.
`
`The ’060 and ’160 Patents explain that in conventional memory packages, the die
`
`interconnects are in communication with each of the array dies, which disadvantageously increases
`
`the load on the data conduit. Ex. 5, at 11:32-40. To address this problem, the ’060 and ’160
`
`Patents disclose memory packages with multiple die interconnects in electrical communication
`
`with some, but not all of the array dies, as illustrated below. Id. at 5:46-6:36.
`
`
`
`51.
`
`As the ’060 and ’160 Patents explain, in the disclosed memory packages “[e]ach of
`
`these die interconnects 320 may be coupled to, or in electrical communication with at least one
`
`port of at least one of the array dies 310. As with the memory package 200, in certain embodiments,
`
`at least one of the die interconnects 320 is in electrical communication with at least one port from
`
`each of at least two array dies 310 without being in electrical communication with a port from at
`
`least one array die 310, which may be in electrical communication with a different die interconnect
`
`320. Id. at 5:54-62 (emphasis added). This enables the memory packages to be designed with
`
`smaller form factor in mind, and lowers power consumption. See id. at 7:22-8:62.
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`IPR2022-00996
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`Case 2:22-cv-00203-JRG-RSP Document 4 Filed 06/10/22 Page 19 of 71 PageID #: 479
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`
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`Micron’s Infringing Activities
`
`52.
`
`Defendants are worldwide semiconductor solution providers that primarily
`
`manufacture semiconductor memory products such as DRAM, DIMMs, and MCP (Multi-Chip
`
`Package), such as