`NETLIST, INC.,
`
`
`Plaintiff,
`
`vs.
`
`)
`)
`)
`)
`
`)
`
`
`)
`)
`MICRON TECHNOLOGY, INC., MICRON
`)
`SEMICONDUCTOR PRODUCTS, INC.,
`)
`AND MICRON TECHNOLOGY TEXAS
`)
`LLC,
`)
`)
`
`UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`
`Civil Action No. 2:22-CV-203-JRG
`
`JURY TRIAL DEMANDED
`
`Filed Under Seal
`
`Defendants.
`
`
`
`PLAINTIFF NETLIST, INC.’S FIRST NOTICE OF DEPOSITION OF DEFENDANTS
`MICRON TECHNOLOGY, INC., MICRON SEMICONDUCTOR PRODUCTS, INC.,
`AND MICRON TECHNOLOGY TEXAS LLC
`
`Please Take Notice that, pursuant to Rule 30(b)(6) of the Federal Rules of Civil
`
`Procedure, and the Local Rules of this Court, Plaintiff Netlist, Inc. (“Netlist”) directs the
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`following interrogatories to defendants Micron Technology, Inc., Micron Semiconductor
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`Products, Inc., and Micron Technology Texas LLC (collectively “Micron” or “Defendants”). The
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`deposition(s) shall take place at a mutually agreeable place and date, beginning at 9:00 am and
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`continuing from day-to-day thereafter (excluding Saturdays, Sundays, and holidays) until
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`completed. The deposition(s) will be conducted pursuant to the Federal Rules of Civil Procedure
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`and will be conducted in the English language before a notary public or other officer authorized
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`to administer oaths. The deposition(s) may be recorded by stenographic means, audiotaped,
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`videotaped, and/or transcribed using real time interactive transcription (e.g., LiveNote).
`
`Pursuant to Federal Rule of Civil Procedure 30(b)(6), Micron shall designate one or more
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`of its officers, directors, managing agents, or other persons who are most knowledgeable, and
`
`competent to testify on its behalf, as to all matters known or reasonably available to Micron with
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`respect to the topics set forth in Attachment A. Pursuant to Federal Rule of Civil Procedure
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`30(b)(6), the person(s) designated should be prepared to testify as to such matters known or
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`reasonably available to Micron. At least five (5) business days before the date set for the
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`deposition(s), Micron shall identify, by name and position, each person so designated and shall
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`set forth the matters on which that person will testify.
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`Netlist reserves the right to serve Micron with additional notices pursuant to Rule 30(b)(6)
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`on additional topics as this litigation progresses and as further evidence is produced.
`
`Dated: May 15, 2023
`
`Respectfully submitted,
`
`/s/ Jason G. Sheasby
`
`Samuel F. Baxter
`Texas State Bar No. 01938000
`sbaxter@mckoolsmith.com
`Jennifer L. Truelove
`Texas State Bar No. 24012906
`jtruelove@mckoolsmith.com
`MCKOOL SMITH, P.C.
`104 East Houston Street Suite 300
`Marshall, TX 75670
`Telephone: (903) 923-9000
`Facsimile: (903) 923-9099
`
`Jason G. Sheasby (pro hac vice)
`jsheasby@irell.com
`Annita Zhong, PhD (pro hac vice)
`hzhong@irell.com
`Thomas C. Werner (pro hac vice)
`twerner@irell.com
`Yanan Zhao (pro hac vice)
`yzhao@irell.com
`Michael W. Tezyan (pro hac vice)
`mtezyan@irell.com
`
`IRELL & MANELLA LLP
`1800 Avenue of the Stars, Suite 900
`Los Angeles, CA 90067
`Tel. (310) 277-1010
`Fax (310) 203-7199
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`Attorneys for Plaintiff Netlist, Inc.
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`ATTACHMENT A
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`DEFINITIONS
`
`Unless the context indicates otherwise, for purposes of these discovery requests, the
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`following words and phrases have the meanings given:
`
`1.
`
`“You,” “Your,” “Micron,” or “Defendant(s)” means Micron Technology, Inc.,
`
`Micron Semiconductor Products, Inc., Micron Technology Texas LLC and any present or
`
`former parent, subsidiary, division, subdivision, affiliated company, licensee, predecessor, or
`
`successor of Micron, and any of its or their present or former officers, directors, agents,
`
`attorneys, consultants, accountants, employees, representatives, investigators, distributors,
`
`salespersons, sales representatives, licensors, licensees, and any other persons acting, or
`
`purporting to act for or on its or their behalf or under its or their control, including but not
`
`limited to experts or persons consulted concerning any factual matter or matters of opinion
`
`relating to any issues involved in the action.
`
`2.
`
`“Netlist” shall mean Netlist, Inc. and all of its affiliates, officers, employees,
`
`agents, representatives, contractors, consultants, attorneys, successors, and assigns.
`
`3.
`
`“Patent” shall mean any United States, international, or foreign classes or types
`
`of patents, utility models, design patents, applications (including provisional applications),
`
`certificates of
`
`invention,
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`reissues, divisionals, continuations, continuations-in-part,
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`extensions, renewals, reexaminations and foreign counterparts thereof. The defined term
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`Patent includes all stated categories of intellectual property regardless of whether those rights
`
`are presently expired or were ever adjudged invalid.
`
`4.
`
`“Netlist Patents-in-Suit” means and refers to one or more of U.S. Patent Nos.
`
`10,860,506 (“’506 Patent”), 10,949,339 (“’339 Patent”), 11,016,918 (“’918 Patent”),
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`11,232,054 (“’054 Patent”), 8,787,060 (“’060 Patent”), and 9,318,160 (“’160 Patent”).
`
`5.
`
`“Third Party” means any individual, entity, organization, partnership, or
`
`corporation that is not a party to this action.
`
`6.
`
`“Micron Accused DDR4 LRDIMMs” shall include any and all Micron Double
`
`Data Rate 4 (“DDR4”) load reduced dual in-line memory modules (“LRDIMMs”), including
`
`ones that its customers further customize.
`
`7.
`
`“Micron Accused DDR5 DIMMs” shall include any and all Micron Double
`
`Data Rate 5 (“DDR5”) dual in-line memory modules, including ones that its customers further
`
`customize.
`
`8.
`
`“Micron Accused HBM Products” shall include any and all Micron HBM2,
`
`HBM2E, HBM3, or HBMnext high bandwidth memory products, including ones that its
`
`customers further customize.
`
`9.
`
`“Micron Accused Products” shall mean any and all Micron Accused DDR4
`
`LRDIMMs, Micron Accused DDR5 DIMMs, and Micron Accused HBM Products.
`
`10.
`
`“Micron Distributor” shall include any person who Micron authorized to sell
`
`any Micron Accused Products.
`
`11.
`
`“Micron Partner” shall include any customers of Micron’s Accused Products
`
`and any other third parties involved in the design, development, manufacture, testing,
`
`assembly, importation, distribution, sourcing, qualification, sale, or offer to sell Micron
`
`Accused Products.
`
`12.
`
`“Micron Supplier” means a natural person or a business entity that supplies
`
`any component involved in the Micron Accused Products or assembled Micron’s Accused
`
`Products in whole or in part. For the purposes of this definition, a co-development relationship
`
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`or a fabrication relationship shall constitute one type of supplier relationship.
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`13.
`
`“Montage” means Montage, Inc. (d/b/a Montage Technologies, Inc.), Montage
`
`Technology, Inc., and any present or former parent, subsidiary, division, subdivision,
`
`affiliated company, licensee, predecessor, or successor of Montage, Inc. and Montage
`
`Technology, Inc., and any of its or their present or former officers, directors, agents, attorneys,
`
`consultants, accountants, employees, representatives, investigators, distributors, salespersons,
`
`sales representatives, licensors, licensees, and any other persons acting, or purporting to act
`
`for or on its or their behalf or under its or their control, including but not limited to experts or
`
`persons consulted concerning any factual matter or matters of opinion relating to any issues
`
`involved in the action.
`
`14.
`
`“MPS” means Monolithic Power Systems, Inc. and any present or former
`
`parent, subsidiary, division, subdivision, affiliated company, licensee, predecessor, or
`
`successor of Monolithic Power Systems, Inc., and any of its or their present or former officers,
`
`directors, agents, attorneys, consultants, accountants, employees,
`
`representatives,
`
`investigators, distributors, salespersons, sales representatives, licensors, licensees, and any
`
`other persons acting, or purporting to act for or on its or their behalf or under its or their
`
`control, including but not limited to experts or persons consulted concerning any factual
`
`matter or matters of opinion relating to any issues involved in the action.
`
`15.
`
`“Rambus” means Rambus Inc. and any present or former parent, subsidiary,
`
`division, subdivision, affiliated company, licensee, predecessor, or successor of Rambus Inc.,
`
`and any of its or their present or former officers, directors, agents, attorneys, consultants,
`
`accountants, employees, representatives, investigators, distributors, salespersons, sales
`
`representatives, licensors, licensees, and any other persons acting, or purporting to act for or
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`on its or their behalf or under its or their control, including but not limited to experts or persons
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`consulted concerning any factual matter or matters of opinion relating to any issues involved
`
`in the action.
`
`16.
`
`“Renesas” means Renesas Electronics America Inc. and any present or former
`
`parent, subsidiary, division, subdivision, affiliated company, licensee, predecessor, or
`
`successor of Renesas Electronics America Inc., and any of its or their present or former
`
`officers, directors, agents, attorneys, consultants, accountants, employees, representatives,
`
`investigators, distributors, salespersons, sales representatives, licensors, licensees, and any
`
`other persons acting, or purporting to act for or on its or their behalf or under its or their
`
`control, including but not limited to experts or persons consulted concerning any factual
`
`matter or matters of opinion relating to any issues involved in the action.
`
`17.
`
`“TI” means Texas Instruments Incorporated and any present or former parent,
`
`subsidiary, division, subdivision, affiliated company, licensee, predecessor, or successor of
`
`Texas Instruments Incorporated, and any of its or their present or former officers, directors,
`
`agents, attorneys, consultants, accountants, employees, representatives, investigators,
`
`distributors, salespersons, sales representatives, licensors, licensees, and any other persons
`
`acting, or purporting to act for or on its or their behalf or under its or their control, including
`
`but not limited to experts or persons consulted concerning any factual matter or matters of
`
`opinion relating to any issues involved in the action.
`
`18.
`
`“Richtek” means Richtek USA, Inc. and any present or former parent,
`
`subsidiary, division, subdivision, affiliated company, licensee, predecessor, or successor of
`
`Richtek USA, Inc., and any of its or their present or former officers, directors, agents,
`
`attorneys, consultants, accountants, employees, representatives, investigators, distributors,
`
`salespersons, sales representatives, licensors, licensees, and any other persons acting, or
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`purporting to act for or on its or their behalf or under its or their control, including but not
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`limited to experts or persons consulted concerning any factual matter or matters of opinion
`
`relating to any issues involved in the action.
`
`19.
`
`“Anpec” means Anpec Technology Inc., and any present or former parent,
`
`subsidiary, division, subdivision, affiliated company, licensee, predecessor, or successor of
`
`Anpec Technology Inc., and any of its or their present or former officers, directors, agents,
`
`attorneys, consultants, accountants, employees, representatives, investigators, distributors,
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`salespersons, sales representatives, licensors, licensees, and any other persons acting, or
`
`purporting to act for or on its or their behalf or under its or their control, including but not
`
`limited to experts or persons consulted concerning any factual matter or matters of opinion
`
`relating to any issues involved in the action.
`
`20.
`
`“Standard(s)” means any technical standard created, authorized, controlled,
`
`and/or developed privately or unilaterally by a corporation, consortium, regulatory body,
`
`government, or standards setting organization.
`
`21.
`
`“JEDEC” means the JEDEC Solid State Technology Association.
`
`22.
`
`“Person” refers to any natural individual; any form of business entity
`
`including, but not limited to, any corporation, company, firm, general partnership, limited
`
`partnership, limited liability company, joint venture, proprietorship, business association,
`
`association, foundation, and legal entity; any directors, officers, owners, members,
`
`employees, agents, representatives, and attorneys of any of the foregoing; anyone else
`
`purporting to act on behalf of any such natural person or business entity; or any government
`
`entity, agency, officer, department, or affiliate.
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`23.
`
`“Source Code” means programming language statements that can be compiled,
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`transformed, interpreted, executed, or otherwise processed by software (or further compiled,
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`transformed, interpreted, executed, or otherwise processed by software) into object code. This
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`includes, without limitation, instructions, statements, procedures, subroutines, and programs
`
`written in a high-level programming language, design description language, or assembly
`
`language, and Specifications (defined above) for the operation of hardware, including,
`
`without limitation, code written in languages such as VHDL, register-transfer language
`
`(RTL), and verilog, and firmware and technical documentation.
`
`24.
`
`“Prior Art” is used in the same manner in which the term is used in pre-AIA
`
`35 U.S.C. §§ 102 and 103, and includes any patent, printed publication, system, prior
`
`knowledge, prior use, prior sale, offer of sale, or other act or event relevant to patentability
`
`under 35 U.S.C. §§ 102 or 103, or that You otherwise assert renders any asserted claim
`
`invalid.
`
`25.
`
`“Data Buffer” means data buffers for use in Micron Accused DDR4
`
`LRDIMMs.
`
`26.
`
`“RCD” means register clock drivers (“RCD”) for use in Micron Accused
`
`DDR4 LRDIMMs.
`
`27.
`
`“DDR4 LRDIMM Write Buffer Timing Control Features” includes the
`
`following: (1) the tristate buffers in each Data Buffer for a write operation (“Write Tristate
`
`Buffers”); (2) the time period during which Write Tristate Buffers are enabled to drive write
`
`data to one or more associated data lines connecting to one or more associated DRAMs and
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`the time period during which the Write Tristate Buffers are disabled; (3) latency if any used
`
`to determine the time period(s) in (2); (4) signals generated by the RCD in association with
`
`driving write data from a DDR4 LRDIMM data buffer to a DRAM and enablement of Write
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`Tristate Buffers, and associated circuitry; (5) signals received by and generated by the RCD
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`in association with a write operation, and associated circuitry; and (6) the number of bits
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`passing through Write Tristate Buffers during each enablement period to a respective DRAM.
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`28.
`
`“DDR4 LRDIMM Read Buffer Timing Control Features” includes the
`
`following: (1) signals generated by the RCD in association with sampling and transmitting
`
`read data by a data buffer and associated circuitry; (2) amount of read strobe delay by the Data
`
`Buffer in response to one or more signals in (1); (3) mechanisms by which the Data Buffer
`
`determines the amount of delay to be applied to a read strobe, and signals and circuitry
`
`associated therewith; (4) clock signals received or outputted by the Data Buffer and the RCD
`
`and associated circuitry; (5) the width of the read data for each Data Buffer; (6) the tristate
`
`buffers in each Data Buffer for a read operation (“Read Tristate Buffers”) and the time period
`
`during which each Read Tristate Buffer is enabled to drive read data to a memory controller
`
`of a host system and the period during which the Read Tristate Buffer is disabled; and (7)
`
`determination of any latency associated with (6).
`
`29.
`
`“DDR5 Power Management Features” means features related to DDR5
`
`DIMMs’ on-board power management and voltage regulation functionality, including but not
`
`limited to (1) input voltage monitoring and regulation, including in response to over-voltage
`
`and under-voltage detection, (2) output voltage regulation and monitoring, the associated
`
`target output voltage for each voltage regulator (whether linear or switch mode) and the
`
`selective switching on or off of an output power supply; and (3) mechanisms and algorithms
`
`for input voltage regulation, including signals generated, power supply switch and register
`
`value update in response to detection of over-voltage or under-voltage for input voltage.
`
`30.
`
`“HBM Load Reduction Features” means features related to the reduction of
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`capacitive load in high-bandwidth memory products, including but not limited to (1) the
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`arrangement of the TSVs (i.e., any structures allowing for electrical communication between
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`the buffer die and some but not all core dies) and (2) enablement/disablement of TSV drivers
`
`in the buffer die.
`
`31.
`
`“Patented Features” means one or more of DDR4 LRDIMM Write Buffer
`
`Timing Control Features, DDR4 LRDIMM Read Buffer Timing Control Features, DDR5
`
`Power Management Features, and HBM Load Reduction Features.
`
`32.
`
`“Including” and “include” mean including without limitation, whether or not
`
`the phrase “without limitation” is explicitly stated.
`
`33.
`
`The words “and” and “or” are terms of inclusion and not of exclusion and are
`
`to be construed conjunctively or disjunctively as necessary to bring within the scope of these
`
`requests for production any information which might otherwise be construed to be outside
`
`their scope.
`
`34.
`
`The term “any” shall mean “any and all” and the term “all” shall mean “any
`
`and all.”
`
`35.
`
`“Date” means the exact day, month and year if so ascertainable, or if not, the
`
`best approximation (including relationship to seasons and other events).
`
`36.
`
`“Document” means any form of communication or representation, in any
`
`language fixed in any tangible medium, including every form of recording letters, words,
`
`pictures, sounds, or symbols, or combinations thereof by means such as handwriting, printing,
`
`photostatting, photographing, magnetic taping or writing, optically burning or encoding, or
`
`any other form of storing, compiling, or mechanically or electrically recording data onto any
`
`media including paper, film, plastic, magnetic tape, computer disks, compact discs (CDs),
`
`digital video discs (DVDs) and the like. For example, the term “Document” includes without
`
`limitation, correspondence, memoranda, notes, diaries, minutes, statistics, letters, telegrams,
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`contracts, reports, studies, checks, statements, tags, labels, invoices, brochures, periodicals,
`
`receipts, returns, summaries, pamphlets, books, notebooks, lab notebooks, invention
`
`disclosures, prospectuses, interoffice, and intra-office communications, offers, notations of
`
`any sort of conversations, working papers, applications, permits, surveys, indices, telephone
`
`calls, meetings, printouts, teletypes, telefax, telefax records, invoices, work sheets, graphic or
`
`oral representations of any kind (including without limitation, pictures, photographs, charts,
`
`microfiche, microfilm, videotape, audiotape, recordings, motion pictures, plans, drawings,
`
`surveys), and electronic or mechanical records or representations of any kind (including,
`
`without limitation, electronic mail or e-mail, Instant Messages, tapes, cassettes, discs, and
`
`recordings).
`
`37.
`
`Every draft, version, revision, or non-identical copy of a “Document,”
`
`including copies that differ from the original because of hand notation(s), shall be considered
`
`a separate “Document,” as that term is used herein, but exhibits, appendices and attachments
`
`to a “Document” shall be considered part of the “Document” itself.
`
`38.
`
`“Communications” means all written, oral, telephonic, or other inquiries,
`
`dialogues, discussions,
`
`conversations,
`
`interviews,
`
`correspondence,
`
`consultations,
`
`negotiations, agreements, understandings, meetings, letters, notes, advertisements, e-mails
`
`and all other Documents evidencing any transmittal of information or verbal or nonverbal
`
`interaction between persons and entities.
`
`39.
`
`“Thing” means any tangible item, including without limitation, models,
`
`prototypes and samples of any device or apparatus or product.
`
`40.
`
`The terms “relate to,” “reflecting,” “relating to,” “concerning,” or any
`
`variations thereof, shall mean relating to, referring to, concerning, mentioning, reflecting,
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`regarding, pertaining to, evidencing, involving, describing, discussing, commenting on,
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`embodying, responding to, supporting, contradicting, constituting (in whole or in part), or
`
`between (as in the context of Communications), as the context makes appropriate.
`
`41.
`
`The term “Identify” or “Identity” shall mean:
`
`(1)
`
`(2)
`
`(3)
`
`(4)
`
`In connection with natural persons, their full names, titles and job
`description, and their present or last known business address and
`residence (designating which);
`
`In connection with firms, partnerships, corporations, proprietorships,
`associations or other entities, their name, and their present or last
`known addresses of the principal place of business (designating
`which);
`
`In connection with Documents, a description of the Document, setting
`forth its Date, title, format, nature, substance, author or over whose
`name it issued, addressee, and present custodian thereof, with such
`reasonable particularity as would be sufficient to permit the Document
`to be sought by subpoena duces tecum or under the provisions of Rule
`34 of the Federal Rules of Civil Procedure;
`
`In connection with oral statements and Communications: (i) the Date
`and location where they were made; (ii) the identity of each of the
`participants and witnesses thereto, and all others present; (iii) the
`medium of communication; and (iv) their substance.
`
`42.
`
`“Key Technical Information” shall mean each and all of (1) read and write
`
`operations in Micron Accused Products; (2) structure and function of data buffers and RCDs
`
`in Micron Accused DDR4 LRDIMM Products; (3) control and enablement period of the write
`
`and read paths and corresponding tristate buffers in data buffers in Micron Accused DDR4
`
`LRDIMM Products; (4) data sampling and transmissions by data buffers in Micron Accused
`
`DDR4 LRDIMM Products, signals involved therein and how the signals are generated, (5)
`
`information sent during and after training mode; (6) chip selection generation and signaling;
`
`(7) rank multiplication; (8) configuration, interconnections, and electrical communications of
`
`the die interconnects in Micron Accused HBM Products; (9) communication of data, control,
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`and address signals to the control die (e.g., buffer die or logic die) and the DRAM dies in
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`Micron Accused HBM Products; (10) control of the driver sizes in Micron Accused HBM
`
`Products; (11) chip selection mechanisms in Micron Accused HBM Products; (12)
`
`interconnections between TSVs in DRAMs and I/O and power terminals in Micron Accused
`
`HBM Products; and (13) voltage regulation and power management in Micron Accused
`
`DDR5 Products, including identification of structures, components and operations thereof,
`
`type and amplitude of supply voltages to each component in Micron Accused DDR5 Products,
`
`and operation and signaling in Micron Accused DDR5 Products in over-voltage or under-
`
`voltage situations.
`
`TOPIC NO. 1:
`
`TOPICS
`
`The identity of the three (3) most knowledgeable Persons for each category of Key
`
`Technical Information, including their dates of employment, current and previous titles, and
`
`qualification.
`
`TOPIC NO. 2:
`
`Micron’s organizational structure with respect to the Micron Accused Products,
`
`including but not limited to the description of any research centers, groups, subdivisions,
`
`departments, or persons responsible for the design, development, engineering, testing,
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`manufacture, assembly, distribution, sourcing, qualification, and distribution of Micron
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`Accused Products and components thereof (such as data buffers, registering clock drivers,
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`PMICs, and control dies).
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`TOPIC NO. 3:
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`The Identity, location, organizational structure, and responsibilities of each Micron
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`person, group, team, business, or functional unit involved with the sales or marketing of
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`Micron Accused Products.
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`TOPIC NO. 4:
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`Micron’s corporate structure and organization, including any relationship between or
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`among Micron Technology, Inc., Micron Semiconductor Products, Inc., and Micron
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`Technology Texas LLC; Micron Partners, Distributors, and Suppliers (including without
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`limitation to those disclosed in Micron’s Initial Disclosures); any past or present successors,
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`subsidiaries, divisions, parents, or affiliates of the same; and any joint ventures or other legal
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`entities that Micron wholly or partially owns or owned, either directly or indirectly involved
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`in the design, development, manufacture, testing, assembly, importation, distribution, sale, or
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`offer to sell of Micron Accused Products.
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`TOPIC NO. 5:
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`The identification of all Micron Accused Products, including the meaning of Micron’s
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`product codes or part numbers.
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`TOPIC NO. 6:
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`Operations and structures of Micron’s Accused HBM Products, including explanation
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`of documents relating to the operation and structures of Micron’s Accused HBM Products
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`produced in this Action.
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`TOPIC NO. 7:
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`The TSV structure in Micron’s Accused HBM Products, all alternatives that Micron
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`considered, and the advantages and disadvantages for each alternative considered versus the
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`adopted structure.
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`TOPIC NO. 8:
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`The read, write and repair operations in Micron’s Accused HBM products, including
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`signals received from the host, signals generated by the buffer die, signals exchanged between
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`the buffer die and core dies, data/control/address signal paths, and enablement and
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`disablement of data paths in the read, write and repair operations.
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`TOPIC NO. 9:
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`Configuration,
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`interconnections, and electrical communications of
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`the die
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`interconnects in Micron Accused HBM Products.
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`TOPIC NO. 10:
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`Communication of data, control, and address signals between the control die (e.g.,
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`buffer die or logic die) and the DRAM dies in Micron Accused HBM Products.
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`TOPIC NO. 11:
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`Control of the driver sizes in Micron Accused HBM Products.
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`TOPIC NO. 12:
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`Interconnections between TSVs in DRAMs and I/O and power terminals in Micron
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`Accused HBM Products.
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`TOPIC NO. 13:
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`The capacitance and resistance of every electrical path carrying address, data, or
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`control signals between control and buffer dies in each of Micron’s Accused HBM Products,
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`and each arrangement considered during the design process.
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`TOPIC NO. 14:
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`Operations and structures of Micron’s Accused DDR5 Products, including
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`explanation of documents relating to the operation and structures of Micron’s Accused DDR5
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`Products produced in this Action.
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`TOPIC NO. 15:
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`Voltage regulation, operation states, and power management in Micron Accused
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`DDR5 Products.
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`TOPIC NO. 16:
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`The operations and operating states of Micron’s Accused DDR5 DIMMs when the
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`input voltage to a PMIC is at or above an over-voltage threshold or at or below an under-
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`voltage threshold, including the identification of (i) signals generated by PMICs; (ii) signals
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`transferred between PMICs and host or between PMICs and other components on the memory
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`module; (iii) any change in the operating state of other components on the memory module;
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`(iv) any non-volatile memories that are updated; (v) any volatile memories that are updated;
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`(vi) any other changes. If the resulting operations or operating states differ depending on the
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`specific Micron Accused DDR5 DIMM or PMIC used, the separate description of each
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`resulting operation and operating state.
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`TOPIC NO. 17:
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`For each PMIC used in Micron Accused DDR5 DIMMs, the identification of the
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`voltage source (including the identification of the circuit that produces the voltage, the input
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`to that circuit, and the output to the circuit) for (i) each non-PMIC component on the DDR5
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`DIMMs; and (ii) each PMIC functional block; and (iii) to the extent that voltage sources may
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`change depending on the different operating conditions, the identification of any such changes
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`in voltage source(s) (including the identification of the circuit that produces the voltage, the
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`input to that circuit, and the output to the circuit), and the conditions that trigger those changes.
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`TOPIC NO. 18:
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`Operations and structures of Micron’s Accused DDR4 LRDIMM Products, including
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`explanation of documents relating to the operation and structures of Micron’s Accused DDR4
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`LRDIMM Products produced in this Action.
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`TOPIC NO. 19:
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`Presence and/or absence of tristate buffers on data paths in Micron Accused DDR4
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`LRDIMM Products.
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`TOPIC NO. 20:
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`The start time and duration of time periods during which data paths and associated
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`tristate buffers are enabled in Micron Accused DDR4 LRDIMM Products;
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`TOPIC NO. 21:
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`Information sent during and after training mode in Micron Accused DDR4 LRDIMM
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`Products.
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`TOPIC NO. 22:
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`The amount of data strobe delay in data buffers in Micron Accused DDR4 LRDIMM
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`Products for data sampling and how the amount of delay is determined.
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`TOPIC NO. 23:
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`For each DDR4 LRDIMM accused product, any buffer control words that affect the
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`timing of the data for a write operation as it passes through a data buffer, including how the
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`buffer control words affect when the data path for the write path through the data buffer is
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`enabled or disabled, how the buffer control words affect the operation of the write FIFO on
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`the data path, how the buffer control words affect the enablement or disablement of tristate
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`buffers on the data path and the timing of the enablement/disablement, how the buffer control
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`words affect the operation of the transmitters and receivers on the data path, and why the data
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`path for the write data in the data buffer is turned off between write operations.
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`TOPIC NO. 24:
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`All facts and circumstances related to Micron’s use in its DDR4 LRDIMM products
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`of data buffers supporting the training modes described in JEDEC Standard 82-32A, DDR4
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`Data Buffer Definition (DDR4DB02), and any revisions thereof, including but not limited to:
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`how DDR4 LRDIMM performance would be affected if the buffer control words in registers
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`F[3:0]BC4x or F[3:0]BC5x of a data buffer were not correctly set; how frequently MRD
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`training is performed during a DDR4 LRDIMM’s operation; reasons that Micron performs
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`testing to ensure that Micron Suppliers’ data buffers can correctly implement MRD training;
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`whether, and reasons why, Micron uses any data buffers that do not comply with JEDEC
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`Standard 82-32A, DDR4 Data Buffer Definition (DDR4DB02) and/or any revisions.
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`TOPIC NO. 25:
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`The read operations in Micron’s Accused DDR4 LRDIMMs, including but not limited
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`to (i) the signals received and sent by each component on the memory module; (ii) the
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`electrical lines on which the signals are transmitted; (iii) the amount of delay that is applied
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`to MDQS in a read operation; (iv) the buffer control words containing the information on the
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`amount of delay described in (iii); (v) how the data buffer receives the value(s) of the control
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`words of (iv); (vi) the mechanism by which data paths via which read data is transmitted
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`through the data buffer (“