TN-41-13: DDR3 Point-to-Point Design Support
`Introduction
`
`Technical Note
`DDR3 Point-to-Point Design Support
`
`Introduction
`
`Point-to-point design layouts have unique memory requirements, and selecting the
`right memory design methodology can be critical to a project’s success. While DDR3
`SDRAM was targeted for use on modules, it can easily be adapted for point-to-point ap-
`plications.
`
`DDR3 is an evolutionary transition from DDR2. DDR3 point-to-point systems are simi-
`lar to DDR2 point-to-point systems; both require similar design principles. But given
`that DDR3 signaling is more critical, DDR3 point-to-point systems require an emphasis
`on improving the data bus signaling.
`
`Before reviewing this technical note, a basic understanding of DDR2 point-to-point de-
`sign methodologies and DDR3 operation is recommended. Micron's DDR3 data sheet,
`along with the following technical notes, are available for reference on micron.com:
`
`• TN-00-20: Understanding the Value of Signal Integrity Testing
`• TN-41-02: DDR3 ZQ Calibration
`• TN-41-04: Dynamic On-Die Termination
`• TN-46-02: Decoupling Capacitor Calculation for a DDR Memory Channel
`• TN-46-06: Termination for Point-to-Point Systems
`• TN-46-11: DDR SDRAM Point-to-Point Simulation Process
`• TN-46-14: Hardware Tips for Point-to-Point System Design: Termination, Layout, and
`Routing
`• TN-47-19: DDR2 (Point-to-Point) Features and Functionality
`• TN-47-20: DDR2 (Point-to-Pont) Package Sizes and Layout Basics
`
`1
`PDF: 09005aef84b67966
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2013 Micron Technology, Inc. All rights reserved.
`tn-41-13.pdf - Rev. B 08/13 EN
`Products and specifications discussed herein are subject to change by Micron without notice.
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`TN-41-13: DDR3 Point-to-Point Design Support
`DDR2 to DDR3 SDRAM Comparison
`
`DDR2 to DDR3 SDRAM Comparison
`When designing point-to-point memory systems, the major differences between DDR2
`and DDR3 include:
`
`• An increase in bandwidth from 800 MT/s to 1600 MT/s, with optional 1866 MT/s and
`2133 MT/s.
`• An increase in the minimum clock frequency from 125 MHz to 300 MHz.
`• Narrower DDR3 output drive ranges that can be recalibrated to adjust for voltage and
`temperature variations.
`• Adjustable on-die termination (ODT) with dynamic control that provides ODT sup-
`port during writes without having to wire the ODT signal.
`• Small FBGA package sizes that enable high-density devices in extremely compact
`footprints for improved power delivery.
`
`See Table 1 (page 3) for a more detailed comparison.
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
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`2
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`TN-41-13: DDR3 Point-to-Point Design Support
`DDR2 to DDR3 SDRAM Comparison
`
`Table 1: DDR3 Point-to-Point Advantages
`
`Feature/Option
`Voltage (core, I/O)
`Low power (core, I/O)
`VREF input
`Data rate
`tCK DLL enabled
`tCK DLL disabled
`Prefetch
`Burst length (selectable)
`Burst type
`Additive latency (selectable)
`Data bus ODT – nominal
`ODT nominal standby
`ODT nominal writes
`Data bus ODT – dynamic
`ODT dynamic writes
`Data Bus ODT – variation
`Driver impedance (full)
`Driver variation (full)
`Driver impedance (reduced)
`Driver variation (reduced)
`Driver/ODT calibration
`Multipurpose register (MPR)
`
`Write leveling
`Reset
`Automatic self refresh (ASR)
`FBGA package
`
`DDR2
`1.8V
`NA
`1 – all inputs
`800 MT/s
`125–400 MHz
`Undefined
`4 bits (4n)
`BL4, BL8
`Fixed
`0, 1, 2, 3, 4
`Yes
`50Ω, 75Ω, 150Ω
`50Ω, 75Ω, 150Ω
`No
`NA
`±20%
`18Ω (12.9–32.5Ω)
`–37–59%
`40Ω (21.6–81.3Ω)
`–44–111%
`None
`None
`
`None
`None
`None
`60/84-ball
`
`DDR3
`1.5V
`1.35V
`2 – DQs and CMD/ADDR
`1600 MT/s
`300–800 MHz
`12.8–125 MHz
`8 bits (8n)
`BC4, BL8
`Fixed, on-the-fly (OTF)
`1, CL - 1, CL - 2
`Yes
`20Ω, 30Ω, 40Ω, 60Ω, 120Ω
`40Ω, 60Ω, 120Ω
`Yes
`60Ω, 120Ω
`±10%
`34Ω (30.5–38.1Ω)
`±10%
`40Ω (36–44Ω)
`±10%
`Via external R
`Outputs
`predefined pattern
`DQS captures clock
`Dedicated input
`Optional
`78/96-ball
`
`DDR3 Advantage
`Lower power
`Lower power
`Improved power delivery
`2X data rate
`2X clock rate
`Slow clock debug
`–
`–
`–
`–
`–
`–
`Improved signaling
`ODT without ODT pin control
`Improved signaling
`–
`Improved signaling
`Improved signaling
`Improved signaling
`Improved signaling
`Improved signaling
`–
`
`De-skews if fly-by used
`–
`Self refresh if TC > 85ºC
`Improved power busing
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`3
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`DDR3 Overview
`
`TN-41-13: DDR3 Point-to-Point Design Support
`DDR2 to DDR3 SDRAM Comparison
`
`DDR3 functions much like DDR2 in that a source-synchronous data strobe is used, and
`data is transferred on both the leading and trailing strobe edges. However, DDR3 has an
`8n-prefetch architecture where the internal data cycle time is one-eighth the external
`data rate, and the internal data bus width is eight times the size of the external data bus
`width.
`
`For example, a x16 DDR3 SDRAM device has a 128-bit-wide internal data bus, so for
`each single access to or from the internal array, eight data transfers of 16 bits each will
`be provided externally. Because of the 8n prefetch, burst lengths are limited (BL = 8). In
`addition to 8n prefetch, both the DDR3 core and the I/O operate from a 1.5V power
`source (DDR3L is 1.35V). With the advanced process technology, lower operating volt-
`age, and input voltage swings, DDR3 and DDR3L provide significant reduction in over-
`all power consumption.
`
`DDR3L (1.35V) will work well in point-to-point designs alongside DDR3 (1.5V). While
`DDR3L has the same timings as DDR3, DDR3L does not have as much voltage margin.
`However, the reduced voltage margin is not typically an issue with a well-terminated
`point-to-point system.
`
`Memory Architecture
`SDRAM, DDR, and DDR2 memory system architectures assume a symmetrical tree lay-
`out coupled with minimal clock skews between command/address/control buses and
`the data bus. DDR3 memory system architectures assume a daisy-chain, or fly-by, lay-
`out. When developing systems that support JEDEC DDR3 modules, fly-by architecture
`must be supported.
`
`DDR3 point-to-point designs, on the other hand, do not have to be implemented using
`a fly-by architecture. A DDR3 point-to-point design can employ either the DDR2 tree ar-
`chitecture (minimal timing skew concerns; command/address/control buses that likely
`do not require termination) or the DDR3 fly-by architecture (significant timing skew be-
`tween clock and data buses; command/address/control buses that require termina-
`tion).
`
`Write leveling was added to DDR3 to remove the skew (induced by the fly-by architec-
`ture) between the command/address/control/clocks buses and each of the DRAM data
`buses, as shown in Figure 1 (page 5). Even if fly-by architecture is used in a point-to-
`point system, it is generally better to hard code the skews rather than use the write-lev-
`eling feature.
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`4
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`TN-41-13: DDR3 Point-to-Point Design Support
`DDR2 to DDR3 SDRAM Comparison
`
`Figure 1: DDR2 Tree vs. DDR3 Fly-By Architecture
`
`
`
`Command/Address/
`Control/Clocks
`
`DDR2
`
`DDR3
`
`DQS
`
`Data valid
`
`Command/Address/
`Control/Clocks
`
`DQS
`
`DQS
`
`DQS
`
`DQS
`
`DQS
`
`DQS
`
`DQS
`
`DQS
`
`On-Die Termination (ODT)
`Like DDR2 ODT, DDR3 ODT reduces layout constraints by eliminating the need for dis-
`crete termination to VTT and the need for VTT generation for the data bus. ODT im-
`provement is one of the more significant additions to DDR3. ODT has been improved in
`the following ways:
`
`• Value reduction – Closer impedance matching for point-to-point systems, providing
`improved signal quality
`• Calibration control – Neutralizing voltage and temperature shifts, providing improved
`signal quality
`• Tighter ranges – Less variation, providing tighter control and improved signal quality
`• Dynamic ODT – Desired termination opportunistically applied during writes
`
`A summary of the DDR3 ODT resistors is shown in the ODT Settings for MR1 and MR2
`tables (Table 2 (page 6) and Table 3 (page 6)). For most point-to-point designs,
`RTT_NOM for non-write cases are not applicable and are not used. These settings are in-
`tended to be used in dual-rank systems coupled with dynamic ODT use. In most cases,
`only RTT_NOM for writes or RTT_WR (that is, dynamic ODT) are used in point-to-point de-
`signs.
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`5
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`TN-41-13: DDR3 Point-to-Point Design Support
`DDR2 to DDR3 SDRAM Comparison
`
`Table 2: ODT Settings – MR1
`
`M9 M6 M2
`0 0 0
`0 0 1
`0 1 0
`0 1 1
`1 0 0
`1 0 1
`1 1 0
`1 1 1
`
`RTT_NOM (ODT) Non-Writes RTT_NOM (ODT) Writes
`RTT_NOM disabled
`RTT_NOM disabled
`RZQ/4 (60Ω [NOM])
`RZQ/4 (60Ω [NOM])
`RZQ/2 (120Ω [NOM])
`RZQ/2 (120Ω [NOM])
`RZQ/6 (40Ω [NOM])
`RZQ/6 (40Ω [NOM])
`RZQ/12 (20Ω [NOM])
`NA
`RZQ/8 (30Ω [NOM])
`NA
`Reserved
`Reserved
`Reserved
`Reserved
`
`Table 3: ODT Settings – MR2
`
`M10 M9
`0 0
`0 1
`1 0
`1 1
`
`RTT_WR (ODT) Dynamic ODT
`RTT_WR disabled
`RZQ/4 (60Ω)
`RZQ/2 (120Ω)
`Reserved
`
`DDR3's smaller signal swing coupled with reduced loading requirements allows for
`drivers with reduced current drive (that is, higher impedance drivers). The output driv-
`ers are the building blocks of ODT resistors. Thus, the ODT resistors can be derived at
`values that support point-to-point architectures well. The closer that the impedances
`match the transmission line, the better the signal quality.
`
`DDR2 does not offer driver/resistor calibration; thus, the ODT resistors change with a
`voltage and/or temperature change. Also, parts from the manufacturer require a wider
`range of specification limits because of manufacturing distributions. DDR3 adds the
`ability to perform calibration when needed. Upon initialization, the drivers are calibra-
`ted to a known value to support tight tolerances. Calibration may also be performed at
`other times, as needed, to neutralize the effects of voltage and temperature shifts. Keep-
`ing tight driver and ODT resistor impedance tolerances helps improve signal quality.
`
`Reducing Values
`
`Calibration Control
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`6
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`Tighter Ranges
`
`Dynamic ODT
`
`TN-41-13: DDR3 Point-to-Point Design Support
`DDR2 to DDR3 SDRAM Comparison
`
`As shown in the table below, the allowed DDR2 ODT variation is twice that of the DDR3
`ODT (referenced at midpoint). The closer that the impedances match the transmission
`line, the better the signal quality.
`
`Table 4: ODT Variation
`
`Feature/Option
`Data bus ODT – varia-
`tion
`Driver/ODT calibration
`
`DDR2
`±20%
`
`DDR3
`±10%
`
`DDR3 Point-to-Point Ad-
`vantage
`Improved signaling
`
`None
`
`Via external R
`
`Improved signaling
`
`The intent of dynamic ODT is to allow the desired ODT value (larger R) to be opportun-
`istically applied during writes, while also allowing a different ODT value (smaller R) to
`be applied to the same memory when in standby and when a different rank is being
`written to in multirank systems. This requires the DRAM device to have its RTT_NOM bits
`set in mode register 1 (MR1) and the RTT_WR bits set in mode register 2 (MR2). After the
`MR1 and MR2 ODT bits are set or enabled, toggling the ODT pin on and off is required
`in order to have a different RTT value when the DRAM is in standby versus during writes.
`RTT_NOM for non-write cases is not applicable and would not be used in a point-to-point
`system. This setting is intended for use in dual-rank systems coupled with dynamic
`ODT.
`
`Either RTT_NOM for writes or RTT_WR (that is, dynamic ODT) may be used for termination
`of the data bus during writes in point-to-point systems. Using RTT_NOM requires the
`ODT pin to toggle and turn on and off RTT termination during writes. Using RTT_WR al-
`lows the ODT pin to be tied active (no routing of signal), and the RTT termination to be
`automatically applied during writes as needed. Thus, dynamic ODT offers a clear bene-
`fit for point-to-point systems: no routing of ODT, yet automatic ODT control on the
`DRAM device.
`
`Output Drive Levels
`In point-to-point designs, the memory’s position is typically quite close to the control-
`ler, which results in short data bus trace lengths. This makes a driver with a low-impe-
`dance output undesirable. DDR2 all but requires the DDR2 reduced drive mode to be
`used since the DDR2 full-drive output buffer impedance was fairly low (that is, 18Ω).
`Unfortunately, the DDR2 reduced output driver has a wide range that is rather difficult
`to design to. DDR3, on the other hand, provides two higher-impedance drives with tight
`tolerances that make them well-suited to support point-to-point designs, as shown in
`the table below.
`
`Table 5: DDR3 Point-to-Point Advantages
`
`Feature/Option
`Driver impedance (full)
`Driver variation (full)
`
`DDR2
`18Ω (12.9–32.5Ω)
`–37–59%
`
`DDR3
`34Ω (30.5–38.1Ω)
`± 10%
`
`DDR3 Advantage
`Improved signaling
`Improved signaling
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`7
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`TN-41-13: DDR3 Point-to-Point Design Support
`DDR3 Layout and Design Considerations
`
`Table 5: DDR3 Point-to-Point Advantages (Continued)
`
`Feature/Option
`Driver impedance (reduced)
`Driver variation (reduced)
`Driver/ODT calibration
`
`DDR2
`40Ω (21.6–81.3Ω)
`–44–111%
`None
`
`DDR3
`40Ω (36–44Ω)
`± 10%
`Via external R
`
`DDR3 Advantage
`Improved signaling
`Improved signaling
`Improved signaling
`
`The figure below compares DDR2 and DDR3 full and reduced drive. The DDR3 values
`are both good options for point-to-point designs since they have a higher impedance
`and are more linear than DDR2 levels.
`
`IOUT (mA)
`
`
`
`VDD – VOUT
`
`DDR3 full drive
`
`DDR3 reduced drive
`
`DDR2 full drive
`
`DDR2 reduced drive
`
`Pull-up characteristics (nominal)
`
`Figure 2: Comparison of Full and Reduced Drive I/O
`
`0
`
`–10mA
`
`–20mA
`
` –30mA
`
`–40mA
`
`–50mA
`
`–60mA
`
`IOUT (mA)
`
`DDR3 full drive
`
`DDR3 reduced drive
`
`VOUT
`
`Pull-down characteristics (nominal)
`
`DDR2 full drive
`
`DDR2 reduced drive
`
`
`
`70mA
`
`60mA
`
`50mA
`
`40mA
`
`30mA
`
`20mA
`
`10mA
`
`0
`
`0V
`
`0.5V
`
`1V
`
`1.5V
`
`2V
`
`–70mA
`
`0V
`
`0.5V
`
`1V
`
`1.5V
`
`2V
`
`DDR3 Layout and Design Considerations
`Layout is one of the key elements of a successfully designed application. The following
`sections provide guidance on the most important factors of layout so that if trade-offs
`need to be considered, they may be implemented appropriately.
`
`Decoupling
`
`Micron DRAM has on-die capacitance for the core as well as the I/O. There is not a total
`reliance on external capacitance. It is not necessary to allocate a capacitor for every pin
`pair (VDD:VSS, VDDQ:VSSQ).
`Decoupling prevents the voltage supply from dropping when the DRAM core requires
`current, as with a refresh, read, or write. It also provides current during reads for the
`output drivers. The core requirements tend to be lower frequency. The output drivers
`tend to have higher frequency demands. This means that the DRAM core requires the
`decoupling to have larger values, and the output drivers want low inductance in the de-
`coupling path but not a significant amount of capacitance.
`
`One recommendation is to place enough capacitance around the DRAM device to sup-
`ply the core and to place capacitance near the output drivers for the I/O. This is accom-
`plished by placing four capacitors around the device on each side of the package. Place
`one of the capacitors centered in the upper quarter of the ball grid and one in the lower
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
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`TN-41-13: DDR3 Point-to-Point Design Support
`DDR3 Layout and Design Considerations
`
`quarter of the ball grid (see Decoupling Placement Recommendations Figure 3
`(page 9)). Place these capacitors as close to the device as practical with the vias loca-
`ted to the device side of the capacitor. For these applications, the capacitors placed on
`both sides of the card in the I/O area may be optimized for specific purposes. The larger
`value primarily supports the DRAM core, and a smaller value with lower inductance pri-
`marily supports I/O. The smaller value should be sized to provide maximum benefit
`near the maximum data frequency.
`
`Decide between two values—0.1µF and 1.0µF—for the core. Intermediate values tend to
`cost the same as 1.0µF capacitors, which is based on demand and may change over
`time. Consider 0.1µF for designs that have significant capacitance away from the DRAM
`and a power supply on the same PCB. For designs that are complex or have an isolated
`power supply (for example, on another board), use 1.0µF. For the I/O, where inductance
`is the basic concern, having a short path with sufficient vias is the main requirement.
`
`Figure 3: Decoupling Placement Recommendations
`
`Power Vias and Sharing
`A DRAM device has four supply pin types: VDD and VSS power the core, and VDDQ and
`VSSQ are present only for the output drivers. However, there are exceptions. The sub-
`strate for the device typically maintains isolation from the package balls all the way to
`the die where isolation is also maintained. This isolation is intended to keep I/O noise
`off of the core supply and core noise off of the I/O drivers. It is good practice, but not an
`absolute requirement, to use separate vias for VSS and VSSQ as well as for VDD and VDDQ.
`There is a compromise position. Where a via connects to a V SS ball on one side of the
`card and a VSSQ ball on the other side of the card, the actual path being shared is mini-
`mized.
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
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`Return Path
`
`TN-41-13: DDR3 Point-to-Point Design Support
`DDR3 Layout and Design Considerations
`
`The path from the planes to the DRAM balls is important. Providing good, low induc-
`tance paths provides the best margin. Therefore, separate vias where possible and pro-
`vide as wide of a trace from the via to the DRAM ball as the design permits.
`
`Where there is concern and sufficient room, multiple vias are a possibility. This is gener-
`ally applied at the decoupling cap to make a low impedance connection to the planes.
`
`If anything is overlooked, it will be the current return path. This is most important for
`terminated signals (parallel termination) since the current flowing through the termina-
`tion and back to the source involves higher currents. No board-level (2D) simulators
`take this into account. They assume perfect return paths. Most simulators interpret that
`an adjacent layer described as a plane is the perfect return path whether it is related to
`the signal or not. Some board simulators take into account plane boundaries and gaps
`in the plane to a degree. A 3D simulator is required to take into account the correct re-
`turn path. These are generally not appropriate for most applications.
`
`Most of the issues with the return path are discovered with visual inspection. The cur-
`rent return path is the path of least resistance. This may vary with frequency, so resist-
`ance alone may be a good indicator.
`
`Trace Length Matching
`Prior to designing the card, it is useful to decide how much of the timing budget to allo-
`cate to routing mismatch. This can be determined by thinking in terms of time or as a
`percentage of the clock period. For example, 1% (±0.5%) at 800 MHz clock is 6.25ps
`(1250ps/200). Typical flight times for FR4 PCB are near 6.5 ps/mm. So matching to
`±1mm (±0.040 inch) allocates 1% of the clock period to route matching. Selecting 1mm
`is completely arbitrary. If the design is not likely to push the design limits, a larger num-
`ber can be allocated.
`
`When the design has unknowns, it is important to select a tighter matching approach.
`Using this approach is not difficult and allows as much margin as is conveniently availa-
`ble to allocate to the unknowns.
`
`Address
`
`Data Bus
`
`For the address, the design will likely use a tree topology with branching. Making the
`branches uneven causes some signal integrity issues. For this reason, make all related
`branches match to within 1mm within each net. Different nets may have different
`branch lengths as long as they are matched within a branch. This is somewhat arbitrary,
`but there are many cases to consider, and 1mm should be adequate for all cases. There
`may be some exceptions.
`
`For DQ, the topology is point-to-point or point-to-two-points where the two points are
`close together. For the data bus, the bit rate is the period on interest. That is 625ps for
`an 800 MHz clock. Because 1% of this interval is 6.25ps, if the matching is held to a
`range of 1% (±0.5%), then ±0.5mm is the limit. Again, this is arbitrary.
`
`Other factors to account for are vias, differences in propagation time for routing on in-
`ner layers versus outer layers, and load differences.
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
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`Propagation Delay
`
`Vias
`
`Timing Budgets
`
`TN-41-13: DDR3 Point-to-Point Design Support
`DDR3 Layout and Design Considerations
`
`Propagation delay for inner layers and outer layers is different because the effective die-
`lectric constant is different. The dielectric constant for the inner layer is defined by the
`glass and resin of the PCB. Outer layers have a mix of materials with different dielectric
`constants. Generally the materials are the glass and resin of the PCB, the solder mask
`that is on the surface, and the air that is above the solder mask. This defines the effec-
`tive dielectric for the outer layers and usually amounts to a 10% decrease in propaga-
`tion delay for traces on the outer layers. For the design of JEDEC UDIMMs, a 10% differ-
`ence accounts for the differences in propagation of the inner layers versus the outer lay-
`ers. If all traces that need to match are routed with the same percentage on the outer
`layers versus the inner layers, this difference may be ignored for the purpose of match-
`ing timing. Otherwise, this difference should be accounted for in any delay or matching
`calculations.
`
`For inner layer propagation, velocity is about 6.5 ps/mm. To match all traces within
`10ps, traces must be held within a range of 1.5mm, 60 mils. In most cases, this can be
`easily achieved. Most designs tolerate a much greater variation and still have significant
`margin. The engineer must decide how much of the timing budget is allocated to trace
`matching.
`
`In most cases, the number of vias in matched lines should be the same. If this is not the
`case, the degree of mismatch should be held to a minimum. Vias represent additional
`length in the Z direction. The actual length of a via depends on the starting and ending
`layers of the current flow. Because all vias are not the same, one value of delay for all
`vias is not possible. Inductance and capacitance cause additional delay beyond the de-
`lay associated with the length of the via. The inductance and capacitance vary depend-
`ing on the starting and ending layers. This is either complex or labor-intensive and is
`the reason for trying to match the number of vias across all matched lines. Vias can be
`ignored if they are all the same. A maximum value for delay through a via to consider is
`20ps. This number includes a delay based on the Z axis and time allocated to the LC de-
`lay. Use a more refined number if available; this generally requires a 3D solver.
`
`The table below lists parameters typically included in an address bus timing budget.
`The address A[15:0], bank address B[2:0], command (RAS#, CAS#, WE#), and control
`(CS#, ODT, CKE) signals are referred to as the CA bus. Separate tables for each group are
`acceptable. Simulation provides an eye. The simulation should include the clock and
`the CA bus, which allows a direct measurement of the setup and hold time for the simu-
`lation case. For most simulations, assume that the clock and CA bus are aligned at the
`source. If this is not the case, address the offset separately.
`
`Table 6: Address Timing Budget Example
`
`Ref Parameter
`A Open address window from simulations
`B DRAM setup and hold requirements from the data sheet
`C
`Slew rate (V/ns)
`
`Setup
`476ps
`45ps
`2.3ps
`
`Hold
`651ps
`120ps
`2.8ps
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`11
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2013 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2028
`Samsung v Netlist
`IPR2022-00996
`
`

`

`TN-41-13: DDR3 Point-to-Point Design Support
`DDR3 Layout and Design Considerations
`
`Table 6: Address Timing Budget Example (Continued)
`
`E
`
`Ref Parameter
`D Timing offset with respect to VREFCA (simulations placed VREF
`ideally) (this applies to setup)
`Timing offset with respect to VREFCA (simulations placed VREF
`ideally) (this applies to hold)
`F DRAM derating
`G Crosstalk
`H Controller error (includes skew and all other errors attributed
`to the controller)
`Clock error (this can be jitter [from all sources including cross-
`talk] or placement error if not included elsewhere)
`Routing error
`J
`K Margin
`
`I
`
`Setup
`13ps
`
`–
`
`88ps
`47ps
`200ps
`
`30ps
`
`10ps
`41ps
`
`Hold
`–
`
`11ps
`
`50ps
`42ps
`200ps
`
`30ps
`
`10ps
`185ps
`
`Notes:
`1. Open address window (A) comes directly from simulations. For setup, the slow
`corner is simulated. This is typically at V DD (MIN) and high temperature with slow
`silicon. These cases are in the spice and IBIS models. The fast corner, which is V DD
`(MAX) and minimum temperature with fast silicon, applies to the hold case. It is
`generally not acceptable to only run the typical case. For DDR3, different thresh-
`olds are used for different speeds and voltages. Attention must be paid to using the
`correct thresholds when extracting the setup and hold margins from the simula-
`tions.
`2. DRAM setup and hold values (B) come directly from the DRAM data sheet. Be sure
`to use the correct speed and voltage numbers.
`3. Slew rate (C) is not used directly but is used to calculate derating values. See the
`DRAM data sheet for the slew rate definitions.
`4. Timing offset with respect to VREFCA (D and E) is to address the fact that the simu-
`lations use a single value for the threshold. VREFCA has a tolerance of 1%, 0.49 x VDD
`to 0.51 x VDD. In addition, any noise that is on VREFCA is added to this parameter.
`Micron uses 30mV as a typical error for VREFCA. This includes both AC and DC con-
`tributors. To get to a value for the table, multiply the slew rate for the setup wave-
`form by 30mV. The resulting value is added to the table.
`5. DRAM derating (F) uses the slew rate to adjust the actual setup and hold time re-
`quired by the device. See the DRAM data sheet for the derating procedure.
`6. Crosstalk (G) can be handled several ways. If the simulation is performed with
`coupling turned on, it is included in the setup and hold values from the simulation
`waveform (A). Another method is to run a separate simulation on fewer signals,
`and then determine which is likely the worst-case signal. This can be done by sim-
`ulation or visual inspection using the result in the timing budget.
`7. Controller error (H) can generally be found in the data sheet for the controller.
`8. Clock error (I) assumes that this is a separate parameter from skew attributed to
`the controller. If included in the controller, it can be ignored.
`9. Routing error (J) assumes that only one trace was simulated. Add any differences
`in routing length between the simulated trace and the fastest and slowest traces
`here. Usually, either all traces are simulated, or just the fastest and slowest traces
`are simulated, resulting in a value of zero.
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`12
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2013 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2028
`Samsung v Netlist
`IPR2022-00996
`
`

`

`TN-41-13: DDR3 Point-to-Point Design Support
`DDR3 Layout and Design Considerations
`
`10. Margin (K) is simply the open address window (A) parameter minus all other pa-
`rameters. If the result is positive, there is margin. If there is a large difference be-
`tween the setup and hold margin, it may be appropriate to skew the clock to get a
`more even margin.
`
`There is nothing in this budget to allocate toward VDD noise. Since the DRAM specifica-
`tion includes noise in the test fixture, some noise is included. Because the environment
`for the test fixture and the application are different, additional VDD noise is not accoun-
`ted for. If the other guidelines in this document are followed, this should be small
`enough to ignore.
`
`Write Leveling and Training
`Write leveling is a new feature for DDR3, intended for applications that use the daisy-
`chain topology for the clock. For an application where memory is only placed on the
`main board, write leveling is only useful if four or more DRAM devices are placed on the
`same side of the PCB using a daisy-chain topology for the clock.
`
`With the daisy-chain topology and four devices, the clock at each device is offset 150ps
`to 200ps from the adjacent devices. The first device has a clock offset 450ps to 600ps
`from the clock at the last device. The major implication is that the DQ bus needs to be
`skewed per byte lane (per 16 bits for x16 devices) to meet tDQSCK for writes. The control-
`ler must provide the skew.
`
`The following three options are available to address this skew requirement:
`1. Use a series of reads and writes to fine-tune the skew (preferred).
`2. Predict or measure the skew one time, and apply it universally to the design.
`3. Use the write leveling feature to determine the skew for each PCB.
`
`Write leveling does not provide a very tight definition of the clock skew. The setup and
`hold requirements provide a good indication of the uncertainty, which varies with the
`maximum speed of the DRAM device.
`
`Drive Strength and Calibration
`DDR3 has two drive strengths: 40Ω and 34Ω. DRAM devices from some manufacturers
`may support 48Ω. DDR3 is designed to match the driver to the transmission line. With a
`40Ω driver, the intended transmission line is 40Ω. The advantage of matching the driver
`to the transmission line is that it eliminates the reflections that return to the driver. The
`result is cleaner edges and a more open eye.
`To achieve a driver near 40Ω, calibration is necessary. To maintain tight calibration, re-
`calibrate periodically. There are commands to initiate calibration. For smaller systems
`where tight tolerance is not necessary, the initial calibration may be all that is required.
`However, this allows the driver impedance to vary with voltage and temperature.
`
`See Micron's technical note, TN-41-02: DDR3 ZQ Calibration, for a better understand-
`ing of calibration.
`
`See the Terminating Point-to-Point Systems section to learn the effects of mismatching
`a driver to the transmission line.
`
`PDF: 09005aef84b67966
`tn-41-13.pdf - Rev. B 08/13 EN
`
`13
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2013 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2028
`Samsung v Netlist
`IPR2022-00996
`
`

`

`TN-41-13: DDR3 Point-to-Point Design Support
`Terminating Point-to-Point Systems
`
`ODT Values/Calibration
`The termination resistances 120Ω, 60Ω, 40Ω, 30Ω, and 20Ω are calibrated at the same
`time as the output drivers. DDR3 has different termination resistances that provide a
`better match compared to DDR2. Because these values are also adjusted through ZQ
`calibration, it is important to perform periodic calibration to keep the ODT termination
`resistances within the data sheet values