64Mb: x4, x8, x16 SDRAM
`Features
`
`SDR SDRAM
`MT48LC16M4A2 – 4 Meg x 4 x 4 Banks
`MT48LC8M8A2 – 2 Meg x 8 x 4 Banks
`MT48LC4M16A2 – 1 Meg x 16 x 4 Banks
`
`Features
`• PC100- and PC133-compliant
`• Fully synchronous; all signals registered on positive
`edge of system clock
`• Internal, pipelined operation; column address can
`be changed every clock cycle
`• Internal banks for hiding row access/precharge
`• Programmable burst lengths: 1, 2, 4, 8, or full-page
`• Auto precharge, includes concurrent auto precharge
`and auto refresh modes
`• Self refresh modes: standard and low-power
`(not available on AT devices)
`• Auto refresh
`– 64ms, 4096-cycle refresh
`(commercial and industrial)
`– 16ms, 4096-cycle refresh
`(automotive)
`• LVTTL-compatible inputs and outputs
`• Single 3.3V ±0.3V power supply
`
`Options
`• Configuration
`– 16 Meg x 4 (4 Meg x 4 x 4 banks)
`– 8 Meg x 8 (2 Meg x 8 x 4 banks)
`– 4 Meg x 16 (1 Meg x 16 x 4 banks)
`• Write recovery (tWR)
`– tWR = 2 CLK
`• Plastic package – OCPL1
`– 54-pin TSOP II (400 mil)
`– 54-pin TSOP II (400 mil) Pb-free
`– 54-ball VFBGA (x16 only) (8mm x
`8mm)
`– 54-ball VFBGA (x16 only) (8mm x
`8mm)
`• Timing – cycle time
`– 6ns @ CL = 3
`– 6ns @ CL = 3
`– 7.5ns @ CL = 3 (PC133)
`– 7.5ns @ CL = 2 (PC133)
`• Self refresh
`– Standard
`– Low-power
`• Operating temperature range
`– Commercial (0˚C to +70˚C)
`– Industrial (–40˚C to +85˚C)
`– Automotive (–40˚C to +105˚C)
`• Revision
`
`Marking
`
`16M43
`8M8
`4M16
`
`A2
`
`TG
`P
`F4
`
`B42
`
`-63
`-6A
`-753
`-7E
`
`None
`L3
`
`None
`IT
`AT2
`:G, :J
`
`Notes:
`
`1. Off-center parting line.
`2. Contact Micron for availability.
`3. Available only on Revision G.
`
`Table 1: Key Timing Parameters
`
`CL = CAS (READ) latency
`
`Speed Grade
`-6
`-6A
`-75
`-7E
`
`Clock
`Frequency (MHz)
`167
`167
`133
`133
`
`Target tRCD-tRP-CL
`3-3-3
`3-3-3
`3-3-3
`2-2-2
`
`tRCD (ns)
`18
`18
`20
`15
`
`tRP (ns)
`18
`18
`20
`15
`
`CL (ns)
`18
`18
`20
`15
`
`1
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`PDF: 09005aef80725c0b
`© 1999 Micron Technology, Inc. All rights reserved.
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`Products and specifications discussed herein are subject to change by Micron without notice.
`
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`

`

`64Mb: x4, x8, x16 SDRAM
`Features
`
`Table 2: Address Table
`
`Parameter
`Configuration
`Refresh count
`Row addressing
`Bank addressing
`Column addressing
`
`16 Meg x 4
`4 Meg x 4 x 4 banks
`4K
`4K A[11:0]
`4 BA[1:0]
`1K A[9:0]
`
`8 Meg x 8
`2 Meg x 8 x 4 banks
`4K
`4K A[11:0]
`4 BA[1:0]
`512 A[8:0]
`
`4 Meg x 16
`1 Meg x 16 x 4 banks
`4K
`4K A[11:0]
`4 BA[1:0]
`256 A[7:0]
`
`Table 3: 64Mb SDR Part Numbering
`
`Part Numbers
`MT48LC16M4A2TG
`MT48LC16M4A2P
`MT48LC8M8A2TG
`MT48LC8M8A2P
`MT48LC4M16A2TG
`MT48LC4M16A2P
`MT48LC4M16A2B41
`MT48LC4M16A2F41
`
`Architecture
`16 Meg x 4
`16 Meg x 4
`8 Meg x 8
`8 Meg x 8
`4 Meg x 16
`4 Meg x 16
`4 Meg x 16
`4 Meg x 16
`
`Package
`54-pin TSOP II
`54-pin TSOP II
`54-pin TSOP II
`54-pin TSOP II
`54-pin TSOP II
`54-pin TSOP II
`54-ball VFBGA
`54-ball VFBGA
`
`Note:
`
`1. FBGA Device Decoder: www.micron.com/decoder.
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`2
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
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`
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`
`

`

`64Mb: x4, x8, x16 SDRAM
`Features
`
`Contents
`Important Notes and Warnings ......................................................................................................................... 7
`General Description ......................................................................................................................................... 7
`Automotive Temperature .............................................................................................................................. 8
`Functional Block Diagrams ............................................................................................................................... 9
`Pin and Ball Assignments and Descriptions ..................................................................................................... 12
`Package Dimensions ....................................................................................................................................... 15
`Temperature and Thermal Impedance ............................................................................................................ 17
`Electrical Specifications .................................................................................................................................. 20
`Electrical Specifications – IDD Parameters ........................................................................................................ 22
`Electrical Specifications – AC Operating Conditions ......................................................................................... 24
`Functional Description ................................................................................................................................... 28
`Commands .................................................................................................................................................... 29
`COMMAND INHIBIT .................................................................................................................................. 29
`NO OPERATION (NOP) ............................................................................................................................... 30
`LOAD MODE REGISTER (LMR) ................................................................................................................... 30
`ACTIVE ...................................................................................................................................................... 30
`READ ......................................................................................................................................................... 31
`WRITE ....................................................................................................................................................... 32
`PRECHARGE .............................................................................................................................................. 33
`BURST TERMINATE ................................................................................................................................... 33
`REFRESH ................................................................................................................................................... 34
`AUTO REFRESH ..................................................................................................................................... 34
`SELF REFRESH ....................................................................................................................................... 34
`Truth Tables ................................................................................................................................................... 35
`Initialization .................................................................................................................................................. 40
`Mode Register ................................................................................................................................................ 42
`Burst Length .............................................................................................................................................. 44
`Burst Type .................................................................................................................................................. 44
`CAS Latency ............................................................................................................................................... 46
`Operating Mode ......................................................................................................................................... 46
`Write Burst Mode ....................................................................................................................................... 46
`Bank/Row Activation ...................................................................................................................................... 47
`READ Operation ............................................................................................................................................. 48
`WRITE Operation ........................................................................................................................................... 57
`Burst Read/Single Write .............................................................................................................................. 64
`PRECHARGE Operation .................................................................................................................................. 65
`Auto Precharge ........................................................................................................................................... 65
`AUTO REFRESH Operation ............................................................................................................................. 77
`SELF REFRESH Operation ............................................................................................................................... 79
`Power-Down .................................................................................................................................................. 81
`Clock Suspend ............................................................................................................................................... 82
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`3
`
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`

`64Mb: x4, x8, x16 SDRAM
`Features
`
`List of Figures
`Figure 1: 16 Meg x 4 Functional Block Diagram ................................................................................................. 9
`Figure 2: 8 Meg x 8 Functional Block Diagram ................................................................................................. 10
`Figure 3: 4 Meg x 16 Functional Block Diagram ............................................................................................... 11
`Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 12
`Figure 5: 54-Ball VFBGA x16 (Top View) ......................................................................................................... 13
`Figure 6: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 15
`Figure 7: 54-Ball VFBGA (8mm x 8mm) – Package Codes F4/B4 ....................................................................... 16
`Figure 8: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 18
`Figure 9: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) .............................................. 19
`Figure 10: ACTIVE Command ........................................................................................................................ 30
`Figure 11: READ Command ........................................................................................................................... 31
`Figure 12: WRITE Command ......................................................................................................................... 32
`Figure 13: PRECHARGE Command ................................................................................................................ 33
`Figure 14: Initialize and Load Mode Register .................................................................................................. 41
`Figure 15: Mode Register Definition ............................................................................................................... 43
`Figure 16: CAS Latency .................................................................................................................................. 46
`Figure 17: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 47
`Figure 18: Consecutive READ Bursts .............................................................................................................. 49
`Figure 19: Random READ Accesses ................................................................................................................ 50
`Figure 20: READ-to-WRITE ............................................................................................................................ 51
`Figure 21: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 52
`Figure 22: READ-to-PRECHARGE .................................................................................................................. 52
`Figure 23: Terminating a READ Burst ............................................................................................................. 53
`Figure 24: Alternating Bank Read Accesses ..................................................................................................... 54
`Figure 25: READ Continuous Page Burst ......................................................................................................... 55
`Figure 26: READ – DQM Operation ................................................................................................................ 56
`Figure 27: WRITE Burst ................................................................................................................................. 57
`Figure 28: WRITE-to-WRITE .......................................................................................................................... 58
`Figure 29: Random WRITE Cycles .................................................................................................................. 59
`Figure 30: WRITE-to-READ ............................................................................................................................ 59
`Figure 31: WRITE-to-PRECHARGE ................................................................................................................. 60
`Figure 32: Terminating a WRITE Burst ............................................................................................................ 61
`Figure 33: Alternating Bank Write Accesses ..................................................................................................... 62
`Figure 34: WRITE – Continuous Page Burst ..................................................................................................... 63
`Figure 35: WRITE – DQM Operation ............................................................................................................... 64
`Figure 36: READ With Auto Precharge Interrupted by a READ ......................................................................... 66
`Figure 37: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 67
`Figure 38: READ With Auto Precharge ............................................................................................................ 68
`Figure 39: READ Without Auto Precharge ....................................................................................................... 69
`Figure 40: Single READ With Auto Precharge .................................................................................................. 70
`Figure 41: Single READ Without Auto Precharge ............................................................................................. 71
`Figure 42: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 72
`Figure 43: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 72
`Figure 44: WRITE With Auto Precharge ........................................................................................................... 73
`Figure 45: WRITE Without Auto Precharge ..................................................................................................... 74
`Figure 46: Single WRITE With Auto Precharge ................................................................................................. 75
`Figure 47: Single WRITE Without Auto Precharge ............................................................................................ 76
`Figure 48: Auto Refresh Mode ........................................................................................................................ 78
`Figure 49: Self Refresh Mode .......................................................................................................................... 80
`Figure 50: Power-Down Mode ........................................................................................................................ 81
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`4
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`

`Figure 51: Clock Suspend During WRITE Burst ............................................................................................... 82
`Figure 52: Clock Suspend During READ Burst ................................................................................................. 83
`Figure 53: Clock Suspend Mode ..................................................................................................................... 84
`
`64Mb: x4, x8, x16 SDRAM
`Features
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`5
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
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`
`

`

`64Mb: x4, x8, x16 SDRAM
`Features
`
`List of Tables
`Table 1: Key Timing Parameters ....................................................................................................................... 1
`Table 2: Address Table ..................................................................................................................................... 2
`Table 3: 64Mb SDR Part Numbering ................................................................................................................. 2
`Table 4: Pin and Ball Descriptions .................................................................................................................. 14
`Table 5: Temperature Limits .......................................................................................................................... 17
`Table 6: Thermal Impedance Simulated Values ............................................................................................... 18
`Table 7: Absolute Maximum Ratings .............................................................................................................. 20
`Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 20
`Table 9: Capacitance ..................................................................................................................................... 21
`Table 10: IDD Specifications and Conditions – Revision G ................................................................................ 22
`Table 11: IDD Specifications and Conditions – Revision J ................................................................................. 22
`Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 24
`Table 13: AC Functional Characteristics ......................................................................................................... 26
`Table 14: Truth Table – Commands and DQM Operation ................................................................................. 29
`Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 35
`Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 37
`Table 17: Truth Table – CKE ........................................................................................................................... 39
`Table 18: Burst Definition Table ..................................................................................................................... 45
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`6
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`Micron Technology, Inc. reserves the right to change products or specifications without notice.
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`

`64Mb: x4, x8, x16 SDRAM
`Important Notes and Warnings
`
`Important Notes and Warnings
`Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
`including without limitation specifications and product descriptions. This document supersedes and replaces all
`information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
`ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
`by Micron.
`
`Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
`cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
`utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
`costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
`product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
`automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
`ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
`products are not designed or intended for use in automotive applications unless specifically designated by Micron
`as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
`demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
`fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
`resulting from any use of non-automotive-grade products in automotive applications.
`
`Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
`nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
`("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
`mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
`Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
`component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
`its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
`costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
`product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
`cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
`Micron product.
`
`Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
`applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
`URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
`WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
`PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
`in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
`vironmental damages will result from failure of any semiconductor component.
`
`Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
`damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
`or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
`breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
`authorized representative.
`
`General Description
`The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
`67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous in-
`terface (all signals are registered on the positive edge of the clock signal, CLK). Each of
`the x4’s 16,777,216-bit banks is organized as 4096 rows by 1024 columns by 4 bits. Each
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`7
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`

`64Mb: x4, x8, x16 SDRAM
`General Description
`
`of the x8’s 16,777,216-bit banks is organized as 4096 rows by 512 columns by 8 bits. Each
`of the x16’s 16,777,216-bit banks is organized as 4096 rows by 256 columns by 16 bits.
`
`Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
`location and continue for a programmed number of locations in a programmed se-
`quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
`lowed by a READ or WRITE command. The address bits registered coincident with the
`ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
`bank; A[11:0] select the row). The address bits registered coincident with the READ or
`WRITE command are used to select the starting column location for the burst access.
`
`The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
`locations, or the full page, with a burst terminate option. An auto precharge function
`may be enabled to provide a self-timed row precharge that is initiated at the end of the
`burst sequence.
`
`The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
`tion. This architecture is compatible with the 2n rule of prefetch architectures, but it al-
`so allows the column address to be changed on every clock cycle to achieve a high-
`speed, fully random access. Precharging one bank while accessing one of the other
`three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-
`dom-access operation.
`
`The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
`mode is provided, along with a power-saving, power-down mode. All inputs and out-
`puts are LVTTL-compatible.
`
`SDRAM devices offer substantial advances in DRAM operating performance, including
`the ability to synchronously burst data at a high data rate with automatic column-ad-
`dress generation, the ability to interleave between internal banks to hide precharge
`time, and the capability to randomly change column addresses on each clock cycle dur-
`ing a burst access.
`
`Automotive Temperature
`The automotive temperature (AT) option adheres to the following specifications:
`
`• 16ms refresh rate
`• Self refresh not supported
`• Ambient and case temperature cannot be less than –40°C or greater than +105°C
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`8
`
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`© 1999 Micron Technology, Inc. All rights reserved.
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`

`Functional Block Diagrams
`
`Figure 1: 16 Meg x 4 Functional Block Diagram
`
`64Mb: x4, x8, x16 SDRAM
`Functional Block Diagrams
`
`1
`
`1
`
`DQM
`
`4
`
`4
`
`Data
`output
`register
`
`Data
`input
`register
`
`4
`
`DQ[3:0]
`
`Bank 3
`Bank 2
`Bank 1
`
`Control logic
`
`Command
`
`decode
`
`CKE
`CLK
`CS#
`WE#
`CAS#
`RAS#
`
`Mode register
`
`Refresh
`counter
`
`12
`
`12
`
`12
`
`Row-
`address
`MUX
`
`12
`
`Bank 0
`row-
`address
`latch
`and
`decoder
`
`4096
`
`Bank 0
`memory
`array
`(4096 x 1024 x 4)
`
`Sense amplifiers
`
`4096
`
`A[11:0],
`BA0, BA1
`
`14
`
`Address
`register
`
`2
`
`Bank
`control
`logic
`
`Column
`address
`counter/
`latch
`
`10
`
`2
`
`10
`
`I/O gating
`DQM mask logic
`read data latch
`write drivers
`
`1024
`(x4)
`
`Column
`decoder
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`9
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
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`

`64Mb: x4, x8, x16 SDRAM
`Functional Block Diagrams
`
`Figure 2: 8 Meg x 8 Functional Block Diagram
`
`Bank 3
`Bank 2
`Bank 1
`
`Control logic
`
`Command
`
`decode
`
`CKE
`CLK
`
`CS#
`WE#
`CAS#
`RAS#
`
`Mode register
`
`Refresh
`counter
`
`12
`
`12
`
`12
`
`12
`
`Row-
`address
`MUX
`
`Bank 0
`row-
`address
`latch
`and
`decoder
`
`4096
`
`Bank 0
`memory
`array
`(4096 x 512 x 8)
`
`1
`
`1
`
`DQM
`
`A[11:0],
`BA0, BA1
`
`14
`
`Address
`register
`
`2
`
`Bank
`control
`logic
`
`Column-
`address
`counter/
`latch
`
`9
`
`2
`
`9
`
`Sense amplifiers
`
`4096
`
`I/O gating
`DQM mask logic
`read data latch
`write drivers
`
`512
`(x8)
`
`Column
`decoder
`
`8
`
`8
`
`Data
`output
`register
`
`Data
`input
`register
`
`8
`
`DQ[7:0]
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`10
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
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`
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`

`Figure 3: 4 Meg x 16 Functional Block Diagram
`
`64Mb: x4, x8, x16 SDRAM
`Functional Block Diagrams
`
`Bank 3
`Bank 2
`Bank 1
`
`Control logic
`
`Command
`
`decode
`
`CKE
`CLK
`CS#
`WE#
`CAS#
`RAS#
`
`Mode register
`
`Refresh
`counter
`
`12
`
`12
`
`12
`
`Row-
`address
`MUX
`
`12
`
`Bank 0
`row-
`address
`latch
`and
`decoder
`
`4096
`
`Bank 0
`memory
`array
`(4096 x 256 x 16)
`
`2
`
`2
`
`DQML,
`DQMH
`
`A[11:0],
`BA0, BA1
`
`14
`
`Address
`register
`
`2
`
`Bank
`control
`logic
`
`Column-
`address
`counter/
`latch
`
`8
`
`2
`
`8
`
`Sense amplifiers
`
`4096
`
`I/O gating
`DQM mask logic
`read data latch
`write drivers
`
`256
`(x16)
`
`Column
`decoder
`
`16
`
`Data
`output
`register
`
`16
`
`Data
`input
`register
`
`16
`
`DQ[15:0]
`
`PDF: 09005aef80725c0b
`64mb_x4x8x16_sdram.pdf - Rev. V 05/15 EN
`
`11
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2026
`Samsung v Netlist
`IPR2022-00996
`
`

`

`64Mb: x4, x8, x16 SDRAM
`Pin and Ball Assignments and Descriptions
`
`Pin and Ball Assignments and Descriptions
`
`Figure 4: 54-Pin TSOP (Top View)
`
`x16
`
`VSS
`DQ15
`VSSQ
`DQ14
`DQ13
`VDDQ
`DQ12
`DQ11
`VSSQ
`DQ10
`DQ9
`VDDQ
`DQ8
`VSS
`NC
`DQMH
`CLK
`CKE
`NC
`A11
`A9
`A8
`A7
`A6
`A5
`A4
`VSS
`
`x8
`–
`DQ7
` –
`NC
`DQ6
` –
`NC
`DQ5
` –
`NC
`DQ4
` –
`NC
` –
` –
`DQM
` –
` –
` –
` –
` –
` –
` –
` –
` –
` –
` –
`
`x4
`–
`NC
` –
`NC
`DQ3
` –
`NC
`NC
` –
`NC
`DQ2
` –
`NC
` –
` –
`DQM
` –
` –
` –
` –
` –
` –
` –
` –
` –
` –
` –
`
`54
`53
`52
`51
`50
`49
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`
`1234567891
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`
`x4
`–
`NC
`–
`NC
`DQ0
`–
`NC
`NC
`–
`NC
`DQ1
`–
`NC
`–
`NC
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`
`x8
`–
`DQ0
`–
`NC
`DQ1
`–
`NC
`DQ2
`–
`NC
`DQ3
`–
`NC
`–
`NC
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`–
`
`x16
`
`VDD
`DQ0
`VDDQ
`DQ1
`DQ2
`VSSQ
`DQ3
`DQ4
`VDDQ
`DQ5
`DQ6
`VSSQ
`DQ7
`VDD
`DQML
`WE#
`CAS#
`RAS#
`CS#
`BA0
`BA1
`A10
`A0
`A1
`A2
`A3
`VDD
`
`Notes:
`
`1. A dash (–) indicates that the x8 and x4 pin function is the same as the x16 pin function.
`2. Package may or may not be assemb