256Mb: x4, x8, x16 SDRAM
`Features
`
`SDR SDRAM
`MT48LC64M4A2 – 16 Meg x 4 x 4 banks
`MT48LC32M8A2 – 8 Meg x 8 x 4 banks
`MT48LC16M16A2 – 4 Meg x 16 x 4 banks
`
`Features
`• PC100- and PC133-compliant
`• Fully synchronous; all signals registered on positive
`edge of system clock
`• Internal, pipelined operation; column address can
`be changed every clock cycle
`• Internal banks for hiding row access/precharge
`• Programmable burst lengths: 1, 2, 4, 8, or full page
`• Auto precharge, includes concurrent auto precharge
`and auto refresh modes
`• Self refresh mode (not available on AT devices)
`• Auto refresh
`– 64ms, 8192-cycle refresh (commercial and
`industrial)
`– 16ms, 8192-cycle refresh (automotive)
`• LVTTL-compatible inputs and outputs
`• Single 3.3V ±0.3V power supply
`
`Options
`• Configurations
`– 64 Meg x 4 (16 Meg x 4 x 4 banks)
`– 32 Meg x 8 (8 Meg x 8 x 4 banks)
`– 16 Meg x 16 (4 Meg x 16 x 4 banks)
`• Write recovery (tWR)
`– tWR = 2 CLK
`• Plastic package – OCPL1
`– 54-pin TSOP II OCPL1 (400 mil)
`(standard)
`– 54-pin TSOP II OCPL1 (400 mil)
`Pb-free
`– 60-ball TFBGA (x4, x8) (8mm x
`16mm)
`– 60-ball TFBGA (x4, x8) (8mm x
`16mm) Pb-free
`– 54-ball VFBGA (x16) (8mm x 14 mm)
`– 54-ball VFBGA (x16) (8mm x 14 mm)
`Pb-free
`– 54-ball VFBGA (x16) (8mm x 8 mm)
`– 54-ball VFBGA (x16) (8mm x 8 mm)
`Pb-free
`• Timing – cycle time
`– 6ns @ CL = 3 (x8, x16 only)
`– 7.5ns @ CL = 3 (PC133)
`– 7.5ns @ CL = 2 (PC133)
`• Self refresh
`– Standard
`– Low power
`• Operating temperature range
`– Commercial (0˚C to +70˚C)
`– Industrial (–40˚C to +85˚C)
`– Automotive (–40˚C to +105˚C)
`• Revision
`
`Notes:
`
`1. Off-center parting line.
`2. Only available on Revision D.
`3. Only available on Revision G.
`4. Contact Micron for availability.
`
`Marking
`
`64M4
`32M8
`16M16
`
`A2
`
`TG
`
`P
`
`FB
`
`BB
`
`FG2
`BG2
`
`F43
`B43
`
`-6A
`-752
`-7E
`
`None
`L2, 4
`
`None
`IT
`AT4
`:D/:G
`
`1
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`PDF: 09005aef8091e6d1
`© 1999 Micron Technology, Inc. All rights reserved.
`256Mb_sdr.pdf - Rev. W 05/15 EN
`Products and specifications discussed herein are subject to change by Micron without notice.
`
`Netlist Ex 2025
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256Mb: x4, x8, x16 SDRAM
`Features
`
`Table 1: Key Timing Parameters
`
`CL = CAS (READ) latency
`
`Speed Grade
`-6A
`-75
`-7E
`
`Clock
`Frequency (MHz)
`167
`133
`133
`
`Table 2: Address Table
`
`Parameter
`Configuration
`Refresh count
`Row addressing
`Bank addressing
`Column addressing
`
`Target tRCD-tRP-CL
`3-3-3
`3-3-3
`2-2-2
`
`tRCD (ns)
`18
`20
`15
`
`tRP (ns)
`18
`20
`15
`
`CL (ns)
`18
`20
`15
`
`64 Meg x 4
`16 Meg x 4 x 4 banks
`8K
`8K A[12:0]
`4 BA[1:0]
`2K A[9:0], A11
`
`32 Meg x 8
`8 Meg x 8 x 4 banks
`8K
`8K A[12:0]
`4 BA[1:0]
`1K A[9:0]
`
`16 Meg x 16
`4 Meg x 16 x 4 banks
`8K
`8K A[12:0]
`4 BA[1:0]
`512 A[8:0]
`
`Table 3: 256Mb SDR Part Numbering
`
`Part Numbers
`MT48LC64M4A2TG
`MT48LC64M4A2P
`MT48LC64M4A2FB1
`MT48LC64M4A2BB1
`MT48LC32M8A2TG
`MT48LC32M8A2P
`MT48LC32M8A2FB1
`MT48LC32M8A2BB1
`MT48LC16M16A2TG
`MT48LC16M16A2P
`MT48LC16M16A2FG
`MT48LC16M16A2BG
`
`Architecture
`64 Meg x 4
`64 Meg x 4
`64 Meg x 4
`64 Meg x 4
`32 Meg x 8
`32 Meg x 8
`32 Meg x 8
`32 Meg x 8
`16 Meg x 16
`16 Meg x 16
`16 Meg x 16
`16 Meg x 16
`
`Note:
`
`1. FBGA Device Decoder: www.micron.com/decoder.
`
`Package
`54-pin TSOP II
`54-pin TSOP II
`60-ball FBGA
`60-ball FBGA
`54-pin TSOP II
`54-pin TSOP II
`60-ball FBGA
`60-ball FBGA
`54-pin TSOP II
`54-pin TSOP II
`54-ball FBGA
`54-ball FBGA
`
`PDF: 09005aef8091e6d1
`256Mb_sdr.pdf - Rev. W 05/15 EN
`
`2
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2025
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256Mb: x4, x8, x16 SDRAM
`Features
`
`Contents
`Important Notes and Warnings ......................................................................................................................... 8
`General Description ......................................................................................................................................... 8
`Automotive Temperature .............................................................................................................................. 9
`Functional Block Diagrams ............................................................................................................................. 10
`Pin and Ball Assignments and Descriptions ..................................................................................................... 13
`Package Dimensions ....................................................................................................................................... 17
`Temperature and Thermal Impedance ............................................................................................................ 21
`Electrical Specifications .................................................................................................................................. 25
`Electrical Specifications – IDD Parameters ........................................................................................................ 27
`Electrical Specifications – AC Operating Conditions ......................................................................................... 29
`Functional Description ................................................................................................................................... 32
`Commands .................................................................................................................................................... 33
`COMMAND INHIBIT .................................................................................................................................. 33
`NO OPERATION (NOP) ............................................................................................................................... 34
`LOAD MODE REGISTER (LMR) ................................................................................................................... 34
`ACTIVE ...................................................................................................................................................... 34
`READ ......................................................................................................................................................... 35
`WRITE ....................................................................................................................................................... 36
`PRECHARGE .............................................................................................................................................. 37
`BURST TERMINATE ................................................................................................................................... 37
`REFRESH ................................................................................................................................................... 38
`AUTO REFRESH ..................................................................................................................................... 38
`SELF REFRESH ....................................................................................................................................... 38
`Truth Tables ................................................................................................................................................... 39
`Initialization .................................................................................................................................................. 44
`Mode Register ................................................................................................................................................ 46
`Burst Length .............................................................................................................................................. 48
`Burst Type .................................................................................................................................................. 48
`CAS Latency ............................................................................................................................................... 50
`Operating Mode ......................................................................................................................................... 50
`Write Burst Mode ....................................................................................................................................... 50
`Bank/Row Activation ...................................................................................................................................... 51
`READ Operation ............................................................................................................................................. 52
`WRITE Operation ........................................................................................................................................... 61
`Burst Read/Single Write .............................................................................................................................. 68
`PRECHARGE Operation .................................................................................................................................. 69
`Auto Precharge ........................................................................................................................................... 69
`AUTO REFRESH Operation ............................................................................................................................. 81
`SELF REFRESH Operation ............................................................................................................................... 83
`Power-Down .................................................................................................................................................. 85
`Clock Suspend ............................................................................................................................................... 86
`Revision History ............................................................................................................................................. 89
`Rev. W – 05/15 ............................................................................................................................................ 89
`Rev. W – 09/14 ............................................................................................................................................ 89
`Rev. V – 1/14, 8/14 ...................................................................................................................................... 89
`Rev. U – 05/13 ............................................................................................................................................. 89
`Rev. T – 03/13 ............................................................................................................................................. 89
`Rev. S – 12/12 ............................................................................................................................................. 89
`Rev. R – 10/12 ............................................................................................................................................. 89
`Rev. Q – 02/12 ............................................................................................................................................. 89
`
`PDF: 09005aef8091e6d1
`256Mb_sdr.pdf - Rev. W 05/15 EN
`
`3
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
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`
`

`

`256Mb: x4, x8, x16 SDRAM
`Features
`
`Rev. P – 12/11 ............................................................................................................................................. 89
`Rev. O – 07/11 ............................................................................................................................................. 90
`Rev. N – 01/10 ............................................................................................................................................. 90
`Rev. M – 11/08 ............................................................................................................................................ 90
`Rev. L – 08/07 ............................................................................................................................................. 90
`Rev. K – 02/07 ............................................................................................................................................. 91
`Rev. K – 06/06 ............................................................................................................................................. 91
`Rev. J – 03/05 .............................................................................................................................................. 91
`Rev. H – 02/05 ............................................................................................................................................. 91
`Rev. H – 10/04 ............................................................................................................................................. 91
`Rev. G – 08/03 ............................................................................................................................................. 91
`Rev. F – 01/03 ............................................................................................................................................. 91
`Rev. E – 03/02 ............................................................................................................................................. 92
`Rev. D – 07/01 ............................................................................................................................................. 92
`Rev. C – 03/01 ............................................................................................................................................. 92
`Rev. B – 10/00 ............................................................................................................................................. 93
`Rev. A – 11/99 ............................................................................................................................................. 93
`
`PDF: 09005aef8091e6d1
`256Mb_sdr.pdf - Rev. W 05/15 EN
`
`4
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2025
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256Mb: x4, x8, x16 SDRAM
`Features
`
`List of Figures
`Figure 1: 64 Meg x 4 Functional Block Diagram ............................................................................................... 10
`Figure 2: 32 Meg x 8 Functional Block Diagram ............................................................................................... 11
`Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 12
`Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 13
`Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 14
`Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 15
`Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil) ............................................................................................... 17
`Figure 8: 60-Ball TFBGA "BB/FB" (8mm x 16mm) (x4, x8) ............................................................................... 18
`Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16) .................................................................................. 19
`Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16) ................................................................................... 20
`Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 23
`Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 23
`Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 24
`Figure 14: ACTIVE Command ........................................................................................................................ 34
`Figure 15: READ Command ........................................................................................................................... 35
`Figure 16: WRITE Command ......................................................................................................................... 36
`Figure 17: PRECHARGE Command ................................................................................................................ 37
`Figure 18: Initialize and Load Mode Register .................................................................................................. 45
`Figure 19: Mode Register Definition ............................................................................................................... 47
`Figure 20: CAS Latency .................................................................................................................................. 50
`Figure 21: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 51
`Figure 22: Consecutive READ Bursts .............................................................................................................. 53
`Figure 23: Random READ Accesses ................................................................................................................ 54
`Figure 24: READ-to-WRITE ............................................................................................................................ 55
`Figure 25: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 56
`Figure 26: READ-to-PRECHARGE .................................................................................................................. 56
`Figure 27: Terminating a READ Burst ............................................................................................................. 57
`Figure 28: Alternating Bank Read Accesses ..................................................................................................... 58
`Figure 29: READ Continuous Page Burst ......................................................................................................... 59
`Figure 30: READ – DQM Operation ................................................................................................................ 60
`Figure 31: WRITE Burst ................................................................................................................................. 61
`Figure 32: WRITE-to-WRITE .......................................................................................................................... 62
`Figure 33: Random WRITE Cycles .................................................................................................................. 63
`Figure 34: WRITE-to-READ ............................................................................................................................ 63
`Figure 35: WRITE-to-PRECHARGE ................................................................................................................. 64
`Figure 36: Terminating a WRITE Burst ............................................................................................................ 65
`Figure 37: Alternating Bank Write Accesses ..................................................................................................... 66
`Figure 38: WRITE – Continuous Page Burst ..................................................................................................... 67
`Figure 39: WRITE – DQM Operation ............................................................................................................... 68
`Figure 40: READ With Auto Precharge Interrupted by a READ ......................................................................... 70
`Figure 41: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 71
`Figure 42: READ With Auto Precharge ............................................................................................................ 72
`Figure 43: READ Without Auto Precharge ....................................................................................................... 73
`Figure 44: Single READ With Auto Precharge .................................................................................................. 74
`Figure 45: Single READ Without Auto Precharge ............................................................................................. 75
`Figure 46: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 76
`Figure 47: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 76
`Figure 48: WRITE With Auto Precharge ........................................................................................................... 77
`Figure 49: WRITE Without Auto Precharge ..................................................................................................... 78
`Figure 50: Single WRITE With Auto Precharge ................................................................................................. 79
`
`PDF: 09005aef8091e6d1
`256Mb_sdr.pdf - Rev. W 05/15 EN
`
`5
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2025
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256Mb: x4, x8, x16 SDRAM
`Features
`
`Figure 51: Single WRITE Without Auto Precharge ............................................................................................ 80
`Figure 52: Auto Refresh Mode ........................................................................................................................ 82
`Figure 53: Self Refresh Mode .......................................................................................................................... 84
`Figure 54: Power-Down Mode ........................................................................................................................ 85
`Figure 55: Clock Suspend During WRITE Burst ............................................................................................... 86
`Figure 56: Clock Suspend During READ Burst ................................................................................................. 87
`Figure 57: Clock Suspend Mode ..................................................................................................................... 88
`
`PDF: 09005aef8091e6d1
`256Mb_sdr.pdf - Rev. W 05/15 EN
`
`6
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2025
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256Mb: x4, x8, x16 SDRAM
`Features
`
`List of Tables
`Table 1: Key Timing Parameters ....................................................................................................................... 2
`Table 2: Address Table ..................................................................................................................................... 2
`Table 3: 256Mb SDR Part Numbering ............................................................................................................... 2
`Table 4: Pin and Ball Descriptions .................................................................................................................. 16
`Table 5: Temperature Limits .......................................................................................................................... 21
`Table 6: Thermal Impedance Simulated Values ............................................................................................... 22
`Table 7: Absolute Maximum Ratings .............................................................................................................. 25
`Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 25
`Table 9: Capacitance ..................................................................................................................................... 26
`Table 10: IDD Specifications and Conditions (x4, x8, x16) Revision D ................................................................ 27
`Table 11: IDD Specifications and Conditions (x4, x8, x16) Revision G ................................................................ 27
`Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 29
`Table 13: AC Functional Characteristics ......................................................................................................... 30
`Table 14: Truth Table – Commands and DQM Operation ................................................................................. 33
`Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 39
`Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 41
`Table 17: Truth Table – CKE ........................................................................................................................... 43
`Table 18: Burst Definition Table ..................................................................................................................... 49
`
`PDF: 09005aef8091e6d1
`256Mb_sdr.pdf - Rev. W 05/15 EN
`
`7
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2025
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256Mb: x4, x8, x16 SDRAM
`Important Notes and Warnings
`
`Important Notes and Warnings
`Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
`including without limitation specifications and product descriptions. This document supersedes and replaces all
`information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
`ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
`by Micron.
`
`Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
`cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
`utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
`costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
`product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
`automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
`ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
`products are not designed or intended for use in automotive applications unless specifically designated by Micron
`as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
`demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
`fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
`resulting from any use of non-automotive-grade products in automotive applications.
`
`Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
`nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
`("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
`mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
`Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
`component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
`its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
`costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
`product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
`cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
`Micron product.
`
`Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
`applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
`URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
`WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
`PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
`in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
`vironmental damages will result from failure of any semiconductor component.
`
`Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
`damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
`or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
`breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
`authorized representative.
`
`General Description
`The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory contain-
`ing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchro-
`nous interface (all signals are registered on the positive edge of the clock signal, CLK).
`Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4
`
`PDF: 09005aef8091e6d1
`256Mb_sdr.pdf - Rev. W 05/15 EN
`
`8
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2025
`Samsung v Netlist
`IPR2022-00996
`
`

`

`256Mb: x4, x8, x16 SDRAM
`General Description
`
`bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by
`8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns
`by 16 bits.
`
`Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
`location and continue for a programmed number of locations in a programmed se-
`quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
`lowed by a READ or WRITE command. The address bits registered coincident with the
`ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
`bank; A[12:0] select the row). The address bits registered coincident with the READ or
`WRITE command are used to select the starting column location for the burst access.
`
`The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
`locations, or the full page, with a burst terminate option. An auto precharge function
`may be enabled to provide a self-timed row