3.3V 2M x 64/72-Bit 1 BANK SDRAM Module
`3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
`
`HYS64/72V2200GU-8/-10
`HYS64/72V4220GU-8/-10
`
`168 pin unbuffered DIMM Modules
`
`• 168 Pin PC100 and PC66 compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules
`for PC main memory applications
`
`• 1 bank 2M x 64, 2M x 72 and 2 bank 4M x 64, 4M x 72 organisation
`
`• Optimized for byte-write non-parity or ECC applications
`
`• JEDEC standard Synchronous DRAMs (SDRAM)
`
`• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
`
`• SDRAM Performance:
`
`fCK
`tAC
`
`Clock frequency (max.)
`
`Clock access time
`
`• Programmed Latencies :
`
`-8
`
`100
`
`6
`
`-8-3
`
`100
`
`6
`
`-10
`
`66
`
` 8
`
`Units
`
`MHz
`
`ns
`
`Product Speed
`
`-8
`
`-8-3
`
`PC100
`
`PC100
`
`CL
`
`2
`
`3
`
`tRCD
`
`tRP
`
`2
`
`2
`
`2
`
`3
`
`PC66
`
`2
`
` 0.3V ) power supply
`
`-10
`• Single +3.3V(–
`• Programmable CAS Latency, Burst Length and Wrap Sequence
`(Sequential & Interleave)
`
`2
`
`2
`
`• Auto Refresh (CBR) and Self Refresh
`
`• Decoupling capacitors mounted on substrate
`
`• All inputs, outputs are LVTTL compatible
`• Serial Presence Detect with E2PROM
`
`• Utilizes 2M x 8 SDRAMs in TSOPII-44 packages
`
`• 4096 refresh cycles every 64 ms
`
`• 133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads
`
`Semiconductor Group
`
`
`
`11
`
`6.98
`
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`
`

`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`The HYS64(72)2200 and HYS64(72)4220 are industry standard 168-pin 8-byte Dual in-line Memory Modules
`(DIMMs) which are organised as 2M x 64, 2M x 72 in 1 bank and 4M x 64 and 4M x 72 in two banks high speed
`memory arrays designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs
`use -8 speed sort 2M x 8 SDRAM devices in TSOP44 packages to meet the PC100 requirement. Modules which
`use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The
`PC board design is according to INTEL’s PC SDRAM Rev.1.0 module specification.
`The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I2C protocol. The
`first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
`
`All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint,
`with 1,25“ ( 31,75 mm) height
`Ordering Information
`
`Type
`
`Ordering Code
`
`Package
`
`Descriptions
`
`HYS 64V2200GU-8
`
`PC100-222-620
`
`L-DIM-168-29 100 Mhz 2M x 64 1 bank SDRAM module
`
`HYS 72V2200GU-8
`
`PC100-222-620
`
`L-DIM-168-29 100 MHz 2M x 72 1 bank SDRAM module
`
`HYS 64V4220GU-8
`
`PC100-222-620
`
`L-DIM-168-29 100 Mhz 4M x 64 2 bank SDRAM module
`
`HYS 72V4220GU-8
`
`PC100-222-620
`
`L-DIM-168-29 100 Mhz 4M x 72 2 bank SDRAM module
`
`HYS 64V2200GU-8-3
`
`PC100-323-620
`
`L-DIM-168-29 100 Mhz 2M x 64 1 bank SDRAM module
`
`HYS 72V2200GU-8-3
`
`PC100-323-620
`
`L-DIM-168-29 100 MHz 2M x 72 1 bank SDRAM module
`
`HYS 64V4220GU-8-3
`
`PC100-323-620
`
`L-DIM-168-29 100 Mhz 4M x 64 2 bank SDRAM module
`
`HYS 72V4220GU-8-3
`
`PC100-323-620
`
`L-DIM-168-29 100 Mhz 4M x 72 2 bank SDRAM module
`
`HYS 64V2200GU-10
`
`PC66-222-920
`
`L-DIM-168-29 66 Mhz 2M x 64 1 bank SDRAM module
`
`HYS 72V2200GU-10
`
`PC66-222-920
`
`L-DIM-168-29 66 MHz 2M x 72 1 bank SDRAM module
`
`HYS 64V4220GU-10
`
`PC66-222-920
`
`L-DIM-168-29 66 Mhz 4M x 64 2 bank SDRAM module
`
`HYS 72V4220GU-10
`
`PC66-222-920
`
`L-DIM-168-29 66 Mhz 4M x 72 2 bank SDRAM module
`
`Module
`Height
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`1,25“
`
`Pin Names
`
`Address Inputs
`A0-A10
`Bank Address
`BA
`DQ0 - DQ63 Data Input/Output
`CB0-CB7
`Check Bits (x72
`organisation only)
`Row Address Strobe
`RAS
`CAS
`Column Address Strobe
`Read / Write Input
`WE
`CKE0, CKE1 Clock Enable
`
`Address Format:
`
`Clock Input
`CLK0 - CLK3
`DQMB0 - DQMB7 Data Mask
`CS0 - CS3
`Chip Select
`Vcc
`Power (+3.3 Volt)
`
`Vss
`SCL
`SDA
`N.C.
`
`Ground
`Clock for Presence Detect
`Serial Data Out for Presence Detect
`No Connection
`
`2M x 64
`2M x 72
`4M x 64
`4M x 72
`
`Part Number
`HYS 64V2200GU
`HYS 72V2200GU
`HYS 64V4220GU
`HYS 72V4220GU
`
`Rows
`11
`11
`11
`11
`
`Columns
`9
`9
`9
`9
`
`Banks
`1
`1
`1
`1
`
`Refresh
`4k
`4k
`4k
`4k
`
`Period
`64 ms
`64 ms
`64 ms
`64 ms
`
`Interval
`15,6 m s
`15,6 m s
`15,6 m s
`15,6 m s
`
`Semiconductor Group
`
`2
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`
`

`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
` Pin Configuration
`PIN #
`Symbol
`
`PIN #
`
`Symbol
`
`PIN #
`
`Symbol
`
`PIN #
`
`Symbol
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`
`VSS
`DQ0
`DQ1
`DQ2
`DQ3
`VCC
`DQ4
`DQ5
`DQ6
`DQ7
`DQ8
`VSS
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`VCC
`DQ14
`DQ15
`NC (CB0)
`NC (CB1)
`VSS
`NC
`NC
`VCC
`WE
`DQMB0
`DQMB1
`CS0
`DU
`VSS
`A0
`A2
`A4
`A6
`A8
`A10
`NC
`VCC
`VCC
`CLK0
`
`43
`44
`45
`46
`47
`48
`49
`50
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`
`VSS
`DU
`CS2
`DQMB2
`DQMB3
`DU
`VCC
`NC
`NC
`NC (CB2)
`NC (CB3)
`VSS
`DQ16
`DQ17
`DQ18
`DQ19
`VCC
`DQ20
`NC
`DU
`CKE1
`VSS
`DQ21
`DQ22
`DQ23
`VSS
`DQ24
`DQ25
`DQ26
`DQ27
`VCC
`DQ28
`DQ29
`DQ30
`DQ31
`VSS
`CLK2
`NC
`WP
`SDA
`SCL
`VCC
`
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`100
`101
`102
`103
`104
`105
`106
`107
`108
`109
`110
`111
`112
`113
`114
`115
`116
`117
`118
`119
`120
`121
`122
`123
`124
`125
`126
`
`VSS
`DQ32
`DQ33
`DQ34
`DQ35
`VCC
`DQ36
`DQ37
`DQ38
`DQ39
`DQ40
`VSS
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`VCC
`DQ46
`DQ47
`NC (CB4)
`NC (CB5)
`VSS
`NC
`NC
`VCC
`CAS
`DQMB4
`DQMB5
`CS1
`RAS
`VSS
`A1
`A3
`A5
`A7
`A9
`BA
`NC
`VCC
`CLK1
`NC
`
`127
`128
`129
`130
`131
`132
`133
`134
`135
`136
`137
`138
`139
`140
`141
`142
`143
`144
`145
`146
`147
`148
`149
`150
`151
`152
`153
`154
`155
`156
`157
`158
`159
`160
`161
`162
`163
`164
`165
`166
`167
`168
`
`VSS
`CKE0
`CS3
`DQMB6
`DQMB7
`NC
`VCC
`NC
`NC
`CB6
`CB7
`VSS
`DQ48
`DQ49
`DQ50
`DQ51
`VCC
`DQ52
`NC
`DU
`NC
`VSS
`DQ53
`DQ54
`DQ55
`VSS
`DQ56
`DQ57
`DQ58
`DQ59
`VCC
`DQ60
`DQ61
`DQ62
`DQ63
`VSS
`CLK3
`NC
`SA0
`SA1
`SA2
`VCC
`
`Note : Pinnames in brackets are for the x72 ECC versions
`
`Semiconductor Group
`
`3
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`
`

`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`WE
`
`CS0
`
`DQMB0
`
`DQ(7:0)
`
`DQMB1
`
`DQ(15:8)
`
`CB(7:0)
`
`CS2
`
`DQMB2
`
`DQ(23:16)
`
`DQMB3
`
`DQ(31:24)
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D0
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D1
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D8
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D2
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D3
`
`DQMB4
`
`DQ(39:32)
`
`DQMB5
`
`DQ(47:40)
`
`DQMB6
`
`DQ(55:48)
`
`DQMB7
`
`DQ(63:56)
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D4
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D5
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D6
`
`CS WE
`
`DQM
`
`DQ0-DQ7
`
`D7
`
`A0-A10,BA
`
`D0 - D7,(D8)
`
`E2PROM (256wordx8bit)
`
`C0-C7,(C8)
`
`D0 - D7,(D8)
`
`D0 - D7,(D8)
`
`SA0
`SA1
`SA2
`SCL
`
`SA0
`SA1
`SA2
`SCL
`
`SDA
`WP
`
`47k
`
`Clock Wiring
`2M x 64 2M x 72
`CLK0 4 SDRAM+3.3pF 5 SDRAM
`CLK1 Termination Termination
`CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF
`CLK3 Termination Termination
`
`VCC
`
`VSS
`
`RAS
`
`CAS
`
`CKE0
`
`D0 - D7,(D8)
`
`D0 - D7,(D8)
`
`D0 - D7,(D8)
`
`Note: D8 is only used in the x72 ECC version
`
`
`Block Diagram for 2M x 64/72 SDRAM DIMM modules (HYS64/72V2200GU)
`
`Semiconductor Group
`
`4
`
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`
`

`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`CS1
`
`CS0
`
`DQMB0
`
`DQ(7:0)
`
`DQMB1
`
`DQ(15:8)
`
`CB(7:0)
`
`CS3
`
`CS2
`
`DQMB2
`
`DQ(23:16)
`
`DQMB3
`
`DQ(31:24)
`
`DQMB4
`
`DQ(39:32)
`
`DQMB5
`
`DQ(47:40)
`
`CS
`
`DQM
`
`DQM
`
`CS
`
`DQ0-DQ7
`D4
`
`DQ0-DQ7
`D12
`
`DQM
`
`CS
`
`DQM
`
`CS
`
`DQ0-DQ7
`D5
`
`DQ0-DQ7
`D13
`
`DQM
`
`CS
`
`CS
`
`DQM
`
`DQ0-DQ7
`D0
`
`DQ0-DQ7
`D8
`
`DQM
`
`CS
`
`DQM
`
`CS
`
`DQ0-DQ7
`D1
`
`DQ0-DQ7
`D9
`
`CS
`
`DQM
`
`CS
`DQM
`
`DQ0-DQ7
`D16
`
`DQ0-DQ7
`D17
`
`CS
`
`DQM
`
`CS
`
`DQM
`
`DQ0-DQ7
`D2
`
`DQ0-DQ7
`D10
`
`CS
`
`DQM
`
`CS
`
`DQM
`
`DQ0-DQ7
`D3
`
`DQ0-DQ7
`D11
`
`DQMB6
`
`DQ(55:48)
`
`DQMB7
`
`DQ(63:56)
`
`CS
`
`CS
`
`DQM
`
`DQM
`
`DQ0-DQ7
`D6
`
`DQ0-DQ7
`D14
`
`CS
`
`DQM
`
`CS
`
`DQM
`
`DQ0-DQ7
`D7
`
`DQ0-DQ7
`D15
`
`A0-A10,BA
`
`D0 - D15,(D16,D17)
`
`VDD
`
`VSS
`
`C0-C31,(C32..C35)
`
`D0 - D15,(D16,D17)
`
`D0 - D7,(D8)
`
`RAS, CAS, WE
`
`D0 - D15,(D16,D17)
`
`E2PROM (256wordx8bit)
`SA0
`SA0
`SA1
`SA1
`SA2
`SA2
`SCL
`SCL
`
`SDA
`WP
`
`47k
`
`CKE0
`
`CKE1
`
`
`VDD
`10k
`
`D0 - D7,(D16)
`
`D9 - D15,(D17)
`
`Clock Wiring
`4M x 64 4M x 72
`
`CLK0 4 SDRAM+3.3pF 5 SDRAM
`CLK1 4 SDRAM+3.3pF 5 SDRAM
`CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF
`CLK3 4 SDRAM+3.3pF 4 SDRAM+3.3pF
`
`Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted.
`
`Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4220GU)
`
`Semiconductor Group
`
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`
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`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`DC Characteristics
`TA = 0 to 70 (cid:176)C; VSS = 0 V; VDD,VDDQ = 3.3 V – 0.3 V
`
`Parameter
`
`Symbol
`
`Input high voltage
`Input low voltage
`Output high voltage (IOUT = – 2.0 mA)
`Output low voltage (IOUT = 2.0 mA)
`Input leakage current, any input
`(0 V < VIN < 3.6 V, all other inputs = 0 V)
`Output leakage current
`(DQ is disabled, 0 V < VOUT < VCC)
`
`VIH
`VIL
`VOH
`VOL
`II(L)
`
`IO(L)
`
`Unit
`
`Limit Values
`min.
`max.
`2.0
`Vcc+0.3 V
`– 0.5
`0.8
`V
`2.4
`–
`V
`–
`0.4
`V
`m A
`– 40
`40
`
`– 40
`
`40
`
`m A
`
`Capacitance
`TA = 0 to 70 (cid:176)C; VDD = 3.3 V – 0.3 V, f = 1 MHz
`
`Parameter
`
`Symbol
`
`Input capacitance
` (A0 to A10, BA, RAS, CAS, WE)
`Input capacitance (CS0 -CS3 )
`Input capacitance (CLK0 - CLK3)
`Input capacitance (CKE0, CKE1)
`Input capacitance (DQMB0 - DQMB7)
`Input / Output capacitance
`(DQ0-DQ63,CB0-CB7)
`Input Capacitance (SCL,SA0-2)
`Input/Output Capacitance
`
`CI1
`
`CI2
`CICL
`CI3
`CI4
`CIO
`
`Csc
`Csd
`
`Limit Values
`max.
`max.
`2Mx72
`4Mx64
`55
`80
`
`max.
`2Mx64
`45
`
`max.
`4Mx72
`90
`
`20
`22
`22
`13
`13
`
`8
`10
`
`25
`38
`38
`13
`12
`
`8
`10
`
`30
`22
`50
`20
`20
`
`8
`10
`
`35
`38
`55
`20
`20
`
`8
`10
`
`Unit
`
`pF
`
`pF
`pF
`pF
`pF
`pF
`
`pF
`pF
`
`Semiconductor Group
`
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`
`

`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`Note
`
`Standby and Refresh Currents (Ta = 0 to 70oC, VCC = 3.3V – 0.3V) 1)
` Parameter
`Symbol
`Test Condition
`X64 X72
`max.
`800
`900 mA 1,2
`
`Operating Current
`
`Icc1
`
`Burst length = 4, CL=3
`trc>=trc(min.),
`tck>=tck(min.), Io=0 mA
`2 bank interleave operation
`
` Precharged Standby
` Current in Power
` Down Mode
` Precharged Standby
` Current in Non-
`power
` Down Mode
`
` Active Standby
` Current in Power
`Down Mode
`
` Active Standby
` Current in Non-
`power Down Mode
`
`Burst Operating
`Current
`
` Auto (CBR) Refresh
`Current
` Self Refresh Current
`
`CKE<=VIL(max), tck>=tck(min.)
`
`Icc2P
`Icc2PS CKE<=VIL(max), tck=infinite
`
`24
`16
`
`27 mA
`18 mA
`
`Icc2N CKE>=VIH(min), tck>=tck (min.),
`input changed once in 3 cycles
`
`160
`
`180 mA CS=
`High
`
`Icc2NS CKE>=VIH(min), tck=infinite,
`no input change
`
`CKE<=VIL(max), tck>=tck(min.)
`
`Icc3P
`Icc3PS CKE<=VIL(max), tck=infinite
`
`80
`
`24
`16
`
`90 mA
`
`27 mA
`18 mA
`
`Icc3N CKE>=VIH(min), tck>=tck (min.)
`input changed one time
`
`200
`
`225 mA CS=
`High
`
`Icc3NS CKE=>VIH(min),tck=infinite,
`no input change
`
`120
`
`135 mA
`
`Icc4
`
`Icc5
`
`Burst length = full page,
`trc = infinite, CL = 3,
`tck>=tck (min.), Io = 0 mA
`2 banks activated
`trc>=trc(min)
`
`760
`
`855 mA 1,2
`
`720
`
`810 mA 1,2
`
`Icc6
`
`CKE=<0,2V
`
`16
`
`18 mA 1,2
`
`Semiconductor Group
`
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`
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`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`AC Characteristics 3)4)
`TA = 0 to 70 (cid:176)C; VSS = 0 V; VCC = 3.3 V – 0.3 V, tT = 1 ns
`
`Parameter
`
`Symbol
`
`Limit Values
`-8
`-10
`-8-3
`PC66
`PC100
`PC100
`2-2-2
`3-2-3
`2-2-2
`min. max. min. max. min. max.
`
`Unit
`
`Note
`
`4,5)
`
`6)
`
`6)
`
`7)
`
`7)
`
`8)
`
`9)
`
`ns
`ns
`
`100
`66
`
`MHz
`MHz
`
`ns
`ns
`ns
`ns
`ns
`ns
`ns
`
`ns
`
`ns
`
`89
`
`–
`–
`–
`–
`–
`
`–
`
`–
`
`ns
`–
`120k ns
`–
`ns
`–
`ns
`–
`ns
`–
`CLK
`
`10
`15
`
`– –
`
`––
`
`3.5
`3.5
`3
`1
`3
`
`8
`
`1
`
`30
`75
`45
`30
`20
`1
`
`100
`100
`
`67
`
`–
`–
`–
`–
`–
`
`–
`
`–
`
`–
`120k
`–
`–
`–
`–
`
`10
`10
`
`– –
`
`––
`
`3
`3
`2
`1
`2.5
`
`8
`
`1
`
`20
`70
`45
`30
`20
`1
`
`100
`100
`
`66
`
`–
`–
`–
`–
`–
`
`–
`
`–
`
`–
`120k
`–
`–
`–
`–
`
`10
`10
`
`– –
`
`––
`
`3
`3
`2
`1
`2.5
`
`8
`
`1
`
`20
`70
`45
`20
`16
`1
`
`Clock and Clock Enable
`Clock Cycle Time
`CAS Latency = 3
`CAS Latency = 2
`System Frequency
`CAS Latency = 3
`CAS Latency = 2
`Clock Access Time
`CAS Latency = 3
`CAS Latency = 2
`Clock High Pulse Width
`Clock Low Pulse Width
`Input Setup time
`Input Hold Time
`CKE Setup Time
`(Power down mode)
`CKE Setup Time
`(Self Refresh Exit)
`Transition time (rise and fall)
`
`Common Parameters
`RAS to CAS delay
`Cycle Time
`Active Command Period
`Precharge Time
`Bank to Bank Delay Time
`CAS to CAS delay time
`(same bank)
`
`tCK
`
`fCK
`
`tAC
`
`tCH
`tCL
`tCS
`tCH
`tCKSP
`
`tCKSR
`
`tT
`
`tRCD
`tRC
`tRAS
`tRP
`tRRD
`tCCD
`
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`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`Parameter
`
`Symbol
`
`Limit Values
`-8
`-10
`-8-3
`PC66
`PC100
`PC100
`2-2-2
`3-2-3
`2-2-2
`min. max. min. max. min. max.
`
`Unit
`
`Note
`
`Refresh Cycle
`Self Refresh Exit Time
`Refresh Period (4096 cycles)
`
`tSREX
`tREF
`
`10
`64
`
`Read Cycle
`Data Out Hold Time
`Data Out to Low Impedance
`Time
`Data Out to High Impedance
`Time
`DQM Data Out Disable
`Latency
`
`tOH
`tLZ
`
`tHZ
`
`tDQZ
`
`Write Cycle
`Data input to Precharge (write
`recovery)
`Data In to Active/refresh
`DQM Write Mask Latency
`
`tDPL
`
`tDAL
`tDQW
`
`3
`0
`
`3
`
`2
`
`2
`
`5
`0
`
`–
`–
`
`–
`–
`
`9
`
`–
`
`–
`
`–
`–
`
`10
`64
`
`3
`0
`
`3
`
`2
`
`2
`
`5
`0
`
`–
`–
`
`–
`–
`
`9
`
`–
`
`–
`
`–
`–
`
`10
`64
`
`ns
`–
`– ms
`
`3
`0
`
`3
`
`2
`
`2
`
`5
`0
`
`–
`–
`
`9
`
`–
`
`–
`
`–
`
`–
`
`ns
`ns
`
`ns
`
`CLK
`
`CLK
`
`CLK
`CLK
`
`9)
`
`8)
`
`4)
`
`10)
`
`11)
`
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`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`Notes:
`
`1. The specified values are valid when addresses are changed no more than once during tck(min.)
`and when No Operation commands are registered on every rising clock edge during tRC(min).
`Values are shown per module bank.
`2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
`3. All AC characteristics are shown for device level.
`An initial pause of 100m s is required after power-up, then a Precharge All Banks command must
`be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
`begin.
`4. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover
`point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns
`with the AC output load circuit show. Specified tac and toh parameters are measured with a 50
`pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
`0.8V and 2.0 V.
`
`tCH
`
`2.4 V
`
`0.4 V
`
`tT
`
`CLOCK
`
`tCL
`
`tSETUP tHOLD
`
`INPUT
`
`1.4V
`
`+ 1.4 V
`
`50 Ohm
`
`50 pF
`
`Z=50 Ohm
`
`I/O
`
`tAC
`
`tLZ
`
`tAC
`
`tOH
`
`OUTPUT
`
`I/O
`
`50 pF
`
`1.4V
`
`Measurement conditions for
`tac and toh
`
`tHZ
`
`fig.1
`5. If clock rising time is longer than 1ns, a time (t T/2 -0.5) ns has to be added to this parameter.
`6. Rated at 1.5 V
`7. If tT is longen than 1 ns, a time (t T -1) ns has to be added to this parameter.
`8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
`commands must be given to “wake-up“ the device.
`9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
`CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
`once the Self Refresh Exit command is registered.
`10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
`levels.
`11.tDAL is equivalent to tDPL + tRP.
`
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`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module
`configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence
`detect protocol ( I2C synchronous 2-wire bus)
`
`SPD-Table:
`
`Byte#
`
`Description
`
`SPD Entry Value
`
`0
`1
`2
`3
`4
`
`5
`6
`7
`8
`9
`10
`11
`12
`
`Number of SPD bytes
`Total bytes in Serial PD
`Memory Type
`Number of Row Addresses (without BS bits)
`Number of Column Addresses
` (for x8 SDRAM)
`Number of DIMM Banks
`Module Data Width
`Module Data Width (cont’d)
`Module Interface Levels
`SDRAM Cycle Time at CL=3
`SDRAM Access time from Clock at CL=3
`Dimm Config (Error Det/Corr.)
`Refresh Rate/Type
`
`SDRAM width, Primary
`13
`Error Checking SDRAM data width
`14
`15 Minimum clock delay for back-to-back ran-
`dom column address
`Burst Length supported
`16
`Number of SDRAM banks
`17
`Supported CAS Latencies
`18
`CS Latencies
`19
`20 WE Latencies
`21
`SDRAM DIMM module attributes
`
`SDRAM Device Attributes :General
`22
`23 Min. Clock Cycle Time at CAS Latency = 2
`24 Max. data access time from Clock for CL=2
`25 Minimum Clock Cycle Time at CL = 1
`26 Maximum Data Access Time from Clock at
`CL=1
`27 Minimum Row Precharge Time
`28 Minimum Row Active to Row Active delay
`tRRD
`
`128
`256
`SDRAM
`11
`9
`
`1 / 2
`64 / 72
`0
`LVTTL
`10.0 ns
` 6.0 ns
`none / ECC
`Self-Refresh,
`15.6m s
`x8
`n/a / x8
`tccd = 1 CLK
`
`1, 2, 4, 8 & full page
`2
`CAS lat. = 2 & 3
`CS latency = 0
`Write latency = 0
`non buffered/non
`reg.
`Vcc tol +/- 10%
`10.0 ns
`6.0 ns
`not supported
`not supported
`
`20 ns
`16 ns
`
`Hex
`2Mx72
`4Mx64
`-8
`-8
`80
`80
`08
`08
`04
`04
`0B
`0B
`09
`09
`
`4Mx72
`-8
`80
`08
`04
`0B
`09
`
`2Mx64
`-8
`80
`08
`04
`0B
`09
`
`01
`40
`00
`01
`A0
`60
`00
`80
`
`08
`00
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`60
`FF
`FF
`
`14
`10
`
`01
`48
`00
`01
`A0
`60
`02
`80
`
`08
`08
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`60
`FF
`FF
`
`14
`10
`
`02
`40
`00
`01
`A0
`60
`00
`80
`
`08
`00
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`60
`FF
`FF
`
`14
`10
`
`02
`48
`00
`01
`A0
`60
`02
`80
`
`08
`08
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`60
`FF
`FF
`
`14
`10
`
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`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`SPD-Table (cont’d):
`
`Byte#
`
`Description
`
`SPD Entry Value
`
`29 Minimum RAS to CAS delay tRCD
`30 Minimum RAS pulse width tRAS
`31 Module Bank Density (per bank)
`32
`SDRAM input setup time
`33
`SDRAM input hold time
`34
`SDRAM data input setup time
`35
`SDRAM data input hold time
`36-61 Superset information (may be used in
`future)
`SPD Revision
`62
`Checksum for bytes 0 - 62
`63
`Manufacturers information (optional)
`64-
`(FFh if not used)
`125
`126 Frequency Specification
`127 Details of 100 MHz Support
`128+ Unused storage locations
`
`20 ns
`45 ns
`16 MByte
`2 ns
`1 ns
`2 ns
`1 ns
`
`Revision 1.2
`
`100 MHz
`
`Hex
`2Mx72
`4Mx64
`-8
`-8
`14
`14
`2D
`2D
`04
`04
`20
`20
`10
`10
`20
`20
`10
`10
`FF
`FF
`
`4Mx72
`-8
`14
`2D
`04
`20
`10
`20
`10
`FF
`
`2Mx64
`-8
`14
`2D
`04
`20
`10
`20
`10
`FF
`
`12
`C9
`XX
`
`64
`AF
`FF
`
`12
`DB
`XX
`
`64
`AF
`FF
`
`12
`CA
`XX
`
`64
`FF
`FF
`
`12
`DC
`XX
`
`64
`FF
`FF
`
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`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`SPD-Table:
`
`Byte#
`
`Description
`
`SPD Entry Value
`
`0
`1
`2
`3
`4
`
`5
`6
`7
`8
`9
`10
`11
`12
`
`Number of SPD bytes
`Total bytes in Serial PD
`Memory Type
`Number of Row Addresses (without BS bits)
`Number of Column Addresses
` (for x8 SDRAM)
`Number of DIMM Banks
`Module Data Width
`Module Data Width (cont’d)
`Module Interface Levels
`SDRAM Cycle Time at CL=3
`SDRAM Access time from Clock at CL=3
`Dimm Config (Error Det/Corr.)
`Refresh Rate/Type
`
`SDRAM width, Primary
`13
`Error Checking SDRAM data width
`14
`15 Minimum clock delay for back-to-back ran-
`dom column address
`Burst Length supported
`16
`Number of SDRAM banks
`17
`Supported CAS Latencies
`18
`CS Latencies
`19
`20 WE Latencies
`21
`SDRAM DIMM module attributes
`
`SDRAM Device Attributes :General
`22
`23 Min. Clock Cycle Time at CAS Latency = 2
`24 Max. data access time from Clock for CL=2
`25 Minimum Clock Cycle Time at CL = 1
`26 Maximum Data Access Time from Clock at
`CL=1
`27 Minimum Row Precharge Time
`28 Minimum Row Active to Row Active delay
`tRRD
`
`128
`256
`SDRAM
`11
`9
`
`1 / 2
`64 / 72
`0
`LVTTL
`10.0 ns
` 6.0 ns
`none / ECC
`Self-Refresh,
`15.6m s
`x8
`n/a / x8
`tccd = 1 CLK
`
`1, 2, 4, 8 & full page
`2
`CAS lat. = 2 & 3
`CS latency = 0
`Write latency = 0
`non buffered/non
`reg.
`Vcc tol +/- 10%
`10.0 ns
`7.0 ns
`not supported
`not supported
`
`30 ns
`20 ns
`
`Hex
`2Mx72
`4Mx64
`-8-3
`-8-3
`80
`80
`08
`08
`04
`04
`0B
`0B
`09
`09
`
`2Mx64
`-8-3
`80
`08
`04
`0B
`09
`
`4Mx72
`-8-3
`80
`08
`04
`0B
`09
`
`01
`40
`00
`01
`A0
`60
`00
`80
`
`08
`00
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`70
`FF
`FF
`
`1E
`14
`
`01
`48
`00
`01
`A0
`60
`02
`80
`
`08
`08
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`70
`FF
`FF
`
`1E
`14
`
`02
`40
`00
`01
`A0
`60
`00
`80
`
`08
`00
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`70
`FF
`FF
`
`1E
`14
`
`02
`48
`00
`01
`A0
`60
`02
`80
`
`08
`08
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`A0
`70
`FF
`FF
`
`1E
`14
`
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`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`SPD-Table (cont’d):
`
`Byte#
`
`Description
`
`SPD Entry Value
`
`29 Minimum RAS to CAS delay tRCD
`30 Minimum RAS pulse width tRAS
`31 Module Bank Density (per bank)
`32
`SDRAM input setup time
`33
`SDRAM input hold time
`34
`SDRAM data input setup time
`35
`SDRAM data input hold time
`36-61 Superset information (may be used in
`future)
`SPD Revision
`62
`Checksum for bytes 0 - 62
`63
`Manufacturers information (optional)
`64-
`(FFh if not used)
`125
`126 Frequency Specification
`127 Details of 100 MHz Support
`128+ Unused storage locations
`
`20 ns
`45 ns
`16 MByte
`2 ns
`1 ns
`2 ns
`1 ns
`
`Revision 1.2
`
`100 MHz
`
`Hex
`2Mx72
`4Mx64
`-8-3
`-8-3
`14
`14
`2D
`2D
`04
`04
`20
`20
`10
`10
`20
`20
`10
`10
`FF
`FF
`
`2Mx64
`-8-3
`14
`2D
`04
`20
`10
`20
`10
`FF
`
`4Mx72
`-8-3
`14
`2D
`04
`20
`10
`20
`10
`FF
`
`12
`E7
`XX
`
`64
`AD
`FF
`
`12
`F9
`XX
`
`64
`AD
`FF
`
`12
`E8
`XX
`
`64
`FD
`FF
`
`12
`FA
`XX
`
`64
`FD
`FF
`
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`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`SPD-Table:
`
`Byte#
`
`Description
`
`SPD Entry Value
`
`0
`1
`2
`3
`4
`
`5
`6
`7
`8
`9
`10
`11
`12
`
`Number of SPD bytes
`Total bytes in Serial PD
`Memory Type
`Number of Row Addresses (without BS bits)
`Number of Column Addresses
` (for x8 SDRAM)
`Number of DIMM Banks
`Module Data Width
`Module Data Width (cont’d)
`Module Interface Levels
`SDRAM Cycle Time at CL=3
`SDRAM Access time from Clock at CL=3
`Dimm Config (Error Det/Corr.)
`Refresh Rate/Type
`
`SDRAM width, Primary
`13
`Error Checking SDRAM data width
`14
`15 Minimum clock delay for back-to-back ran-
`dom column address
`Burst Length supported
`16
`Number of SDRAM banks
`17
`Supported CAS Latencies
`18
`CS Latencies
`19
`20 WE Latencies
`21
`SDRAM DIMM module attributes
`
`SDRAM Device Attributes :General
`22
`23 Min. Clock Cycle Time at CAS Latency = 2
`24 Max. data access time from Clock for CL=2
`25 Minimum Clock Cycle Time at CL = 1
`26 Maximum Data Access Time from Clock at
`CL=1
`27 Minimum Row Precharge Time
`28 Minimum Row Active to Row Active delay
`tRRD
`
`128
`256
`SDRAM
`11
`9
`
`1 / 2
`64 / 72
`0
`LVTTL
`10.0 ns
` 8.0 ns
`none / ECC
`Self-Refresh,
`15.6m s
`x8
`n/a / x8
`tccd = 1 CLK
`
`1, 2, 4, 8 & full page
`2
`CAS lat. = 2 & 3
`CS latency = 0
`Write latency = 0
`non buffered/non
`reg.
`Vcc tol +/- 10%
`15.0 ns
`9.0 ns
`not supported
`not supported
`
`30 ns
`20 ns
`
`Hex
`2Mx72
`4Mx64
`-10
`-10
`80
`80
`08
`08
`04
`04
`0B
`0B
`09
`09
`
`4Mx72
`-10
`80
`08
`04
`0B
`09
`
`2Mx64
`-10
`80
`08
`04
`0B
`09
`
`01
`40
`00
`01
`A0
`80
`00
`80
`
`08
`00
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`F0
`90
`FF
`FF
`
`1E
`14
`
`01
`48
`00
`01
`A0
`80
`02
`80
`
`08
`08
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`F0
`90
`FF
`FF
`
`1E
`14
`
`02
`40
`00
`01
`A0
`80
`00
`80
`
`08
`00
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`F0
`90
`FF
`FF
`
`1E
`14
`
`02
`48
`00
`01
`A0
`80
`02
`80
`
`08
`08
`01
`
`8F
`02
`06
`01
`01
`00
`
`06
`F0
`90
`FF
`FF
`
`1E
`14
`
`Semiconductor Group
`
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`IPR2022-00996
`
`

`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`SPD-Table (cont’d):
`
`Byte#
`
`Description
`
`SPD Entry Value
`
`29 Minimum RAS to CAS delay tRCD
`30 Minimum RAS pulse width tRAS
`31 Module Bank Density (per bank)
`32
`SDRAM input setup time
`33
`SDRAM input hold time
`34
`SDRAM data input setup time
`35
`SDRAM data input hold time
`36-61 Superset information (may be used in
`future)
`SPD Revision
`62
`Checksum for bytes 0 - 62
`63
`Manufacturers information (optional)
`64-
`(FFh if not used)
`125
`126 Frequency Specification
`127 Details
`128+ Unused storage locations
`
`30 ns
`45 ns
`16 MByte
`3 ns
`1 ns
`3 ns
`1 ns
`
`Revision 1.2
`
`66 MHz
`
`Hex
`2Mx72
`4Mx64
`-10
`-10
`1E
`1E
`2D
`2D
`04
`04
`30
`30
`10
`10
`30
`30
`10
`10
`FF
`FF
`
`4Mx72
`-10
`1E
`2D
`04
`30
`10
`30
`10
`FF
`
`2Mx64
`-10
`1E
`2D
`04
`30
`10
`30
`10
`FF
`
`12
`A1
`XX
`
`66
`AF
`FF
`
`12
`B3
`XX
`
`66
`AF
`FF
`
`12
`A2
`XX
`
`66
`FF
`FF
`
`12
`B4
`XX
`
`66
`FF
`FF
`
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`

`

`HYS64(72)V2200/4220GU-8/-10
`SDRAM-Modules
`
`4,0
`
`31.75
`
`17,78
`
`L-DIM-168-29
`SDRAM DIMM Module package
`
`133,35
`
`127,35
`
`x)
`
`84
`
`168
`
`1
`
`10 11
`
`40
`
`41
`
`42,18
`
`66,68
`
`3,0
`
`A
`
`85
`
`94 95
`
`C
`
`B
`
`124
`
`125
`
`x)
`
`D
`
`1,0 + 0.5
`-
`
`+-0,2 0,15
`
`2,54 min.1
`
`,27
`
`2,0
`
`Detail B
`
`Detail C
`
`DM168-29.WMF
`
`x) on ECC modules only
`
`6,35
`
`6,35
`
`3,125
`
`2,0
`
`3,125
`
`Detail A
`2.26
`
`RADIUS
`
`1.27 + 0.10
`
`4.45
`
`8.25
`
`Detail D
`
`Semiconductor Group
`
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`
`

`

`This datasheet has been download from:
`
`www.datasheetcatalog.com
`
`Datasheets for electronics components.
`
`Netlist Ex 2015
`Samsung v Netlist
`IPR2022-00996
`
`