JEDEC Standard No. 21–C
`Page 4.20.3–1
`
`4.20.3 – 144 Pin, PC133 SDRAM Unbuffered SO–DIMM, Reference Design
`Specification
`
`PC133 SDRAM Unbuffered SO-DIMM
`Reference Design Specification
`Revision 1.02
`
`Netlist Inc.
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`Release 11
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–2
`
` Contents
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1. Product Description
`Product Family Attributes
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`3
`3
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`2. Environmental Requirements
`Absolute Maximum Ratings
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`4
`4
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3. Architecture
`Pin Description
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Input/Output Functional Description
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Unbuffered SDRAM SO-DIMM Pinout
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Block Diagram: Raw Card Version A
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Block Diagram: Raw Card Version B
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Termination for Unused Clock Signals (0 loads)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Clock Net Wiring (4 loads)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`4
`4
`5
`6
`7
`8
`9
`9
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`4. Component Details
`Pin Assignments for 64Mb and 128Mb SDRAM Planar Components
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Pin Assignments for 256Mb 54 pin SDRAM Planar Components
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Reference SDRAM Component Specifications
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`10
`10
`11
`12
`
`15
`15
`15
`16
`
`17
`17
`17
`17
`18
`19
`20
`21
`22
`23
`
`Netlist Inc.
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`5. Unbuffered SO-DIMM Details
`SDRAM Module Configurations (Reference Designs)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Gerber File Revision Matrix
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Example Raw Card Component Placement
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`6. SO-DIMM Wiring Details
`Signal Groups
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`General Net Structure Routing Guidelines
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Explanation of Net Structure Diagrams
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Data Net Structures
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Data Mask Net Structures
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Select Net Structures
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Clock Enable Net Structures
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Address/Control Net Structures
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Cross Section Recommendations
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8. Serial PD Definition
`Serial Presence Detect Data EXAMPLE
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`24
`24
`
`9. Product Label
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`26
`
`9. SO-DIMM Mechanical Specifications
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`27
`
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`

`JEDEC Standard No. 21–C
`Page 4.20.3–3
`
`1. Product Description
`
`This reference specification defines the electrical and mechanical requirements for 144-pin, 3.3 Volt, 133 MHz,
`64-bit wide, Unbuffered Synchronous DRAM Small Outline Dual In-Line Memory Modules (SDRAM SO-
`DIMMs).These SDRAM SO-DIMMs are intended for use as main memory when installed in systems such as
`mobile personal computers.
`
`Reference design examples are included which provide an initial basis for Unbuffered SO-DIMM designs. Mod-
`ifications to these reference designs are required to meet all system timing, signal integrity and thermal re-
`quirements for 133 MHz support. Other designs are acceptable, and all Unbuffered SO-DIMM implementations
`must use simulations and lab verification to ensure proper timing requirements and signal integrity in the de-
`sign.
`
`This specification largely follows the JEDEC defined 144-pin 8-Byte Unbuffered SDRAM SO-DIMM product.
`(Refer to JEDEC standard 21-C, Section 4.5.6, at www.jedec.org).
`
`Product Family Attributes
`
`SO-DIMM Organization
`
`SO-DIMM Dimensions (nominal)
`
`Pin Count
`
`SDRAMs Supported
`
`Capacity
`
`Serial PD
`
`Voltage Options
`
`Interface
`
`144
`
`64 Mb, 128 Mb, 256 Mb
`
`32 MB, 64 MB, 128 MB, 256 MB
`
`Consistent with JEDEC Rev. 2.0
`3.3 volt (VDD/VDDQ)
`LVTTL
`
`x 64
`
`67.6 mm (2.66”) x 25.40 mm (1.0”) to x 31.75 mm (1.25”)
`
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`

`JEDEC Standard No. 21–C
`Page 4.20.3–4
`
`2. Environmental Requirements
`
`PC133 SDRAM Unbuffered SO-DIMMs are intended for use in mobile computing environments that have lim-
`ited capacity for heat dissipation.
`
`Absolute Maximum Ratings
`
`Symbol
`TOPR
`HOPR
`TSTG
`HSTG
`
`Parameter
`Operating Temperature (ambient)
`Operating Humidity (relative)
`Storage Temperature
`Storage Humidity (without condensation)
`Barometric Pressure (operating & storage)
`
`Rating
` 0 to +65
` 10 to 90
`-50 to +100
` 5 to 95
` 105 to 69
`
`Units
`∞C
`%
`∞C
`%
`kPa
`
`Notes
`1
`1
`1
`1
`1, 2
`
`1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
`operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
`may affect reliability.
`2. Up to 9850 ft.
`
`Netlist Inc.
`
` DQ(0:63)
`DQMB(0:
`7)
`VDD
`VSS
`SCL
` SDA
`
` Data Input/Output
`
` Data Mask
`
`64
`
`8
`
`18
`Power (3.3 V)
`18
` Ground
`1
`Serial Presence Detect Clock Input
`Serial Presence Detect Data Input/Output 1
`
`2
`
`2
`
`1
`1
`1
`2
`
`13
`
`1
`
`2
`
`3. Architecture
`
`Pin Description
`
`CK(0:1)
`
` Clock Inputs
`
`CKE(0:1) Clock Enables
`
`RAS
`CAS
`WE
`S(0:1)
`A(0:9,11:13
`)
`
` Row Address Strobe
`Column Address Strobe
` Write Enable
` Chip Selects
`
`Address Inputs
`
`A10/AP
`
`Address Input/Autoprecharge
`
`BA0-BA1
`
` SDRAM Bank Address
`
` NC
`
` No Connect
`
`DU
`
`Don’t Use - leave as NC
`
`8
`
`1
`14
`4
`
`Total:
`
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`

`JEDEC Standard No. 21–C
`Page 4.20.3–5
`
`Input/Output Functional Description
`
`Symbol
`
`Type
`
`CK0 - CK1
`
`Input
`
`CKE0,1
`
`Input
`
`S0 - S1
`
`Input
`
`RAS, CAS
`WE
`
`Input
`
`BA0, BA1
`
`Input
`
`Polarity
`Positive
`Edge
`
`Active
`High
`
`Active
`Low
`
`Active
`Low
`
`—
`
`A0 - A9,
`A11-A13
`A10/AP
`
`Input
`
`—
`
`DQ0 - DQ63
`
`DQMB0 -
`DQMB7
`
`VDD, VSS
`
`SDA
`
`Input
`Output
`
`Input
`
`Supply
`Input
`Output
`
`SCL
`
`Input
`
`—
`
`Active
`High
`
`—
`
`—
`
`Function
`
`The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their
`associated clock.
`
`Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
`ing the clocks, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
`
`Enables the associated SDRAM command decoder when low and disables the command decoder
`when high. When the command decoder is disabled, new commands are ignored but previous
`operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1.
`
`When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to
`be executed by the SDRAM.
`
`Selects which SDRAM bank of four is activated.
`During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when
`sampled at the rising clock edge.
`During a Read or Write command cycle, A0-A11 defines the column address (CA0-CA11) when
`sampled at the rising clock edge. In addition to the column address, AP is used to invoke autopre-
`charge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected
`and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled.
`During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which
`bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or
`BA1. If AP is low, then BA0 and BA1 are used to define which bank to precharge.
`
`Netlist Inc.
`
`Data Bit Input/Output pins.
`
`The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high im-
`pedance state when sampled high. In Read mode, DQMB controls the output buffers like an output
`enable. In Write mode, DQMB operates as a byte mask by allowing input data to be written if it is
`low but blocks the write operation if it is high.
`Power and ground for the module.
`
`This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be
`connected to VDD to act as a pull up.
`This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
`from SCL to VDD to act as a pull up.
`
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`

`JEDEC Standard No. 21–C
`Page 4.20.3–6
`
`. U
`
`nbuffered SDRAM SO-DIMM Pinout
`
`Pin
`#
`
`Front
`Side
`
`Pin
`#
`
`Back
`Side
`
`1
`
`3
`
`5
`
`VSS
`
`DQ0
`
`DQ1
`
`2
`
`4
`
`6
`
`VSS
`
`DQ32
`
`DQ33
`
`41
`
`DQ10
`
`42
`
`DQ42
`
`77
`
`NC
`
`DQ11
`
`44
`
`DQ43
`
`79
`
`NC
`
`Pi
`n#
`
`37
`
`39
`
`Front
`Side
`
`Pin
`#
`
`Back
`Side
`
`DQ8
`
`DQ9
`
`38
`
`40
`
`DQ40
`
`DQ41
`
`Pi
`n#
`
`73
`
`75
`
`NU
`
`VSS
`
`Front
`Side
`
`Pin
`#
`
`Back
`Side
`
`Pi
`n #
`
`Front
`Side
`
`Pin
`#
`
`Back
`Side
`
`74
`
`76
`
`78
`
`80
`
`CK1
`
`109
`
`A9
`
`110
`
`BA1
`
`VSS
`
`111
`
`A10/AP
`
`112
`
`A11
`
`NC
`
`113
`
`VDD
`
`114
`
`VDD
`
`NC
`
`115
`
`DQMB2
`
`116
`
`DQMB6
`
`7
`
`9
`
`11
`
`13
`
`15
`
`DQ2
`
`DQ3
`
`VDD
`
`DQ4
`
`DQ5
`
`8
`
`10
`
`12
`
`14
`
`16
`
`DQ34
`
`DQ35
`
`VDD
`
`43
`
`45
`
`VDD
`
`46
`
`VDD
`
`81
`
`VDD
`
`82
`
`VDD
`
`117
`
`DQMB3
`
`118
`
`DQMB7
`
`47
`
`DQ12
`
`48
`
`DQ44
`
`83
`
`DQ16
`
`84
`
`DQ48
`
`119
`
`VSS
`
`120
`
`VSS
`
`DQ36
`
`49
`
`DQ13
`
`50
`
`DQ45
`
`85
`
`DQ17
`
`86
`
`DQ49
`
`121
`
`DQ24
`
`122
`
`DQ56
`
`DQ37
`
`51
`
`DQ14
`
`52
`
`DQ46
`
`87
`
`DQ18
`
`88
`
`DQ50
`
`123
`
`DQ25
`
`124
`
`DQ57
`
`DQ47
`
`89
`
`DQ19
`
`90
`
`DQ51
`
`125
`
`DQ26
`
`126
`
`DQ58
`
`17
`
`19
`
`21
`
`23
`
`25
`
`DQ38
`
`53
`
`DQ15
`
`54
`
`DQ6
`
`DQ7
`
`VSS
`
`18
`
`20
`
`22
`
`DQ39
`
`VSS
`
`DQMB0
`
`24
`
`DQMB4
`
`DQMB1
`
`26
`
`DQMB5
`
`55
`
`57
`
`59
`
`61
`
`VSS
`
`NC
`
`NC
`
`56
`
`58
`
`60
`
`VSS
`
`91
`
`VSS
`
`92
`
`VSS
`
`127
`
`DQ27
`
`128
`
`DQ59
`
`NC
`
`93
`
`DQ20
`
`94
`
`DQ52
`
`129
`
`VDD
`
`130
`
`VDD
`
`NC
`
`95
`
`DQ21
`
`96
`
`DQ53
`
`131
`
`DQ28
`
`132
`
`DQ60
`
`CK0
`
`62
`
`CKE0
`
`97
`
`DQ22
`
`98
`
`DQ54
`
`133
`
`DQ29
`
`134
`
`DQ61
`
`DQ23
`
`100
`
`DQ55
`
`135
`
`DQ30
`
`136
`
`DQ62
`
`Netlist Inc.
`
`VDD
`
`99
`
`CAS
`
`101
`
`VDD
`
`102
`
`VDD
`
`137
`
`CKE1
`
`103
`
`A6
`
`104
`
`A7
`
`139
`
`A12
`
`105
`
`A8
`
`106
`
`BA0
`
`141
`
`DQ31
`
`138
`
`DQ63
`
`VSS
`
`140
`
`VSS
`
`SDA
`
`142
`
`SCL
`
`VDD
`
`A0
`
`A1
`
`A2
`
`VSS
`
`27
`
`29
`
`31
`
`33
`
`35
`
`Note:
`
`28
`
`30
`
`32
`
`34
`
`36
`
`VDD
`
`A3
`
`A4
`
`A5
`
`VSS
`
`63
`
`65
`
`67
`
`69
`
`71
`
`VDD
`
`RAS
`
`WE
`
`S0
`
`S1
`
`64
`
`66
`
`68
`
`70
`
`72
`
`A13
`
`107
`
`VSS
`
`108
`
`VSS
`
`143
`
`VDD
`
`144
`
`VDD
`
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`

`JEDEC Standard No. 21–C
`Page 4.20.3–7
`
`Block Diagram: Raw Card Version A
`(Populated as 1 physical bank of x16 SDRAMs)
`
`DQMB4
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`4 loads
`
`0 loads
`
`SDRAMs D0-D3
`
`SDRAMs D0-D3
`
`SDRAMs D0-D3
`
`SDRAMs D0-D3
`
`SDRAMs D0-D3
`
`SDRAMs D0-D3
`
`SDRAMs D0-D3, SPD
`
`SDRAMs D0-D3, SPD
`
`#Unless otherwise noted, resistor values are 10 Ohms.
`
`Serial Presence Detect (SPD)
`
`SCL
`
`WP
`A0
`
`A1
`
`A2
`
`SDA
`
`Note: DQ wiring may differ from that described
`in this drawing; however DQ/DQMB
`relationships are maintained as shown.
`
`Release 11
`
`Revision 1.02
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
`CS
`
`D2
`
`CS
`
`D3
`
`DQMB5
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQMB6
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQMB7
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`Netlist Inc.
`
`CS
`
`D0
`
`CS
`
`D1
`
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`DQMB0
`
`DQMB1
`
`DQMB2
`
`DQMB3
`
`S0
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`CK0
`
`CK1
`
`BA0-BAn
`
`A0-An
`
`RAS
`
`CAS
`
`WE
`
`CKE0
`
`VDD
`
`VSS
`
`Netlist Ex 2013-p. 7
`Samsung v Netlist
`IPR2022-00996
`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–8
`
`Block Diagram: Raw Card Version B
`(Populated as 2 physical banks of x16 SDRAMs)
`
`DQMB4
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQMB0
`
`DQMB1
`
`DQMB2
`
`DQMB3
`
`S1
`S0
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D0
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D1
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D4
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D5
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`Netlist Inc.
`
`DQMB5
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQMB6
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQMB7
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`D2
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D3
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`D6
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`CS
`LDQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D7
`UDQM
`I/O 8
`I/O 9
`I/O 10
`I/O 11
`I/O 12
`I/O 13
`I/O 14
`I/O 15
`
`CK0
`
`CK1
`
`BA0-BAn
`
`A0-An
`
`RAS
`
`CAS
`
`WE
`
`CKE0
`
`CKE1
`
`VDD
`
`VSS
`
`4 loads
`
`4 loads
`
`SDRAMs D0-D7
`
`SDRAMs D0-D7
`
`SDRAMs D0-D7
`
`SDRAMs D0-D7
`
`SDRAMs D0-D7
`
`SDRAMs D0-D3
`
`SDRAMs D4-D7
`
`SDRAMs D0-D7, SPD
`
`SDRAMs D0-D7, SPD
`
`#Unless otherwise noted, resistor values are 10 Ohms.
`
`Serial Presence Detect (SPD)
`
`SCL
`
`WP
`A0
`
`A1
`
`A2
`
`SDA
`
`Note: DQ wiring may differ from that described
`in this drawing; however DQ/DQMB
`relationships are maintained as shown.
`
`Revision 1.02
`
`Release 11
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
`Netlist Ex 2013-p. 8
`Samsung v Netlist
`IPR2022-00996
`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–9
`
`Termination for Unused Clock Signals (0 loads)
`
`TL2
`
`TL3
`
`TL4
`
`TL3
`
`TL4
`
`Unused
`CK
`
`10 Ohm
`
`10 pF
`
`Clock Net Wiring (4 loads)
`
`TL0
`
`TL1
`
`SO-DIMM
`Connector
`
`Clock Routing Trace Lengths:
`
`SDRAM
`Pin
`
`SDRAM
`Pin
`
`SDRAM
`Pin
`
`SDRAM
`Pin
`
`TL4
`
`TL4
`
`TL2
`
`TL3
`
`TL3
`
`Netlist Inc.
`
`Release 11
`
`Revision 1.02
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
`Netlist Ex 2013-p. 9
`Samsung v Netlist
`IPR2022-00996
`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–10
`
`4. Component Details
`
`Pin Assignments for 64 Mb and 128 Mb SDRAM Planar Components
`(Top View)
`
`54
`53
`52
`51
`50
`49
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`
`VSS
`DQ15
`VSSQ
`DQ14
`DQ13
`VDDQ
`DQ12
`DQ11
`VSSQ
`DQ10
`DQ9
`VDDQ
`DQ8
`VSS
`NC
`UDQM
`CK
`CKE
`NC
`A11
`A9
`A8
`A7
`A6
`A5
`A4
`VSS
`
`Netlist Inc.
`
`1 2 3 4 5 6
`
`7 8
`
`9 1
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`
`VDD
`DQ0
`VDDQ
`DQ1
`DQ2
`VSSQ
`DQ3
`DQ4
`VDDQ
`DQ5
`DQ6
`VSSQ
`DQ7
`VDD
`LDQM
`WE
`CAS
`RAS
`CS
`BA0
`BA1
`A10/AP
`A0
`A1
`A2
`A3
`VDD
`
`54-pin Plastic
`TSOP(II) 400 mil
`1 Mb x 16 I/O x 4 Bank
`2 Mb x 16 I/O x 4 Bank
`
`Note: Raw Card Versions ‘A’ and ‘B’ support the use of the above SDRAM pin assignments.
`These pin assignments are consistent with the JEDEC standard package definition.
`
`Revision 1.02
`
`Release 11
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
`Netlist Ex 2013-p. 10
`Samsung v Netlist
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`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–11
`
`Pin Assignments for 256 Mb and 512 Mb 54 pin SDRAM Planar Components
`(Top View)
`
`54
`53
`52
`51
`50
`49
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`
`VSS
`DQ15
`VSSQ
`DQ14
`DQ13
`VDDQ
`DQ12
`DQ11
`VSSQ
`DQ10
`DQ9
`VDDQ
`DQ8
`VSS
`NC
`UDQM
`CK
`CKE
`A12
`A11
`A9
`A8
`A7
`A6
`A5
`A4
`VSS
`
`Netlist Inc.
`
`1 2 3 4 5 6
`
`7 8
`
`9 1
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`
`VDD
`DQ0
`VDDQ
`DQ1
`DQ2
`VSSQ
`DQ3
`DQ4
`VDDQ
`DQ5
`DQ6
`VSSQ
`DQ7
`VDD
`LDQM
`WE
`CAS
`RAS
`CS
`BS0
`BS1
`A10/AP
`A0
`A1
`A2
`A3
`VDD
`
`54-pin Plastic
`TSOP(II) 400mil
`
`4Mb x 16 I/O x 4 Bank
`8Mb x 16 I/O x 4 Bank
`
`Note: Raw Card Versions ’A’ and ‘B’ supports the use of the above SDRAM
`pin assignment. This pin assignment is consistent with the JEDEC
`standard package.
`
`Release 11
`
`Revision 1.02
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
`Netlist Ex 2013-p. 11
`Samsung v Netlist
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`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–12
`
`Reference SDRAM Component Specifications
`The 133 MHz SDRAM components used with this SO-DIMM design specification are intended to be consistent
`with PC133 SDRAM specifications prevalent in the industry. The following is for reference only..
`DC Electrical Characteristics
`
`Parameter
`
`Supply Voltage
`I/O Supply Voltage
`Input Leakage Current
`(0 < VIN < VDDQ)
`Icc Low Power
`(CKE low, all banks closed)
`
`Output High Voltage
`(IOH = -4 mA)
`Output Low Voltage
`(IOL = 4 mA)
`Input Pin Capacitance
`(@1 MHz, 25 _C TA, 1.4 V bias, 200 mV swing, VDD = 3.3 V)
`
`I/O Pin Capacitance(@1 MHz, 25 _C TA, 1.4 V bias, 200 mV swing, VDD =
`3.3 V)
`
`Pin Capacitance
`(@1 MHz, 25 _C TA, 1.4 V bias, 200 mV swing, VDD = 3.3 V)
`Pin Inductance
`Ambient Temperature
`(No Airflow)
`
`Min
`3.0
`3. 0
`
`-10
`
`-
`
`2.4
`
`-
`
`2.5
`
`4.0
`
`2.5
`
`0
`
`Notes
`
`1, 2
`
`3
`
`4
`
`5
`
`Max
`3.6
`3.6
`
`+1 0
`
`2
`
`-
`
`0.4
`
`3.8
`
`6.5
`
`3.5
`
`10
`
`65
`
`Units
`V
`V
`
`mA
`
`ma
`
`V
`
`V
`
`pF
`
`pF
`
`pF
`
`nH
`
`∞C
`
`Symbol
`VDD
`VDDQ
`
`Iil
`
`ICC6
`
`VOH
`
`VOL
`
`CIN
`
`CI/O
`
`CCK
`
`LPIN
`
`TA
`
`Netlist Inc.
`
`1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
`2. No Activate or Precharge currents should be included in the Iccac value.
`3. Target 3.1 pF
`4. Target 4.8 pF
`5. Target 3.0 pF
`
`Revision 1.02
`
`Release 11
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
`Netlist Ex 2013-p. 12
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`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–13
`
`AC Timing Parameters
`(TA = 0-65 ∞C; VDD = 3.0 V - 3.6 V; CL = 2, 3) (Part <$tblsheetnum> of <$tblsheetcount>)
`Speed Grade
`Speed Grade
`100MHz
`133MHz
`
`
`
`SymbolSymbol
`
`
`
`ParameterParameter
`
`
`
`UnitsUnits
`
`
`
`NotesNotes
`
`Clock Period
`Clock High Time
`Rated @1.5V
`
`Clock Low Time
`
`
`
`IInput Setup Timest S t Ti
`
`
`
`
`
`
`
`IInput Hold Timest H ld Ti
`
`
`
`Output Valid From Clock
`
`Output Hold From Clock
`Rated @ 50 pF (1.8 ns @ 0 pf)
`
`Max
`
`Min
`10
`
`3
`
`3
`2
`2
`1
`1
`
`3
`
`6.0
`(tco =
`5.2)
`
`Address/ Command & CKE
`Data
`Address/Command & CKE
`Data
`CAS Latency = 2 or 3,
`LVTTL levels, Rated @ 50 pF
`all outputs switching
`
`tCK
`
`tCH
`
`tCL
`
`
`
`ttIS
`
`
`
`ttIH
`
`tAC
`
`tOH
`
`Netlist Inc.
`
`RAS to RAS Bank Activate Delay
`
`Output Valid to Z
`CAS to CAS Delay
`CAS Bank Delay
`CKE to Clock Disable
`RAS Precharge Time
`RAS Active Time
`Activate to Command Delay (RAS to CAS Delay)
`
`tOHZ
`tCCD
`tCBD
`tCKE
`tRP
`tRAS
`tRCD
`tRRD
`RAS Cycle Time
`tRC
`DQM to Input Data Delay
`tDQD
`tDWD Write Cmd. to Input Data Delay
`Mode Register set to Active delay
`tMRD
`tROH
`Precharge to O/P in High Z
`tDQZ
`DQM to Data in High Z for read
`tDQM
`DQM to Data mask for write
`tDPL
`Data-in to PRE Command Period
`tDAL
`Data-in to ACT (PRE) Command period (Auto precharge)
`tSB
`Power Down Mode Entry
`tSRX
`Self Refresh Exit Time
`tPDE
`Power Down Exit Set up Time
`tCKSTP Clock Stop During Self Refresh or Power Down
`Refresh Period
`tREF
`tRFC
`Row Refresh Cycle Time
`
`9
`
`3
`1
`1
`1
`20
`50
`20
`
`20
`
`70
`0
`0
`3
`
`CL
`
`1
`
`64
`
`2
`0
`20
`5
`
`10
`1
`200
`
`80.0
`
`Max
`
`5.4
`(tco =
`4.6)
`
`7
`
`CL
`
`1
`
`64
`
`Min
`7.5
`
`2.5
`
`2.5
`1.5
`1.5
`0.8
`0.8
`
`2.7
`
`2.7
`1
` 1
`1
`20
`45
`20
`
`15
`
`67.5
`0
`0
`3
`
`2
`0
`15
`5
`
`10
`1
`200
`
`75.0
`
`ns
`
`ns
`
`ns
`ns
`ns
`ns
`ns
`
`ns
`
`ns
`
`ns
`tCK
`tCK
`tCK
`ns
`ns
`ns
`
`ns
`
`ns
`tCK
`tCK
`tCK
`tCK
`tCK
`tCK
`ns
`tCK
`tCK
`ns
`tCK
`tCK
`ms
`ns
`
`1
`
`2
`
`3
`
`4
`5
`6
`7
`
`1. Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
`2. CL = CAS Latency
`3. Data Masked on the same clock
`4. Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
`5. Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
`6. If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
`7. For 64 Mb and 128 Mb SDRAM technology, 4096 refresh cycles. For 256 Mb SDRAM technology, 8192 refresh cycles.
`
`Release 11
`
`Revision 1.02
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
`Netlist Ex 2013-p. 13
`Samsung v Netlist
`IPR2022-00996
`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–14
`
`5. Unbuffered SO-DIMM Details
`
`SDRAM Module Configurations (Reference Designs)
`
`Raw
`Card
`Version
`A
`B
`A
`B
`A
`B
`A
`B
`
` SO-DIMM
`Capacity
`
`32 MB
`64 MB
`64 MB
`128 MB
`128 MB
`256 MB
`256 MB
`512 MB
`
`SO-DIMM
`Organiza-
`tion
`4MX64
`8Mx64
`8Mx64
`16Mx64
`16Mx64
`32Mx64
`32Mx64
`64Mx64
`
`SDRAM
`Density
`
`64 Mb
`64 Mb
`128 Mb
`128 Mb
`256 Mb
`256 Mb
`512 Mb
`512 Mb
`
`SDRAM
`Organiza-
`tion
`4M X 16
`4M x 16
`8M x 16
`8M x 16
`16M x 16
`16M x 16
`32M x 16
`32M x 16
`
`# of
`SDRAM
`s
`4
`8
`4
`8
`4
`8
`4
`8
`
`SDRAM
`Package Type
`
`54 lead TSOP
`54 lead TSOP
`54 lead TSOP
`54 lead TSOP
`54 lead TSOP
`54 lead TSOP
`54 lead TSOP
`54 lead TSOP
`
`# of
`Physical
`Banks
`
`# of Banks
`in SDRAM
`
`# Address bits
`row/col/banks
`
`1
`
`2
`
`1
`
`2
`
`1
`
`2
`
`1
`
`2
`
`4
`
`4
`
`4
`
`4
`
`4
`
`4
`
`4
`
`4
`
`12/8/2
`
`12/8/2
`
`12/9/2
`
`12/9/2
`
`13/9/2
`
`13/9/2
`
`13/10/2
`
`13/10/2
`
`PC133 Gerber Releases
`
`PC133 Unbuffered SO-DIMM gerbers are identical to PC100 Unbuffered SO-DIMM gerbers.
`
`Gerber Revisions
`
`Raw Card
`A
`B
`
`Revision Level
`Revision 1.0
`Revision 1.0
`
`Notes
`
`Netlist Inc.
`
`Revision 1.02
`
`Release 11
`
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`
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`
`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–15
`
`Example Raw Card Component Placement
`
`Version A, Front
`
`x16 SDRAM
`
`x16 SDRAM
`
`SPD
`
`1
`
`x16 SDRAMs
`
`59
`
`61
`
`143
`
`Netlist Inc.
`
`Version B, Front
`
`x16 SDRAMs
`
`SPD
`
`1
`
`59
`
`61
`
`143
`
`Release 11
`
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`
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–16
`
`6. SO-DIMM Wiring Details
`
`Signal Groups
`
`This reference specification categorizes SDRAM timing-critical signals into seven groups whose members
`have identical loadings and routings. The following table summarizes the signals contained in each group.
`
`.
`
`Signal Group
`
`Signals In Group
`
`Clock
`Data
`Data Mask
`Select
`Clock Enable
`Address/Control
`
`CK [1:0]
`DQ [63:0]
`DQMB[7:0]
`S [1:0]
`CKE [1:0]
`Ax, BAx, RAS, CAS, WE
`
`General Net Structure Routing Guidelines
`
`Page
`9
`18
`19
`20
`21
`22
`
`Net structures and lengths must satisfy signal quality and setup/hold time requirements for the memory inter-
`face. Net structure diagrams for each signal group are shown in the following sections. Each diagram is ac-
`companied by a trace length table that lists the minimum and maximum allowable lengths for each trace seg-
`ment and/or net.
`
`Netlist Inc.
`
`The general routing recommendations are as follows. Other stackups and layouts are possible that meet the
`electrical characteristics.
`
`• Route all signal traces except clocks using 5/5 rules, i.e., 5 mil traces and 5 mil minimum spacing between
`adjacent traces.
`• Route clocks using at least 90% of the total trace length in the inner layers.
`• Route clocks using 5/5 rules with 5 mil ground traces surrounding them. The ground traces are stitched to
`ground at 0.5” intervals, or as often as routing allows.
`• Internal signal layers and the power plane should have a ground ring around the perimeter of the board,
`stitched to ground at 0.5” intervals. The ground ring should be at least 20 mils wide where layout permits,
`but can be reduced to 10 mils when necessary.
`• No test points are required.
`
`Explanation of Net Structure Diagrams
`
`The net structure routing diagrams provide a reference design example for each raw card version. These de-
`signs provide an initial basis for unbuffered SO-DIMM designs. The diagrams should be used to determine in-
`dividual signal wiring on a SO-DIMM for any supported configuration. Only transmission lines (represented as
`cylinders and labeled with trace length designators “TL”) represent physical trace segments. All other lines are
`zero in length. To verify SO-DIMM functionality, a full simulation of all signal integrity and timing is required.
`The given net structures and trace lengths are not inclusive for all solutions.
`
`Once the net structure has been determined, the permitted trace lengths for the net structure can be read from
`the table below each net structure routing diagram. Some configurations require the use of multiple net struc-
`ture routing diagrams to account for varying load quantities on the same signal. All diagrams define one load
`as one SDRAM input. The net structure routing data in this document accurately represent reference Raw
`Card versions A and B.
`
`Revision 1.02
`
`Release 11
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–17
`
`Data Net Structures DQ[63:0]
`
`Net Structure Routing for Data
`
`SO-DIMM
`Connector
`
`TL0
`
`10 ohms
`
`TL1
`
`+ 5%
`
`TL2
`
`SDRAM Pin
`
`SDRAM Pin
`
`TL2
`For designs using two physical banks
`
`Trace Lengths for Data Net Structure
`
` TL0
`
`TL1
`
`TL2
`
`Total
`
`Min
`0.60
`
`Max
`1.00
`
`Max
`Min
`Max
`Min
`Max
`Min
`0.25
`0
`0.90
`0
`0.50
`0.10
`All distances are given in inches and should be kept within a tolerance of ± 0.01 inch
`
`Netlist Inc.
`
`Release 11
`
`Revision 1.02
`
`Downloaded by Mario Martinez (mmartinez@netlist.com) on Aug 16, 2022, 3:53 pm PDT
`
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–18
`
`Data Mask Net Structures, DQMB[7:0]
`
`Net Structure Routing for Data Mask
`
`TL0
`
`SO-DIMM
`Connector
`
`TL1
`
`SDRAM Pin
`
`SDRAM Pin
`
`TL1
`For designs using two physical banks
`
`Trace Lengths for Data Mask Net Structures
`
`TL0
`
`TL1
`
`Total
`
`Min
`Max
`Min
`Max
`Min
`1.00
`0.30
`0
`1.10
`0.75
`All distances are given in inches and should be kept within a tolerance of ± 0.01 inches.
`
`Max
`1.40
`
`Netlist Inc.
`
`Revision 1.02
`
`Release 11
`
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–19
`
`Select Net Structures CS [1:0]
`
`Net Structure Routing for Select
`
`TL3
`
`TL3
`
`SDRAM Pin
`
`SDRAM Pin
`
`TL2
`
`TL1
`
`TL0
`
`SO-DIMM
`Connector
`
`SDRAM Pin
`
`SDRAM Pin
`
`Netlist Inc.
`
`TL1
`
`TL2
`
`TL3
`
`TL3
`
`Trace Lengths for Select Net Structures
`
`TL0
`
`TL1
`
`TL2
`
`TL3
`
`Total
`
`Max
`Min
`Max
`Min
`Max
`Min
`Max
`Min
`0.35
`0.05
`0.60
`0
`0.50
`0.10
`1.10
`0.50
`All distances are given in inches and should be kept within a tolerance of ± 0.01 inches
`
`Min
`1.00
`
`Max
`2.30
`
`Release 11
`
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–20
`
`Clock Enable Net Structures, CKE [1:0]
`
`.
`
`Net Structure Routing for Clock Enable
`
`TL3
`
`SDRAM Pin
`
`TL3
`
`SDRAM Pin
`
`TL2
`
`TL1
`
`TL0
`
`SO-DIMM
`Connector
`
`TL1
`
`TL2
`
`Netlist Inc.
`
`TL3
`
`SDRAM Pin
`
`TL3
`
`SDRAM Pin
`
`Trace Lengths for Clock Enable Net Structure
`
`TL0
`
`TL1
`
`TL2
`
`TL3
`
`Total
`
`Min
`0.50
`
`Max
`1.10
`
`Min
`0
`
`Max
`0.50
`
`Min
`0
`
`Max
`1.00
`
`Min
`0.05
`
`Max
`0.35
`
`Min
`1.00
`
`Max
`2.30
`
`1. All distances are given in inches and should be kept within a tolerance of ± 0.01 inches.
`
`Revision 1.02
`
`Release 11
`
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–21
`
`Address/Control Net Structures Ax, BAx, RAS, CAS, WE
`
`Net Structure Routing for Address and Control
`
`SDRAM Pin
`
`TL3
`
`TL3
`
`SDRAM Pin
`
`TL2
`
`SDRAM Pin
`
`TL3
`
`TL3
`
`SDRAM Pin
`
`For designs using two physical banks
`
`TL1
`
`TL0
`
`SO-DIMM
`Connector
`
`SDRAM Pin
`
`TL3
`
`TL3
`
`TL1
`
`TL3
`
`SDRAM Pin
`
`Netlist Inc.
`
`For designs using two physical banks
`
`TL2
`
`TL3
`
`SDRAM Pin
`
`SDRAM Pin
`
`. T
`
`race Lengths for Address and Control Net Structures
`
`TL0
`
`Min
`0.50
`
`Max
`2.50
`
`TL1
`
`Min
`0
`
`Max
`1.10
`
`TL2
`
`TL3
`
`Total
`
`Min
`0
`
`Max
`1.00
`
`Min
`0.10
`
`Max
`0.40
`
`Min
`0.75
`
`Max
`4.00
`
`1. All distances are given in inches and should be kept within a tolerance of ± 0.01 inches.
`
`.
`
`Release 11
`
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`

`1.00 + 0.1 mm
`
`Component Types and Placement
`
`Signal Layer 3
`
`Signal Layer 4
`
`Signal Layer 6
`
`Netlist Inc.
`
`JEDEC Standard No. 21–C
`Page 4.20.3–22
`
`Cross Section Recommendations
`
`The SO-DIMM printed circuit board design uses six-layers of glass epoxy material. PCBs must contain full
`ground plane and full power plane layers. The PCB stackup must be designed with 5 mil wide traces. The re-
`quired board impedance is 55W ± 15%.
`
`Note: The PCB edge connector contacts shall be gold-plated and not chamfered.
`
`PCB Electrical Specifications
`
`Parameter
`
`Trace velocity: S0 (outer layers)
`Trace velocity: S0 (inner layers)
`Trace impedance: Z0 (all layers)
`
`Example Layer Stackup for 5 mil Traces
`
`Signal Layer 1
`
`Min
`141
`167
`47
`
` Max
`153
`180
`63
`
`Units
`ps/inch
`ps/inch
`Ohms
`
`Ground Layer 2
`
`Voltage Layer 5
`
`Components shall be surface mounted on both sides of the PCB and positioned on the PCB to meet the mini-
`mum and maximum trace lengths required for SDRAM signals. Bypass capacitors, for SDRAM devices, must
`be practically located near the device power pins.
`
`Revision 1.02
`
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`

`

`JEDEC Standard No. 21–C
`Page 4.20.3–23
`
`7. Serial PD Definition
`The Serial Presence Detect function MUST be implemented on the PC SDRAM Unbuffered SO-DIMM. The
`component used and the data