Distributed by:
`
`www.Jameco.com ✦ 1-800-831-4242
`The content and copyrights of the attached
` material are the property of its owner.
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`LP2997 DDR-II Termination Regulator
`
`June 2006
`
`LP2997
`DDR-II Termination Regulator
`General Description
`The LP2997 linear regulator is designed to meet the JEDEC
`SSTL-18 specifications for termination of DDR-II memory.
`The device contains a high-speed operational amplifier to
`provide excellent response to load transients. The output
`stage prevents shoot through while delivering 500mA con-
`tinuous current and transient peaks up to 900mA in the
`application as required for DDR-II SDRAM termination. The
`LP2997 also incorporates a VSENSE pin to provide superior
`load regulation and a VREF output as a reference for the
`chipset and DIMMs.
`An additional feature found on the LP2997 is an active low
`shutdown (SD) pin that provides Suspend To RAM (STR)
`functionality. When SD is pulled low the VTT output will
`tri-state providing a high impedance output, but, VREF will
`remain active. A power savings advantage can be obtained
`in this mode through lower quiescent current.
`
`Typical Application Circuit
`
`Features
`n Source and sink current
`n Low output voltage offset
`n No external resistors required
`n Linear topology
`n Suspend to Ram (STR) functionality
`n Low external component count
`n Thermal Shutdown
`n Available in SO-8, PSOP-8 packages
`
`Applications
`n DDR-II Termination Voltage
`n SSTL-18 Termination
`
`20109418
`
`© 2006 National Semiconductor Corporation
`
`DS201094
`
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`Connection Diagrams
`
`LP2997
`
`PSOP-8 Layout
`
`20109403
`
`SO-8 Layout
`
`20109404
`
`Pin Descriptions
`
`SO-8 Pin or
`PSOP-8 Pin
`1
`2
`3
`4
`5
`6
`7
`8
`
`Name
`
`GND
`SD
`VSENSE
`VREF
`VDDQ
`AVIN
`PVIN
`VTT
`
`EP
`
`Function
`
`Ground
`Shutdown
`Feedback pin for regulating VTT.
`Buffered internal reference voltage of VDDQ/2
`Input for internal reference equal to VDDQ/2
`Analog input pin
`Power input pin
`Output voltage for connection to termination
`resistors
`Exposed pad thermal connection Connect to
`soft Ground
`
`Ordering Information
`
`Order Number
`
`Package Type
`
`LP2997M
`LP2997MX
`LP2997MR
`LP2997MRX
`
`SO-8
`SO-8
`PSOP-8
`PSOP-8
`
`NSC Package
`Drawing
`M08A
`M08A
`MRA08A
`MRA08A
`
`Supplied As
`
`95 Units per Rail
`2500 Units Tape and Reel
`95 Units Tape and Reel
`2500 Units Tape and Reel
`
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`LP2997
`
`151˚C/W
`43˚C/W
`1kV
`
`0˚C to +125˚C
`2.2V to 5.5V
`
`SO-8 Thermal Resistance (θJA)
`PSOP-8 Thermal Resistance (θJA)
`Minimum ESD Rating (Note 2)
`
`Operating Range
`Junction Temp. Range (Note 3)
`AVIN to GND
`
`Absolute Maximum Ratings (Note 1)
`If Military/Aerospace specified devices are required,
`please contact the National Semiconductor Sales Office/
`Distributors for availability and specifications.
`
`PVIN, AVIN, VDDQ to GND
`No pin should exceed AVIN
`Storage Temp. Range
`Junction Temperature
`Lead Temperature (Soldering, 10 sec)
`
`−0.3V to +6V
`−65˚C to +150˚C
`150˚C
`260˚C
`
`Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C and limits in boldface
`type apply over the full Operating Temperature Range (TJ = 0˚C to +125˚C) (Note 4). Unless otherwise specified,
`AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V.
`
`Max
`0.887
`0.937
`0.986
`
`0.887
`0.939
`0.988
`
`0.890
`0.940
`0.990
`25
`25
`25
`500
`
`150
`
`5
`
`0.8
`
`Units
`
`V
`
`kΩ
`
`V
`
`mV
`
`µA
`
`kΩ
`µA
`
`µA
`
`V
`
`V
`
`nA
`Celsius
`Celsius
`
`Typ
`0.860
`0.910
`0.959
`2.5
`
`0.856
`0.908
`0.957
`
`0.856
`0.908
`0.957
`
`0 0 0
`
`320
`
`100
`115
`
`2
`
`13
`165
`10
`
`Min
`0.837
`0.887
`0.936
`
`0.822
`0.874
`0.923
`
`0.828
`0.878
`0.928
`-25
`-25
`-25
`
`1.9
`
`Conditions
`PVIN = VDDQ = 1.7V
`PVIN = VDDQ = 1.8V
`PVIN = VDDQ = 1.9V
`IREF = -30 to +30 µA
`
`IOUT = 0A
`PVIN = VDDQ = 1.7V
`PVIN = VDDQ = 1.8V
`PVIN = VDDQ = 1.9V
`IOUT = ±0.5A (Note 7)
`PVIN = VDDQ = 1.7V
`PVIN = VDDQ = 1.8V
`PVIN = VDDQ = 1.9V
`IOUT = 0A
`IOUT = -0.5A
`IOUT = +0.5A
`IOUT = 0A (Note 5)
`
`SD = 0V
`
`SD = 0V
`
`(Note 6)
`
`Symbol
`VREF
`
`Parameter
`VREF Voltage
`
`ZVREF
`
`VTT
`
`VREF Output
`Impedance
`VTT Output Voltage
`
`VosTT/VTT
`
`VTT Output Voltage
`Offset (VREF-VTT)
`
`IQ
`
`ZVDDQ
`ISD
`
`IQ_SD
`
`VIH
`
`VIL
`
`ISENSE
`TSD
`TSD_HYS
`
`Quiescent Current
`(Note 5)
`VDDQ Input Impedance
`Quiescent Current in
`Shutdown (Note 5)
`Shutdown Leakage
`Current
`Minimum Shutdown
`High Level
`Maximum Shutdown
`Low Level
`VSENSE Input Current
`Thermal Shutdown
`Thermal Shutdown
`Hysteresis
`
`3
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`Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C and limits in boldface type
`apply over the full Operating Temperature Range (TJ = 0˚C to +125˚C) (Note 4). Unless otherwise specified,
`AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V. (Continued)
`
`Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
`intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The
`guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
`test conditions.
`Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
`Note 3: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θJA = 151.2˚ C/W
`junction to ambient with no heat sink.
`Note 4: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
`(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
`Note 5: Quiescent current defined as the current flow into AVIN.
`Note 6: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, θJA, and
`the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal
`shutdown.
`Note 7: VTT load regulation is tested by using a 10 ms current pulse and measuring VTT.
`
`LP2997
`
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`LP2997
`
`Typical Performance Characteristics
`Iq vs AVIN in SD
`
`Iq vs AVIN
`
`VIH and VIL
`
`VREF vs VDDQ
`
`20109420
`
`20109421
`
`VTT vs VDDQ
`
`Iq vs AVIN in SD Temperature
`
`20109422
`
`20109424
`
`20109426
`
`20109427
`
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`

`Typical Performance Characteristics (Continued)
`
`Iq vs AVIN Temperature
`
`Maximum Sourcing Current vs AVIN
`(VDDQ = 1.8V, PVIN = 1.8V)
`
`LP2997
`
`Maximum Sinking Current vs AVIN
`(VDDQ = 1.8V)
`
`20109428
`
`20109435
`
`20109436
`
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`LP2997
`
`Block Diagram
`
`Description
`The LP2997 is a linear bus termination regulator designed to
`meet the JEDEC requirements of SSTL-18. The output, VTT
`is capable of sinking and sourcing current while regulating
`the output voltage equal to VDDQ / 2. The output stage has
`been designed to maintain excellent load regulation while
`preventing shoot through. The LP2997 also incorporates two
`distinct power rails that separates the analog circuitry from
`the power output stage. This allows a split rail approach to
`be utilized to decrease internal power dissipation. It also
`permits the LP2997 to provide a termination solution for the
`next generation of DDR-SDRAM memory (DDRII).
`
`Pin Descriptions
`
`AVIN AND PVIN
`AVIN and PVIN are the input supply pins for the LP2997.
`AVIN is used to supply all the internal control circuitry. PVIN,
`however, is used exclusively to provide the rail voltage for
`the output stage used to create VTT. These pins have the
`capability to work off separate supplies, under the condition
`that AVIN is always greater than or equal to PVIN. For
`SSTL-18 applications, it is recommended to connect PVIN to
`the 1.8V rail used for the memory core and AVIN to a rail
`within its operating range of 2.2V to 5.5V (typically a 2.5V
`supply). PVIN should always be used with either a 1.8V or
`2.5V rail. This prevents the thermal limit from tripping be-
`cause of excessive internal power dissipation. If the junction
`temperature exceeds the thermal shutdown than the part will
`enter a shutdown state identical to the manual shutdown
`where VTT is tri-stated and VREF remains active. A lower rail
`such as 1.5V can be used but it will reduce the maximum
`output current, therefore it is not recommended for most
`termination schemes.
`
`VDDQ
`VDDQ is the input used to create the internal reference
`voltage for regulating VTT. The reference voltage is gener-
`ated from a resistor divider of two internal 50kΩ resistors.
`This guarantees that VTT will track VDDQ / 2 precisely. The
`optimal implementation of VDDQ is as a remote sense. This
`can be achieved by connecting VDDQ directly to the 1.8V
`rail at the DIMM instead of PVIN. This ensures that the
`reference voltage tracks the DDR memory rails precisely
`without a large voltage drop from the power lines. For
`SSTL-18 applications VDDQ will be a 1.8V signal, which will
`
`20109405
`
`create a 0.9V termination voltage at VTT (See Electrical
`Characteristics Table for exact values of VTT over tempera-
`ture).
`
`VSENSE
`The purpose of the sense pin is to provide improved remote
`load regulation. In most motherboard applications the termi-
`nation resistors will connect to VTT in a long plane. If the
`output voltage was regulated only at
`the output of
`the
`LP2997 then the long trace will cause a significant IR drop
`resulting in a termination voltage lower at one end of the bus
`than the other. The VSENSE pin can be used to improve this
`performance, by connecting it to the middle of the bus. This
`will provide a better distribution across the entire termination
`bus. If remote load regulation is not used then the VSENSE
`pin must still be connected to VTT. Care should be taken
`when a long VSENSE trace is implemented in close proximity
`to the memory. Noise pickup in the VSENSE trace can cause
`problems with precise regulation of VTT. A small 0.1uF ce-
`ramic capacitor placed next to the VSENSE pin can help filter
`any high frequency signals and preventing errors.
`
`SHUTDOWN
`The LP2997 contains an active low shutdown pin that can be
`used for suspend to RAM functionality. In this condition the
`VTT output will tri-state while the VREF output remains active
`providing a constant reference signal for the memory and
`chipset. During shutdown VTT should not be exposed to
`voltages that exceed PVIN. With the shutdown pin asserted
`low the quiescent current of the LP2997 will drop, however,
`VDDQ will always maintain its constant impedance of 100kΩ
`for generating the internal reference. Therefore, to calculate
`the total power loss in shutdown both currents need to be
`considered. For more information refer to the Thermal Dis-
`sipation section. The shutdown pin also has an internal
`pull-up current; therefore, to turn the part on the shutdown
`pin can either be connected to AVIN or left open
`
`VREF
`VREF provides the buffered output of the internal reference
`voltage VDDQ / 2. This output should be used to provide the
`reference voltage for the Northbridge chipset and memory.
`Since these inputs are typically an extremely high imped-
`ance, there should be little current drawn from VREF. For
`improved performance, an output bypass capacitor can be
`used, located close to the pin, to help with noise. A ceramic
`capacitor in the range of 0.1 µF to 0.01 µF is recommended.
`
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`

`very low ESR (typically less than 10 mΩ). However, some
`dielectric types do not have good capacitance characteris-
`tics as a function of voltage and temperature. Because of the
`typically low value of capacitance it is recommended to use
`ceramic capacitors in parallel with another capacitor such as
`an aluminum electrolytic. A dielectric of X5R or better is
`recommended for all ceramic capacitors.
`Hybrid - Several hybrid capacitors such as OS-CON and SP
`are available from several manufacturers. These offer a
`large capacitance while maintaining a low ESR. These are
`the best solution when size and performance are critical,
`although their cost is typically higher than any other capaci-
`tors.
`
`Thermal Dissipation
`Since the LP2997 is a linear regulator any current flow from
`VTT will result in internal power dissipation generating heat.
`To prevent damaging the part from exceeding the maximum
`allowable junction temperature, care should be taken to
`derate the part dependent on the maximum expected ambi-
`ent temperature and power dissipation. The maximum allow-
`able internal temperature rise (TRmax) can be calculated
`given the maximum ambient
`temperature (TAmax) of
`the
`application and the maximum allowable junction temperature
`(TJmax).
`
`TRmax = TJmax − TAmax
`From this equation, the maximum power dissipation (PDmax)
`of the part can be calculated:
`PDmax = TRmax / θJA
`The θJA of the LP2997 will be dependent on several vari-
`ables: the package used; the thickness of copper; the num-
`ber of vias and the airflow. For instance, the θJA of the SO-8
`is 163˚C/W with the package mounted to a standard 8x4
`2-layer board with 1oz. copper, no airflow, and 0.5W dissi-
`pation at room temperature. This value can be reduced to
`151.2˚C/W by changing to a 3x4 board with 2 oz. copper that
`is the JEDEC standard. Figure 1 shows how the θJA varies
`with airflow for the two boards mentioned.
`
`FIGURE 1. θJA vs Airflow (SO-8)
`
`20109407
`
`Additional improvements can be made by the judicious use
`of vias to connect the part and dissipate heat to an internal
`ground plane. Using larger traces and more copper on the
`
`Pin Descriptions (Continued)
`This output remains active during the shutdown state and
`thermal shutdown events for the suspend to RAM function-
`ality.
`
`VTT
`VTT is the regulated output that is used to terminate the bus
`resistors. It is capable of sinking and sourcing current while
`regulating the output precisely to VDDQ / 2. The LP2997 is
`designed to handle continuous currents of up to +/- 0.5A with
`excellent load regulation. If a transient is expected to last
`above the maximum continuous current rating for a signifi-
`cant amount of time, then the bulk output capacitor should
`be sized large enough to prevent an excessive voltage drop.
`If the LP2997 is to operate in elevated temperatures for long
`durations care should be taken to ensure that the maximum
`junction temperature is not exceeded. Proper thermal de-
`rating should always be used. (Please refer to the Thermal
`Dissipation section) If the junction temperature exceeds the
`thermal shutdown point than VTT will tri-state until the part
`returns below the temperature hysteresis trip-point
`
`Component Selections
`
`INPUT CAPACITOR
`The LP2997 does not require a capacitor for input stability,
`but
`it
`is recommended for improved performance during
`large load transients to prevent the input rail from dropping.
`The input capacitor should be located as close as possible to
`the PVIN pin. Several recommendations exist dependent on
`the application required. A typical value recommended for AL
`electrolytic capacitors is 22 µF. Ceramic capacitors can also
`be used. A value in the range of 10 µF with X5R or better
`would be an ideal choice. The input capacitance can be
`reduced if the LP2997 is placed close to the bulk capaci-
`tance from the output of the 1.8V DC-DC converter. For the
`AVIN pin, a small 0.1uF ceramic capacitor is sufficient to
`prevent excessive noise from coupling into the device.
`
`OUTPUT CAPACITOR
`The LP2997 has been designed to be insensitive of output
`capacitor size or ESR (Equivalent Series Resistance). This
`allows the flexibility to use any capacitor desired. The choice
`for output capacitor will be determined solely on the applica-
`tion and the requirements for load transient response of VTT.
`As a general recommendation the output capacitor should
`be sized above 100 µF with a low ESR for SSTL applications
`with DDR-SDRAM. The value of ESR should be determined
`by the maximum current spikes expected and the extent at
`which the output voltage is allowed to droop. Several capaci-
`tor options are available on the market and a few of these
`are highlighted below:
`AL - It should be noted that many aluminum electrolytics only
`specify impedance at a frequency of 120 Hz, which indicates
`they have poor high frequency performance. Only aluminum
`electrolytics that have an impedance specified at a higher
`frequency (100 kHz) should be used for the LP2997. To
`improve the ESR several AL electrolytics can be combined in
`parallel for an overall reduction. An important note to be
`aware of is the extent at which the ESR will change over
`temperature. Aluminum electrolytic capacitors can have their
`ESR rapidly increase at cold temperatures.
`Ceramic - Ceramic capacitors typically have a low capaci-
`tance, in the range of 10 to 100 µF range, but they have
`excellent AC performance for bypassing noise because of
`
`LP2997
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`LP2997
`
`To calculate the maximum power dissipation at VTT both
`conditions at VTT need to be examined, sinking and sourcing
`current. Although only one equation will add into the total,
`VTT cannot source and sink current simultaneously.
`PVTT = VVTT x ILOAD (Sinking) or
`PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing)
`The power dissipation of the LP2997 can also be calculated
`during the shutdown state. During this condition the output
`VTT will tri-state, therefore that term in the power equation
`will disappear as it cannot sink or source any current (leak-
`age is negligible). The only losses during shutdown will be
`the reduced quiescent current at AVIN and the constant
`impedance that is seen at the VDDQ pin.
`PD = PAVIN + PVDDQ
`PAVIN = IAVIN x VAVIN
`PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
`
`Thermal Dissipation (Continued)
`top side of the board can also help. With careful layout it is
`possible to reduce the θJA further than the nominal values
`shown in Figure 1
`Optimizing the θJA and placing the LP2997 in a section of a
`board exposed to lower ambient temperature allows the part
`to operate with higher power dissipation. The internal power
`dissipation can be calculated by summing the three main
`sources of
`loss: output current at VTT, either sinking or
`sourcing, and quiescent current at AVIN and VDDQ. During
`the active state (when shutdown is not held low) the total
`internal power dissipation can be calculated from the follow-
`ing equations:
`
`PD = PAVIN + PVDDQ + PVTT
`
`Where,
`
`PAVIN = IAVIN * VAVIN
`PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
`
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`

`Figure 2 shows the recommended circuit configuration for
`DDR-II applications. The output stage is connected to the
`1.8V rail and the AVIN pin can be connected to either a 2.5V,
`3.3V or 5V rail.
`
`Typical Application Circuits
`Several different application circuits have been shown to
`illustrate some of the options that are possible in configuring
`the LP2997. Graphs of the individual circuit performance can
`be found in the Typical Performance Characteristics section
`in the beginning of the datasheet. These curves illustrate
`how the maximum output current is affected by changes in
`AVIN and PVIN.
`
`LP2997
`
`FIGURE 2. Recommended DDR-II Termination
`
`20109413
`
`This circuit permits termination in a minimum amount of
`board space and component count. Capacitor selection can
`be varied depending on the number of lines terminated and
`the maximum load transient. However, with motherboards
`and other applications where VTT is distributed across a long
`plane it is advisable to use multiple bulk capacitors and
`addition to high frequency decoupling. The bulk output ca-
`pacitors should be situated at both ends of the VTT plane for
`optimal placement. Large aluminum electrolytic capacitors
`are used for their low ESR and low cost.
`
`PCB Layout Considerations
`1.
`The input capacitor for the power rail should be placed
`as close as possible to the PVIN pin.
`2. VSENSE should be connected to the VTT termination bus
`at the point where regulation is required. For mother-
`board applications an ideal
`location would be at the
`center of the termination bus.
`
`3. VDDQ can be connected remotely to the VDDQ rail input
`at either the DIMM or the Chipset. This provides the
`most accurate point for creating the reference voltage.
`4. For improved thermal performance excessive top side
`copper should be used to dissipate heat from the pack-
`age. Numerous vias from the ground connection to the
`internal ground plane will help. Additionally these can be
`located underneath the package if manufacturing stan-
`dards permit.
`5. Care should be taken when routing the VSENSE trace to
`avoid noise pickup from switching I/O signals. A 0.1uF
`ceramic capacitor located close to the SENSE can also be
`used to filter any unwanted high frequency signal. This
`can be an issue especially if long SENSE traces are used.
`6. VREF should be bypassed with a 0.01 µF or 0.1 µF
`ceramic capacitor for improved performance. This ca-
`pacitor should be located as close as possible to the
`VREF pin.
`
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`LP2997
`
`Physical Dimensions inches (millimeters) unless otherwise noted
`
`8-Lead Small Outline Package (M8)
`NS Package Number M08A
`
`8-Lead PSOP Package (PSOP-8)
`NS Package Number MRA08A
`
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`Notes
`
`LP2997DDR-IITerminationRegulator
`
`National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
`the right at any time without notice to change said circuitry and specifications.
`For the most current product information visit us at www.national.com.
`
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`expected to cause the failure of the life support device or
`system, or to affect its safety or effectiveness.
`
`National Semiconductor
`Americas Customer
`Support Center
`Email: new.feedback@nsc.com
`Tel: 1-800-272-9959
`
`www.national.com
`
`National Semiconductor
`Europe Customer Support Center
`Fax: +49 (0) 180-530 85 86
`Email: europe.support@nsc.com
`Deutsch Tel: +49 (0) 69 9508 6208
`English Tel: +44 (0) 870 24 0 2171
`Français Tel: +33 (0) 1 41 91 8790
`
`National Semiconductor
`Asia Pacific Customer
`Support Center
`Email: ap.support@nsc.com
`
`National Semiconductor
`Japan Customer Support Center
`Fax: 81-3-5639-7507
`Email: jpn.feedback@nsc.com
`Tel: 81-3-5639-7560
`
`Netlist Ex 2009
`Samsung v Netlist
`IPR2022-00996
`
`