TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`Overview
`
`Technical Note
`Power Solutions for DDR2 Notebook PCs
`In cooperation with
`
`Overview
`
`This technical note provides general guidelines for designing power circuitry for DDR2
`memory. It includes the DDR2 voltage requirements and encompasses a sample refer-
`ence design focused on the Texas Instruments Incorporated (TI) TPS51116, a complete
`DDR2 memory power solution that includes a synchronous buck controller, 3A linear
`dropout regulator (LDO), and buffered references.
`
`DDR2 Advantages for Notebooks
`DDR2 memory is an excellent solution for notebook computers. Aside from faster
`speeds, its greatest advantage over older memory technologies is its reduced power
`consumption, which results in cooler operating temperatures and extended battery life
`(see Figure 1 on page 2).
`
`The reduced power consumption is realized through a number of design features,
`including lower operating voltages, reduced page sizes, and 4n-prefetch support. DDR2
`memory uses a low operating voltage of only VDD = VDDQ = 1.8V and supports an
`SSTL_18 I/O interface. The reduced page sizes minimize the activation current, and the
`4n-prefetch architecture allows the device core to run at a slower frequency while
`driving an ultra-fast data rate (currently up to 1066 MT/s/b).
`
`Another advantage of DDR2 memory in notebooks is higher density in the same space;
`aside from the voltage-key placement and pinout change, the DDR2 SODIMM uses the
`same 200-pin socket as DDR.
`
`At the device level, DDR2 components are manufactured at individual memory densities
`up to 2Gb (at the component level, this reflects a 128Mb x 16 or 256Mb x 8 device), which
`means DDR2 supports a 4GB channel with just 2 slots.
`
`Also new with DDR2 memory is on-die termination (ODT), which has a significant
`impact on signal quality and power dissipation. ODT gives the controller more effective
`management of termination to the high-speed signals where and when it is needed.
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`1
`©2004 Micron Technology, Inc. All rights reserved.
`TN4705.fm - Rev. B 4/10 EN
`Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
`Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All
`information discussed herein is provided on an “as is” basis, without warranties of any kind. Products and specifications
`discussed herein are subject to change by Micron without notice.
`
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`

` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`DDR2 Advantages for Notebooks
`
`Figure 1:
`
` Power Performance Curves on SDR, DDR, and DDR2
`
`SDR (PC133)
`
`DDR (DDR333)
`
`DDR2 (DDR2-533)
`
`*Includes DRAM core power only
`Dual-rank, 256Mb (16 Meg x 16)-based SODIMMs,
`utilizing CKE on unused rank with 50% page hits
`
` 20%
`
` 30%
`
` 40%
`
` 50%
` 60%
`Bandwidth
`
` 70% 80%
`
`3.5
`
`3.0
`
`2.5
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0.0
`
`Watts*
`
`DDR2 Notebook Assumptions
`JEDEC has defined 4 standardized small outline, dual in-line memory modules
`(SODIMMs) that include single- and dual-rank DIMMs utilizing either x16 or x8 devices.
`All 4 configurations are 64-bit-wide unbuffered SODIMMs with predefined electrical
`and mechanical specifications.
`
`This technical note assumes that the notebook system designer will utilize a dual
`memory channel with 2 slots, 1 per channel (see Figure 2 on page 3). For a dual-channel,
`2-slot system, both the address and command lines terminate at VTT through a resistor.
`All the high-speed data strobes and data signals utilize localized ODT. On the module,
`the differential clock pairs (CK/CK#) are differentially terminated.
`
`This combination makes for a low-cost, low-power application that maximizes battery
`life while maintaining a small size and high performance.
`
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`TN4705.fm - Rev. B 4/10 EN
`
`2
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
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` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`DDR2 Voltage Requirements
`
`DDR2 Voltage Requirements
`One challenge in designing a DDR2 system is meeting the strict power requirements and
`predefined power-up and initialization sequences as defined by JEDEC (JESD79-2 DDR2
`SDRAM Specification). Therefore, it is critical that the initial power ramps be controlled
`to meet specifications. In addition, both the termination voltage (VTT) and reference
`voltage (VREF) must maintain their respected relationships to VDD at all times. The
`following sections provide detailed voltage requirements for DDR2 notebook systems.
`
`Figure 2:
`
` Functional Block Diagram of a Dual-Channel, 2-Slot DDR2 Notebook
`
`Battery (Adaptor)
`
`Rt
`
`VTT
`
`4.5V–28V(DC)
`
`Power Good
`
`S3
`
`S5
`
`SODIMM 1
`
`ODT Circuit
`VDDQ
`
`sw1
`
`R1
`
`R2
`
`VSSQ
`
`Main Controller (CPU)
`
`SODIMM 2
`
`ODT Circuit
`VDDQ
`
`sw1
`
`R1
`
`R2
`
`VSSQ
`
`Data/Strobes
`
`Data/Strobes
`
`DDR2
`Memory
`Controller
`
`2 Clock Pairs
`
`(SSTL_18 I/O)
`
`2 Clock Pairs
`
`Address/Command
`and Control Lines
`
`Address/Command
`and Control Lines
`
`VREF
`
`VDDSPD
`
`Rt
`
`VTT
`
`VDD (VDD, VDDQ, VDDL)
`
`TI Voltage Controller (TPS51116)
`
`VSS
`(VSS, VSSQ, VSSL, VSSSPD)
`
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`

`Supply
`
`VDD (VDD, VDDL, VDDQ)
`
`VREF
`
` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`DDR2 Voltage Requirements
`
`The DDR2 device requires a single power source for primary supply voltages in order to
`ensure that all voltage levels track each other, especially during the power ramp. At the
`module level, VDD (device core), VDDL (device DLL), and VDDQ (device I/O) share a single
`power plane with the interconnecting pins labeled as VDD. Likewise, VSS, VSSL, and VSSQ
`share a common ground plane labeled as VSS.
`The memory supply voltage is specified as VDD = VDDQ = 1.8V with a DC tolerance of
`±100mV. DC is defined as any signal ≤20 MHz. At the initial power-up, all supply power
`should be stable and meet specification within ≤10ms.
`
`The amount of current each module consumes depends on the density and speed of the
`module, number of ranks, and, most importantly, the usage conditions. For example, to
`build a high-density, dual-rank module using (x8) DRAMs, 16 individual devices are
`required. A system utilizing 2 of these modules and running a heavy-use condition may
`consume up to 7W–8W. However, the same system, using 1 lower-density, dual-rank
`module using (x16) DRAMs, will have only 8 discrete components each, and, under
`moderate use conditions, might consume a total of only 1.5W–2W.
`
`Micron’s Web site has a dedicated technical note, “TN-47-04: Calculating Memory
`System Power for DDR2,” and a custom DDR2 power calculator that provide additional
`information about how to estimate actual module power usage at
`www.micron.com/systemcalc.
`
`Another key supply voltage is the input reference voltage (VREF). All DDR2 input
`receivers are calibrated to operate within the specified VREF input levels. For proper
`device operation, it is critical that the VREF input is free from excess noise or voltage vari-
`ations. Any degrading of the VREF input voltage directly affects the setup and hold times
`of the DDR2 device.
`VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
`DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed
`±1% of the DC value. Peak-to-peak AC noise on VREF must not exceed ±2% of VREF(DC).
`AC noise is defined as any noise over 20 MHz in frequency. There is virtually no current
`draw on the DDR2 VREF pin; only leakage current is present (less than 5µA per DRAM
`component).
`
`Figure 3 on page 5 shows the industry-standard voltage specifications and tracking
`requirements for VREF.
`
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`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
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` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`DDR2 Voltage Requirements
`
`Figure 3:
`
` Required VREF Voltage Relationships
`
`VREF(AC)max = VDDQ x 0.52
`VREF(DC)max = VDDQ x 0.51
`VREF,nom* = VDDQ/2
`VREF(DC)min = VDDQ x 0.49
`VREF(AC)min = VDDQ x 0.48
`
`*VREF should track variations in VDDQ and VREF(AC)
` and must always be within 1% of VREF(DC)
`
`1.7V
`
`1.8V
`VDDQ (V)
`
`1.9V
`
`1.00
`
`0.98
`
`0.96
`
`0.94
`
`0.92
`
` 0.9
`
`0.88
`
`0.86
`
`0.84
`
`0.82
`
`0.80
`
`VREF(V)
`
`VTT
`
`DDR2 memory is optimized for stub-series terminated logic at 1.8V (SSTL_18) opera-
`tion. The address, command, and control lines require system-level termination to a
`midpoint voltage. This midpoint voltage is called VTT (or the I/O termination voltage).
`Having the termination sit at midpoint ensures symmetry for switching times. It is
`important that VTT tracks any variation in the DC levels of VREF. By specification, at all
`times VTT must equal VREF ±40mV. The termination voltage (VTT) is supplied directly to
`the motherboard but not to the module. See Figure 4 on page 6 for logic levels of a prop-
`erly terminated SSTL_18 signal.
`
`ODT (On-Die Termination)
`
`As previously mentioned, DDR2’s high-speed, bidirectional signals (data and strobes)
`are uniquely terminated with on-die termination (ODT). This new feature allows for
`optimal signal quality (see Figure 5 on page 6) by dynamically controlling the exact
`termination value where and when it is needed. For example, the ideal placement for
`termination is at the end of the active signal trace. So, when WRITING to SODIMM1, the
`memory controller dynamically disables the ODT function on SODIMM2 and the
`memory controller (both buses) and activates the ODT circuitry on SODIMM1 (at the
`end of the active transmission line). Likewise, during a READ from either SODIMM, the
`
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` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`DDR2 Voltage Requirements
`
`memory controller dynamically disables the ODT circuitry at both SODIMM locations
`and enables ODT circuitry on the active bus at the memory controller. ODT facilitates a
`much-simpler board design that uses fewer components and thereby costs less.
`
`ODT also allows better thermal and power-management control. For example, during
`DRAM inactive times, most memory controllers completely disable the termination in
`order to conserve power. ODT can accomplish this dynamically.
`
`Figure 4:
`
` SSTL_18 Single-Ended Input-Logic Levels
`
`1150mV
`
`1025mV
`
`936mV
`918mV
`900mV
`882mV
`864mV
`
`775mV
`
`650mV
`
`VIH(AC)
`
`VIH(DC)
`
`VREF + AC Noise
`VREF + DC Error
`VREF - DC Error
`VREF - AC Noise
`
`VIL(DC)
`
`VIL(AC)
`
`Note: Numbers in diagram reflect nominal values (VDD = VDDQ = 1.8V)
`
`Figure 5:
`
` Functional Block Diagram of ODT
`
`DQ Pins
`
`Output
`Driver
`
`VDDQ
`
`RC VR
`
`2 RTT
`
`2 RTT
`
`VSSQ
`
`ODT Pin
`
`Control
`
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`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
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`

` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`Power Management for Notebooks with Micron DDR2 and TI
`
`VDDSPD
`
`Although not utilized for the DRAM, there is one additional power requirement for the
`SODIMM—the power for the serial present detect (SPD) EEPROM, which holds the
`module operating parameters. This voltage (VDDSPD) has a wide range tolerance, from
`+1.7V to +3.6V. In its worst case, the current draw of this pin should be no more than
`3mA–4mA.
`
`Power Management for Notebooks with Micron DDR2 and TI TPS51116
`Designers who use Micron's DDR2 memory modules can now incorporate TI’s
`TPS51116, an integrated power-management solution that combines a DC/DC current-
`mode switching controller with a 3A sink/source linear dropout regulator (LDO). This
`highly integrated device significantly reduces the number of external components typi-
`cally required to support all the power management for DDR2 memory systems, making
`the TPS51116 easy to use while offering a smaller total-solution size and lower total-
`solution cost, without sacrificing performance.
`
`TPS51116: A Solution for Complete DDR2 Power Management
`Figure 6 on page 8 shows a typical application schematic for the TPS51116 and how it
`integrates into the complete DDR2 power-management solution with:
`(cid:129) Synchronous current mode DC/DC controller to power VDD
`(cid:129) Buffered reference to provide VREF (VREF tracks one-half VDD)
`(cid:129) 3A sink/source LDO to power VTT (VTT tracks VREF)
`(cid:129) S3/S5 sleep-state controls
`
`This high-level integration simplifies the design of the power-management segment of
`DDR2 memory. This places the burden on the TPS51116 to meet the industry-standard
`specifications and the proper management of S3 and S5 states.
`The synchronous current mode DC/DC controller is used to power VDD/VDDQ. Imple-
`menting the power supply requires 2 external NFETs, in addition to an inductor and
`input/output capacitors. This output is used to power DDR2 memory’s VDD/VDDQ and is
`able to achieve high efficiency during wide load variation—expected to range from
`10mA to 10A.
`
`The output of TPS51116’s switcher is internally divided down by one half and is used to
`generate VREF. The VREF output tracks changes in VDD/VDDQ with a high level of accu-
`racy, achieved by the precisely matched internal-resistor divider. VREF is buffered,
`helping increase its immunity to noise and changes in load. This is critical in main-
`taining the stringent VREF to VDDQ tracking requirements of the DDR2 device.
`The final-output-voltage rails required for DDR2 is for VTT. The power for this rail comes
`from the LDO segment of the TPS51116. The LDO supports 3A peak current and has 1.5A
`continuous current capabilities.
`
`This LDO can sink/source current and meet the industry-standard specifications with
`only 2x10uF ceramic output capacitors. DDR2 allows the use of an LDO to power termi-
`nation (VTT) because of the reduction in required current, resulting from the implemen-
`tation of ODT.
`
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`TN4705.fm - Rev. B 4/10 EN
`
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`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
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`

` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`Line Regulation, Load Regulation, and Transient Response
`
`Figure 6:
`
` Typical Application Circuit for TPS51116
`
`VIN
`
`C5
`ceramic
`2x10uF
`
`VDD
`
`C8
`SP-CAP
`2x150uF
`
`GND
`
`5V_IN
`
`R1 = 5.11K W
`R2 = 100K W
`M1 = IRF7821
`M2 = IRF7832
`
`C1
`ceramic
`0.1uF
`
`L1
`1.1uF
`
`M1
`
`M2
`
`R1
`
`R2
`
`C2
`ceramic
`4.7uF
`
`GND
`
`TPS51116
`
`VBST
`DRVH
`LL
`DRVL
`PGND
`CS
`V5IN
`PGOOD
`S5
`S3
`
`20
`19
`18
`17
`16
`15
`14
`13
`12
`11
`
`VLDOIN
`VTT
`VTT GND
`VTT SNS
`GND
`MODE
`VTTREF
`COMP
`VDDQ SNS
`VDDQ SET
`
`1 2 3 4 5 6 7 8 9
`
`10
`
`VTT
`
`GND
`
`C4
`ceramic
`0.033uF
`
`GND
`
`VREF
`
`C3
`ceramic
`2x10uF
`
`S3
`S5
`PGOOD
`
`Line Regulation, Load Regulation, and Transient Response
`DDR2 memory requires industry-standard power specifications. The voltage tolerances
`that need to be supported throughout the changes in input voltage (line regulation),
`output current (load regulation), and transient response are defined as:
`(cid:129) VDDQ = 1.8V ±100mV
`(cid:129) VREF = 0.49 VDDQ/0.51 VDDQ
`(cid:129) VTT = VREF ±40mV
`Line regulation ensures that the tolerances are maintained when the input voltage
`changes. Figure 7 on page 9 shows as the input voltage changes from 4V to 28V, VDDQ
`changes by only a few millivolts (spec is ±100mV). VREF tracks VDDQ/2, and there is a
`difference of only about 10mV between VTT and VREF (spec is ±40mV).
`Load regulation and transient response ensures the tolerances are maintained when the
`output current changes. Load regulation is a static test condition, while transient
`response is a dynamic test condition.
`Figure 8 on page 9 shows VDDQ with a static load change from 0A to 10A on VDDQ, with
`its output voltage <35mV from 1.8V (specification is ±100mV). In Figure 9 on page 10,
`the load changes from -1.5A to 1.5A on VTT, and VDDQ is about 25mV from 1.8V (specifi-
`cation is ±100mV), with VTT–VREF near ±20mV (specification is VREF ±40mV).
`
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`
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` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`Line Regulation, Load Regulation, and Transient Response
`
`Figure 7:
`
` Line Regulation for All 3 Outputs
`
`VDDQ/2
`
`VREF
`
`VTT
`
`0.915
`
`0.910
`
`0.905
`
`0.900
`
`0.895
`
`0.890
`
`VOUT(V)*
`
`8
`
`12
`
`20
`
`24
`
`28
`
`32
`
`0
`
`4
`
`16
`VIN (V)
`* Test was performed with a 7A load on VDDQ/2 and a 0.3A load VTT
`
`Figure 8:
`
` Load Regulation VDDQ Only (VIN = 12V)
`
`0
`
`2
`
`6
`4
`Output Current (A)
`
`VDDQ
`
`8
`
`10
`
`1.850
`1.845
`1.840
`1.835
`1.830
`1.825
`1.820
`1.815
`1.810
`
`Volts
`
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`
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` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`Line Regulation, Load Regulation, and Transient Response
`
`Figure 9:
`
` Transient Response (VIN = 12V)
`
`Tek Stop: 2.50MS/s
`
`1
`
`32
`
`4
`
`VDDQ (25mV)
`
`VREF
`
`VTT
`
`VTT load
`(-1.5A to 1.5A)
`
`Ch1 50.0mV Ch2 20.0mV
`Ch3 20.0m V
`Ch4
`1.00 V
`
` Note: VTT–VREF (+/-20mV)
`
`M 20.0uS Ch4 1.54V
`
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` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`TPS51116 Manages the Critical Relationship Between VTT/VREF
`
`TPS51116 Manages the Critical Relationship Between VTT/VREF and VDDQ
`TI’s TPS51116 has a very important role in managing notebook sleep-state functions. For
`DDR2 memory, it is critical during both start-up and shutdown that VDDQ is always
`higher than VTT/VREF. If VTT/VREF is greater than VDDQ + 0.3V, the DDR2 memory could
`latch up.
`
`TPS51116’s integrated sleep-state functions help prevent this condition—the S3 and S5
`pins on the TPS51116 are connected to the S3 and S4/S5 control signals in the notebook
`computer (Figure 2 on page 3), enabling the S3 and S5 pins to be used to manage all
`sleep-state functions:
`(cid:129) S0 = Full On
`(cid:129) S3 = Suspend-to-RAM (STR)
`(cid:129) S4/S5 = Suspend-to-Disk (STD)/Soft Off
`
`Table 1 summarizes how the TPS51116 handles the sleep-state modes.
`
`When transitioning from an S4/S5 state (STD) to S0 (Full On), S5 will go HIGH first, and
`then S3 will go HIGH. Figure 10 on page 12 shows that when S5 goes HIGH, VDDQ turns
`on, and when S3 goes HIGH, VTT will turn on. During start-up, VTT cannot turn on until a
`VDDQ voltage exists; as soon as VDDQ voltage turns on, the VTT voltage will track VDDQ.
`Therefore, during start-up, VDDQ will always be greater than VTT.
`
`Table 1:
`
`S3 and S5 TPS51116 Input and Output Parameters
`
`State
`S0
`S3
`S4/S5
`
`Status
`Full On
`Suspend-to-RAM (STR)
`Suspend-to-Disk (STD)/Soft Off
`
`S3
`HIGH
`LOW
`LOW
`
`Inputs
`
`Outputs
`VTT
` VREF
`VDDQ
`S5
`On
`On
`On
`HIGH
`Off (High-Z)
` On
`On
`HIGH
`LOW Off (Discharge) Off (Discharge) Off (Discharge)
`
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`

` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`TPS51116 Manages the Critical Relationship Between VTT/VREF
`
`Figure 10: Full-On Power Ramp
`
`Tek Stop: 10.kS/s
`
`21
`
`3
`
`4
`
`VDDQ
`VTT
`
`S5
`
`S3
`
`Ch1 1.00 V
`Ch3 5.00 V
`
`Ch2 500mV
`Ch4 5.00V
`
`M 5.00ms Ch2 680mV
`
`During an S3 state, the S3 control signal goes LOW, and the system enters a Suspend-to-
`RAM state (STR). STR can occur only after the DRAM has been properly placed into self
`refresh mode. This requires a predefined series of command sequences (turn off ODT,
`precharge all banks, and then synchronously take CKE LOW with the AUTO REFRESH
`command). (See any Micron DDR2 data sheet for details on the required command
`sequence.)
`
`The STR or self refresh mode is the lowest DRAM power state. If the proper command
`sequences are followed, and all supply voltages are kept within their specified limits, the
`DDR2 DRAM will preserve the data contents indefinitely. During this state, VDD/VDDQ
`and VREF remain on, and VTT enters a high-impedance state (High-Z). The VTT output no
`longer sinks or sources current and is floating, as shown in Figure 11 on page 13.
`
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`TN4705.fm - Rev. B 4/10 EN
`
`12
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2006
`Samsung v Netlist
`IPR2022-00996
`
`

`

` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`TPS51116 Manages the Critical Relationship Between VTT/VREF
`
`Figure 11: Enter Suspend-to-RAM (STR)
`
`Tek Run: 50.0kS/s
`
`1
`
`2
`4
`
`3
`
`VDDQ
`
`VREF
`VTT
`(High-Z)
`
`S3
`
`Ch1 1.00 V
`Ch3 5.00 V
`
`500mV
`Ch2
`Ch4 500mV
`
`M 1.00ms Ch3 3.2 V
`
`Note: During Suspend-to-RAM, all supply voltages must be
` maintained within specified data sheet values, including VREF.
` VTT is not required during STR.
`
`For the TPS51116 to enter a Suspend-to-Disk (STD) state, the S5 signal must go LOW.
`During the STD (S4/S5 state), no power is supplied to the DRAM, and all DRAM data is
`lost. Upon exiting STD, it is critical that the DDR2 memory is powered up correctly, with
`a full initialization sequence. This includes the ramp-up of supply voltages and main-
`taining the required voltage relationships described previously.
`
`After all supply voltages are steady, there must be 200µs of stable clocks before CKE goes
`HIGH, and the DRAM initialization sequence is started. (See any Micron DDR2 data
`sheet for expanded DRAM initialization requirements.)
`During the STD, all TPS51116 outputs discharge to GND, including VDD/VDDQ, VTT, and
`VREF. The TPS51116 has been designed to ensure that VTT and VREF discharge more
`quickly than VDDQ to guarantee that VDDQ will always be greater than VTT/VREF, as
`shown in Figure 12 on page 14.
`
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`TN4705.fm - Rev. B 4/10 EN
`
`13
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2006
`Samsung v Netlist
`IPR2022-00996
`
`

`

` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`TPS51116 Manages the Critical Relationship Between VTT/VREF
`
`Figure 12: Suspend-to-DISK (STD)
`
`Tek Stop: 100kS/s
`
`4
`1
`
`2
`
`3
`
`VDDQ
`
`S5
`
`VTT
`
`VREF
`
`Ch1 1.00 V Ch2 500mV
`Ch4 5.00V
`Ch3
`500m V
`
`M 500ms Ch1 900mV
`
`Note: After the DRAM has been properly shut down, all supply
` voltages may be removed, and DRAM contents will be lost
`
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`TN4705.fm - Rev. B 4/10 EN
`
`14
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2006
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`IPR2022-00996
`
`

`

`Load Efficiency
`
` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`Load Efficiency
`
`The TPS51116 has a high level of integration, making it easy to use and offering a smaller
`total solution size and lower total solution cost, without sacrificing performance. One of
`the most important performance features is the efficiency of the switcher, which is used
`to power VDD. High efficiency at full loads—such as 10A—is important in reducing the
`total power dissipation and in extending battery life within the notebook computer.
`
`A reduction in total power dissipation translates to a reduction in cost and size. The
`higher the efficiency, the longer the battery will last when the notebook is on or in an
`active state. The TPS51116 efficiency at 10A is 90% (input voltage at 12V), which is
`considered very high, as shown in Figure 13.
`
`High efficiency at light loads—such as 10mA—is typically found during a standby condi-
`tion and is critical in extending battery life when the notebook is in a standby mode. The
`higher the efficiency, the longer the battery will last while in standby. The TPS51116 has
`exceptional light-load efficiency that achieves greater than 80% (input voltage at 12V), as
`shown in Figure 13.
`
`The TPS51116 can achieve this high level of efficiency at both 10A and 10mA because of
`its ability to adapt to the changes in load. At heavy loads—such as 10A—the high
`efficiency can be achieved because of the TPS51116’s strong gate-drive capability and
`the gate drive’s adaptive-dead-time control scheme. At light loads—such as 10mA—the
`TPS51116 enters skip mode, which significantly reduces the switching frequency.
`
`Figure 13: Light-Load and Full-Load VDD/VDDQ Efficiency
`
`0.100
`
`1.000
`
`10.000
`
`IDDQ (A)
`
`100
`
`95
`
`90
`
`85
`
`80
`
`75
`
`70
`
`65
`
`60
`
`55
`
`50
`0.010
`
`Efficiency (%)
`
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`TN4705.fm - Rev. B 4/10 EN
`
`15
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2006
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Summary
`
` TN-47-05 DDR2 POWER SOLUTIONS FOR NOTEBOOKS
`Summary
`
`DDR2 voltage requirements, solution, size, and efficiency are the most important
`considerations when designing power circuitry in a notebook computer. The TPS51116
`is an ideal solution for powering Micron’s DDR2 memory modules because it is opti-
`mized for low cost, is in a small total solution size, and provides high performance.
`
`The TPS51116 high-level integration requires only 7 external resistors and capacitors,
`not including the power train for the switcher. Other solutions will use 18 or more
`external components, even if the switcher is integrated with the LDO. Typically, these
`notebooks require separate power-management ICs for VDDQ and VTT/VREF.
`Texas Instruments’ power products can be found at www.ti.com.
`
`For notebook applications, DDR2 is an excellent solution, providing ultra-fast data-
`transfer rates with extremely low operating-power requirements, dynamic ODT termi-
`nation, and a small footprint.
`
`With ODT, there is substantially less termination and signal routing on the motherboard.
`To ensure functionality, strict guidelines must be followed, making it a challenge to
`successfully integrate a power solution for a reliable DDR2 notebook design. This tech-
`nical note identifies for the designer the critical DDR2 voltages and establishes a method
`to implement power to the DDR2 memory channel.
`
`For the latest data sheets, please refer to Micron’s Web site at www.micron.com/
`datasheets.
`
`PDF: 09005aef8130a7b8 / Source: 09005aef8135f026
`TN4705.fm - Rev. B 4/10 EN
`
`16
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2006
`Samsung v Netlist
`IPR2022-00996
`
`