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`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`
`SAMSUNG ELECTRONICS CO., LTD, MICRON TECHNOLOGY, INC.,
`MICRON SEMICONDUCTOR PRODUCTS, INC., and
`MICRON TECHNOLOGY TEXAS LLC
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`___________________
`
`Case No. IPR2022-00996
`Patent No. 11,016,918
`___________________
`
`PATENT OWNER’S SUR-REPLY
`
`
`
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
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`Case No. IPR2022-00996
`Patent No. 11,016,918
`
`TABLE OF CONTENTS
`
`I.
`II.
`
`Page
`CLAIM CONSTRUCTION ......................................................................... 1
`GROUNDS 1-3 (Reply 2-23) ....................................................................... 2
`A. Harris+FBDIMM Does Not Disclose Receiving Power Via
`Edge Connections (Reply, 2-7) .......................................................... 2
`Harris Does Not Disclose Receiving “data, address, and
`control signals” from the Host (Reply, 7-9) ....................................... 6
`A POSITA Would Not Have Used Four Converters in
`Grounds 1-3 (Reply, 9-18) ............................................................... 10
`1.
`Harris Uses a Single Converter to Provide Multiple
`Different Voltages (Reply, 10-13) ......................................... 10
`Samsung’s Argument That Using Different Converters
`for Voltages Having Different Functions is Improper
`and Unsupported (Reply, 13-15) ........................................... 15
`Harris Does Not Disclose or Suggest Generating VTT
`on the Module ........................................................................ 17
`A POSITA Would Not Have Used a Buck Converter
`to Provide VDDSPD ................................................................... 18
`D. A POSITA Would Not Have Modified Harris With Amidi’s
`Battery Backup (Reply, 18-20) ........................................................ 19
`The Prior Art Does Not Disclose a Trigger Signal to Switch
`to Backup Power in Response to Over-Voltage Detection
`(Reply, 20-22) .................................................................................. 20
`Non-Volatile Memory for Claims 10-11, 15, 22 (Reply, 23) .......... 22
`F.
`G. Write Operation for Claims 11-12, 18-19, 25-26 (Reply, 23) ......... 22
`III. GROUNDS 4-5 (Reply 23-37) ................................................................... 23
`A.
`Spiers’s PCI Card Is Not A Recited Memory Module ..................... 23
`
`B.
`
`C.
`
`E.
`
`2.
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`3.
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`4.
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`The Combination Does Not Render Obvious Challenged
`Claims ............................................................................................... 28
`1.
`No Usage of DDR2/DDR3 .................................................... 28
`2.
`No Usage of Four Buck Converters ....................................... 29
`(a)
`VTT 29
`(b)
`1.8V 30
`(c)
`1.8V and 1.5V ....................................................................... 31
`(d)
`5V-to-3.3V converter ............................................................ 31
`Other Claims ..................................................................................... 32
`(a)
`Pre-regulated input voltages ................................................. 32
`(b)
`Claim 23 ................................................................................ 33
`(c)
`Claim 13 ................................................................................ 33
`(d)
`Claims 5-7, 9-13, 16-22 and 24-27 (over-voltage
`detection) .............................................................................. 33
`Claims 8 and 14 .................................................................... 34
`(e)
`IV. CONCLUSION ........................................................................................... 34
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`C.
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Baldwin Graphic Sys., Inc. v. Siebert, Inc.,
`512 F.3d 1338 (Fed. Cir. 2008) .................................................................... 11
`Intel Corp. v. Qualcomm Inc.,
`21 F.4th 784 (Fed. Cir. 2021) ....................................................................... 32
`Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) .................................................................... 11
`Maxwell v. J. Baker, Inc.,
`86 F.3d 1098 (Fed. Cir. 1996) ...................................................................... 10
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`Patent No. 11,016,918
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`EXHIBIT LIST
`
`Document
`Declaration of Dr. Sunil P. Khatri
`U.S. 8,301,833
`Belloni, M. et al., A 4-Output Single-Inductor DC-DC Buck Converter
`with Self-Boosted Switch Drivers and 1.2A Total Output Current,
`ISSCC 2008, Session 24.6
`Ma, Dongsheng et al., Single-Inductor Multiple-Output Switching
`Converters With Time-Multiplexing Control in Discontinuous
`Conduction Mode, IEEE J. of Solid-State Circuits, 38(1) (Jan. 2003)
`U.S. 6,067,2451
`Micron Technical Note, TN-47-05 DDR2 Power Solutions for
`Notebooks Overview (2004)
`Texas Instruments, LP29996-N, LP2296A DDR Termination
`Regulator (Nov. 2002-Revised Dec. 2016)
`National Semiconductor, LP2996 DDR Termination Regulator (June
`2006), downloaded from https://datasheet.octopart.com/LP2996MR-
`NOPB-Texas-Instruments-datasheet-7837571.pdf (last visited
`09/08/2022)
`National Semiconductor, LP2997 DDR-II Termination Regulator
`(June 2006), downloaded from
`https://www.jameco.com/Jameco/Products/ProdDS/843930.pdf (last
`visited 09/08/2022)
`National Semiconductor, LP2998 DDR-II and DDR-I Termination
`Regulator (Dec. 12, 2007), downloaded from
`https://www.semiee.com/file/backup/INTERSIL-LP2998.pdf (last
`visited 09/08/2022)
`Bergveld, H. J., Battery Management Systems Design by Modeling,
`Royal Philips Electronics N.V. (2001)
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`
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`Exhibit No.
`EX2001
`EX2002
`EX2003
`
`EX2004
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`EX2005
`EX2006
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`EX2007
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`EX2008
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`EX2009
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`EX2010
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`EX2011
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`Document
`Romo, Joaquin, DDR Memories: Comparison and overview, NXP
`technical note, downloaded from
`https://www.nxp.com/docs/en/supporting-
`information/BeyondBits2article17.pdf (last access 09/08/2022). As
`downloaded the file shows the following meta data:
`
`
`JEDEC Standard No. 21-C, PC133 SDRAM Unbuffered SO-DIMM
`Reference Design Specification Rev. 1.02 (2001)
`Qimonda HYB39SC256[80/16]0FE, HYI39SC256[80/16]OFF
`datasheet (June 2007), downloaded from
`https://pdf.dzsc.com/200810211/200809251204372352.pdf (last
`visited 09/08/2022)
`Siemens HYS64/72V2200GU-8/-10, HYS64/72V4220GU-8/-10
`datasheet (June 1998), downloaded from
`https://cdn.datasheetspdf.com/pdf-down/P/C/6/PC66-222-
`920_SiemensSemiconductorGroup.pdf (last visited 09/08/2022)
`EURESYS, PCI Bus Variation Technical Note (2006), downloaded
`from PCI Bus Variation - Technology Note (euresys.com) (last
`accessed 09/08/2022)
`Qimonda HY[B/I]39S256[40/80/16]0FT(L) etc. datasheet (September
`2007), downloaded from
`https://cms.nacsemi.com/content/AuthDatasheets/QMDAS00628-
`1.pdf (last visited 09/08/2022)
`Transcend, What is the difference between SDRAM, DDR1, DDR2,
`DDR3 and DDR4? Downloaded from https://www.transcend-
`info.com/support/faq-296#:~:text=DDR3 (last visited 09/08/2022)
`Transcend company profile, https://us.transcend-
`info.com/about/company (last visited 09/08/2022)
`Brown, M., Power Supply Cookbook, Newnes (2d.) (2001)
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`
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`Exhibit No.
`EX2012
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`EX2013
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`EX2014
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`EX2015
`
`EX2016
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`EX2017
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`EX2018
`
`EX2019
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`EX2020
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`EX2022
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`EX2023
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`EX2024
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`EX2025
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`EX2026
`
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`Exhibit No.
`EX2021
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`Document
`Texas Instruments, Low Dropout Operation in a Buck Converter
`(SLUA928A, December 2018 — revised March. 2019), downloaded
`from Low Dropout Operation in a Buck Converter (Rev. A) (last
`visited 09/08/2022)
`Electronic Design, Simple Soft-Start Circuitry Provides Long Startup
`Times (June 22, 1998), downloaded from
`https://www.electronicdesign.com/power-
`management/article/21801244/simple-softstart-circuitry-provides-
`long-startup-times (last visited 09/08/2022)
`Micron Technical Note, TN-04-30, Various Methods of DRAM
`Refresh (1999), downloaded from DT30 (reactivemicro.com) (last
`visited 09/08/2022)
`Schmid, Patrick, Understanding Hard Drive Performance (March 5,
`2007), downloaded from
`https://www.tomshardware.com/reviews/understanding-hard-drive-
`performance,1557-5.html (last visited 09/08/2022)
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/dram/256mb_sdr.pdf (last visited 09/08/2022)
`Micron, 256Mb SDR SDRAM datasheet (1999), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/dram/64mb_x4x8x16_sdram.pdf (last visited 09/08/2022)
`Transcend, DDR2 SO-DIMM datasheet
`EX2027
`EX2028 Micron Technical Note TN-41-13, DDR3 Point-to-Point Design
`Support Introduction (2013), downloaded from
`https://www.micron.com/-
`/media/client/global/documents/products/technical-
`note/dram/tn4113_ddr3_point_to_point_design.pdf (last visited
`09/08/2022)
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`Document
`PCI Technology Overview (Feb. 2003)
`downloaded from
`https://web.archive.org/web/20040721012143/http://www.cs.unc.edu/
`Research/stc/FAQs/pci-overview.pdf (Wayback Machine
`(archive.org)) (last visited 09/08/2022)
`Deposition transcripts of Dr. Andrew Wolfe with errata (March 16-17,
`2023)
`Declaration of Dr. William Henry Mangione-Smith
`Markman Order, Netlist, Inc. v. Samsung Electronics Co., Ltd., Civ.
`Action 2:21-cv-00463-JRG, Dkt. 114 (E.D. Tex. filed Dec. 14, 2022)
`Samsung’s Objections to Claim Construction Memorandum Order,
`Netlist, Inc. v. Samsung Electronics Co., Ltd., Civ. Action 2:21-cv-
`00463-JRG, Dkt. 136 (E.D. Tex. filed Dec. 29, 2022)
`Bruce Jacob et al., Memory Systems: Cache, DRAM, Disk (2008)
`Netlist Presentation (excerpt)
`AgigA Tech et al., “NVDIMM Hands on Lab,” Flash Memory
`Summit 2014 (Aug. 5-6, 2014), downloaded from
`https://www.snia.org/sites/default/files/FMS%20NVDIMM%20Demo
`%20SIG%20HOL%20Aug’14%20final.pdf.
`Intel, Power Supply Design Guide for Desktop Platform Form
`Factors, Rev. 1.1 (March, 2007), downloaded from
`https://web.archive.org/web/20100601215705/http://www.formfactors
`.org/developer%5Cspecs%5CPSU_DG_rev_1_1.pdf
`Intel, ATX12V, Power Supply Design Guide, Version 2.2 (March
`2005), downloaded from
`https://web.archive.org/web/20070403181612/http://www.formfactors
`.org/developer/specs/ATX12V_PSDG_2_2_public_br2.pdf
`IDT, IDTAMB0480 Product Brief (“Advanced Memory Buffer for
`Fully Buffered DIMM Modules) (April 2006), downloaded from
`https://pdf1.alldatasheet.com/datasheet-
`pdf/view/199557/IDT/IDTAMB0480.html
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`Exhibit No.
`EX2029
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`EX2030
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`EX2031
`EX2032
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`EX2033
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`EX2034
`EX2035
`EX2036
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`EX2037
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`EX2038
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`EX2039
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`Document
`Ganesh, B. et. al., Fully-Buffer DIMM Memory Architectures:
`Understanding Mechanisms, Overheads and Scaling, HPCA2007
`Chang, K. K. et al., Understanding Reduced-Voltage Operation in
`Modern DRAM Chips: Characterization, Analysis, and Mechanisms,
`arXiv:1705.10292v1 [cs.AR] (May 29, 2017)
`Kingston Technology, KVR667D2D4F5/2G FBDIMM datasheet
`(4/14/06), downloaded from
`https://www.kingston.com/dataSheets/KVR667D2D4F5_2G.pdf.
`Samsung, Samsung Unveils New Power Management Solutions for
`DDR5 Modules, downloaded from
`https://semiconductor.samsung.com/newsroom/news/samsung-
`unveils-new-power-management-solutions-for-ddr5-modules/
`Micron, 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM
`RDIMM Features (2003), downloaded from https://media-
`www.micron.com/-/media/client/global/documents/products/data-
`sheet/modules/rdimm/htf9c32_64_128x72.pdf?rev=ca2587e210f1488
`9ad6fe88e3511e938
`Micron, 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Features (2008), downloaded from https://media-www.micron.com/-
`/media/client/global/documents/products/data-
`sheet/modules/sodimm/htf16c128_256_512x64hz.pdf?rev=2b5a70772
`1a24f4facccd8c86aaddfc7
`JEDEC Standard No. 21C, 4.20.11 – 200-Pin DDR2 SDRAM
`Unbuffered SO-DIMM Design Specification, Rev. 2.5 (Release 18)
`Smart Modular Technologies, SG5127FBD225652-SA FBDIMM
`Datasheet (March 20, 2007), downloaded from
`https://datasheet.ciiva.com/8371/sg5127fbd225652-sa-8371204.pdf
`Micron, 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB x72)
`Features (2005), downloaded from
`https://datasheet.octopart.com/MT18HTF12872FDY-667B5E3-
`Micron-datasheet-20608.pdf
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`Exhibit No.
`EX2040
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`EX2041
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`EX2042
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`EX2043
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`EX2044
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`EX2045
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`EX2046
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`EX2047
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`EX2048
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`Document
`Samsung Electronics, DDR2 Fully Buffered DIMM, 240pin FBDIMMs
`based on 1Gb C-Die, Rev. 1.52 (April 2008), downloaded from
`https://www.compuram.biz/documents/datasheet/143851ds_ddr2_1gb
`_c-die_based_fbdimm_rev152.pdf
`Texas Instruments, TPS51116 Datasheet (2008)
`Texas Instruments, Serial Presence Detect (1998), downloaded from
`http://www.ti.com/lit/pdf/smmu001
`Mikhaylov, K., Evaluation of Power Efficiency for Digital Serial
`Interfaces of Microcontrollers, 2012 5th Int’l Conference on New
`Technologies, Mobility and Security (NTMS)
`Dell Perc H700 G5V20 SAS PCIe x8 RAID Controller 1GB NV
`Cache Adapter (image)
`“TI ATI unveils next-generation 3-A DDR termination regulator,”
`downloaded from https://www.electronicproducts.com/ti-unveils-next-
`generation-3-a-ddr-termination-regulatorlinear-regulator-supports-
`ddr3-power-requirements-for/
`JEDEC, TG401_1, VR on DIMM TG Report (Dec. 2011)
`Deposition transcripts of Dr. Andrew Wolfe with errata (March
`January 4, 2023)
`Micron DDR5: Key Module Features, downloaded from https://media-
`www.micron.com/-/media/client/global/documents/products/technical-
`marketing-brief/ddr5_key_module_features_tech_brief.pdf?la=zh-
`tw&rev=f3ca96bed7d9427ba72b4c192dfacb56
`EPA, Report to Congress on Server and Data Center Energy
`Efficiency (Aug. 2, 2007), downloadable from
`https://www.osti.gov/servlets/purl/929723-4d6s1A/
`Intel, Fully Buffered DIMM Server Memory Architecture: Capacity,
`Performance, Reliability and Longevity (Feb. 18, 2004), downloaded
`from https://www.bestor.spb.ru/v3/Content/pdf/OSA_S008_FB-
`DIMM-Arch.pdf
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`Exhibit No.
`EX2049
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`EX2050
`EX2051
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`EX2052
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`EX2053
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`EX2054
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`EX2055
`EX2056
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`EX2057
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`EX2058
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`EX2059
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`Document
`Exhibit No.
`EX2101 Wolfe Deposition exhibit, FB-DIMM Design Considerations (Feb. 18,
`2004), downloaded from
`https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=e1c
`8e931ff9f54dc673973af4b1044daec6883e8
`EX2102 Wolfe Deposition exhibit, Linear Technology PCI Express Power and
`Mini Card Solutions
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`CLAIM CONSTRUCTION1
`Petitioner contends that “memory module” is not limited to “main memory2
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`I.
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`modules … designed to connect to the primary memory controller.” Reply 1. That
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`argument ignores the District Court’s finding based on intrinsic evidence—which
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`Samsung did not object to—that “the invention [i.e., the claimed memory module]
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`‘is couplable to a memory controller of a host system,’ ’918 Patent at 3:66–67 …,
`
`not just the host system as recited in the claims.” EX2032, 28 (emphasis in original);
`
`EX1001, 3:66-67 (“OVERVIEW Described herein is a memory module couplable
`
`to a memory controller of a host system”). Throughout the “OVERVIEW” as well
`
`the “Description of Example Embodiments,” the memory module is described
`
`consistently as a module coupled to and under the control of a host memory
`
`controller. EX1001, 4:5-12, 4:14-24, 4:35-39, 4:45-51, 5:4-20, 4:36-50, 6:4-6, 6:25-
`
`29, 6:61-66, 7:1-4, 7:21-25, 7:29-34, 7:43-49, 7:54-57, 21:24-25, 22:53-58, 23:19-
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`22, 26:43-51, 23:41-44.
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`1 Emphasis added unless otherwise noted.
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`2 “Main memory” is commonly known as RAM.
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`https://www.pcmag.com/encyclopedia/term/main-
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`memory#:~:text=Main%20memory%20is%20the%20primary,to%20the%20capaci
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`ty%20of%20RAM.
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`II. GROUNDS 1-3 (Reply 2-23)
`A. Harris+FBDIMM Does Not Disclose Receiving Power Via Edge
`Connections (Reply, 2-7)
`At institution, based on the facts at that time, the Board concluded “that
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`Harris’s external voltage source may be the host system ….” ID, 19-20. That
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`conclusion does not address whether power is supplied via the memory module’s
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`“edge connections,” as expressly required by the claims. Nor did the Board consider
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`additional evidence, including EX2031, ¶¶54-70.
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`Samsung argues that Harris’s reference to “externally supplied voltage”
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`means only “power ‘external’ to the DIMM memory module.” Reply, 2. If so,
`
`system board power supplies, external to FBDIMMs, would also provide externally
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`supplied voltages. But Harris associates “external voltage source[s]” only with
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`voltage supplies to its modified FBDIMM having no “power supply interface pins,”
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`and never with system board power supplies. EX1023, Figs. 1A-1B (external
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`voltage source from side), [0003], [0010]-[0012], [0016], cl. 1. Thus, “external
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`voltage source[s]” do not include system board power supplies and thus do not
`
`supply power via the edge connections as required by the claims.
`
`Samsung makes a strawman argument that “Netlist does not dispute that the
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`FBDIMM Standards … teach supplying power via edge connections,” (Reply 2; see
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`also Reply 5-6), but Grounds 1-3 do not rely on a standard FBDIMM powered by
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`system board power supplies. They rely on Harris’s modified FBDIMM that
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`replaces its “power supply interface pins with as few as six +12V pins (from an
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`external voltage source).” Pet. 21-22, 50-51, 71, 75-77; EX1023, [0012]. As
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`explained in the POR, the new 12V pins are not on the FBDIMM’s edge connections.
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`POR 3-11; EX1023, [0012], [0019]-[0020]; EX2031, ¶59. Notably, Harris does not
`
`describe the “+12V pins” as “interface pins.” Id.
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`
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`Harris, Figure 3, confirms that “external voltage source[s]” are not supplied
`
`to FBDIMMs from edge connections. The figure shows a “bidirectional memory
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`link” to memory controller via edge connections, but does not “explicitly show…
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`each memory board also receives a supply voltage ….” EX1023, [0017]; EX2031,
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`¶60; contra Reply 4. That description would make no sense if voltages were
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`supplied via the edge connections (including if supplied by the “memory controller
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`302”),3 as both memory controller 302 and edge connectors are explicitly shown.
`
`POR 8. Thus, even if in normal DIMMs, “[t]he motherboard supplies the voltage
`
`for DIMM alongside the memory controller signals,” that does not speak to what
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`would happen in Harris’s modified FBDIMMs. EX2030, 103:25-131:5.
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`
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`Netlist also does not assert that “all power” is eliminated: the 12V power is
`
`supplied, albeit not from the edge connections. EX2031, ¶¶59-60; contra Reply 5.
`
`Dr. Wolfe testified that the “system board power supply that is being eliminated”
`
`refers to “supplies such as the memory VDD and the memory VCC that are specific
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`3 The experts agree that memory controllers were not known as power supplies to
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`DIMMs. EX2030, 1030:19-131:10; EX2031, ¶67.
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`to a particular generation of memory chips.” EX2030, 116:10-117:6. That
`
`testimony, Harris and the Petition, however, do not suggest further providing a 12V
`
`power plane to the DIMM’s interface. EX1023, [0002]-[0003], [0012]-[0013],
`
`[0019]; EX2031, ¶58.
`
`Nor does Harris’s disclosure of “connector keyway” indicate that the 12V is
`
`supplied from the edge connection. Contra Reply 5-6. Keying is “to make sure that
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`you couldn’t insert the wrong DIMM into a slot that didn’t match or support it.”
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`EX1075, 172:8-1. In Harris, by removing “power supply interface pins,” a non-
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`standard DIMM is formed and a different keyway can prevent it from being plugged
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`“into a motherboard that was not aware that the functionality of certain pins had
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`changed.” EX2030, 117:13-21; EX1023, [0013]. But that does not mean the 12V
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`pins are added to the edge connection. The PCI references are also inapposite
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`because “[t]he signaling voltage [shown] and the power voltage [at issue] are not
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`related.” EX2016, 8.
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`Samsung does not dispute that receiving power from a side/top of the memory
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`module was known, but argues in Reply that this state of the art “would not negate
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`the obviousness of using edge connections for power, as was highly common.”
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`Reply 6-7. In the prior art, when power was supplied from the edge, the system
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`board provided the power supplies and associated power planes. Harris, however,
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`refers to its 12V voltage source as an “external voltage source,” which as explained
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`above, is not associated with power supplies from system board. Harris, [0012],
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`[0019]. Petitioner has not provided any evidence that in such cases, power could
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`continue to be supplied from a DIMM’s edge connections.
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`This is significant because the Petition does not suggest further modifying
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`Harris’s FIGs. 1A-1B by providing an “external voltage source” from the edge
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`connections instead of side connections. Pet., 21-22; POR, 5. Samsung may not
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`reformulate its challenge now. Thus, Samsung must show that Harris expressly or
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`inherently discloses a memory module receiving power via its edge connections.
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`Samsung has not made such a showing, or even that it would be obvious, given
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`Harris’s rejection of conventional approaches by eliminating system-board-specific
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`power supply and associated power planes, in order to improve upgradeability and
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`extensibility, and to lower costs. EX1023, [0002], [0019]-[0020]; EX2031, ¶¶26-
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`27, 58, 61-62, 68.
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`B. Harris Does Not Disclose Receiving “data, address, and control
`signals” from the Host (Reply, 7-9)
`The Petition argues that Harris’s Buffer 112 receives data, address and control
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`signals respectively as DQ0-DQ63, A0-A15 and RAC, CAS, WE, CS signals. Pet.
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`22-23:
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`The POR points out those are signals generated and outputted by the buffer,
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`and not ones received from the DIMM interface. POR 11-15; EX2031, ¶¶72-74.
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`The Reply does not deny that, arguing instead that “signals received by the AMB on
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`the FBDIMM result in ‘data, address, and control signals needed by the DDR2
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`SDRAM.’” Reply 8-9. But the claims require an “interface including a plurality of
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`edge connections configured to couple … data, address and control signals between
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`the memory module and the host system.” EX1001, 38:22-24, 39:56:59, 40:53-56.
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`In the inventions, the DIMM interface “provides a conduit for … data, address, and
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`control signals” between the host and the memory module. See EX1001, 22:1-6.
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`FBDIMMs do not do that (see illustration above); instead, Dr. Wolfe
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`associates “data, address, and control signals” with the outputs from the AMB and
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`characterizes that is received as “information.” EX1003, ¶230; EX2030, 7:20-11:6
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`(Dr. Wolfe acknowledging that “address command bits” and “data and data strobe
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`signals” he relied on are “the output on the DDR I/O side,” and “information” to and
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`from FBDIMMs is carried “over the northbound and southbound links in an encoded
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`form”). The claims, however, require specific “signals,” and not just “information,”
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`be coupled between the host and the memory module. EX1001, 1.b., 16.b, 23.b.
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`The AMB outputs are not transmitted over FBDIMM’s edge connections.
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`Netlist is not rewriting the claims to require “dedicated pins.” Contra Reply
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`8-9. Rather, the pin names indicate what “signals” are exchanged at the interface
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`between the host and the FBDIMM, as shown below. EX1027, p.4.
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`
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`Samsung’s other strawman arguments also fail. First, that “[a]ll memory
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`control for the DRAM resides in the host” and the AMB buffers “all read, write,
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`and configuration accesses addressed to the DIMM” does not undermine the fact
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`that in an FBDIMM, the relied on signals are generated and outputted by the
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`buffer, and not exchanged at the interface between the FBDIMM and the host.
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`EX2030, 7:20-11:6; EX2030, ¶230.
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`Second, while FBDIMM is an example “compatible with certain
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`embodiments described herein, (EX1001, 21:38-55), the claims need not
`
`encompass it. Maxwell v. J. Baker, Inc., 86 F.3d 1098, 1107 (Fed. Cir. 1996)
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`(recognizing “disclosed but unclaimed subject matter”). Indeed, the patent does
`
`not describe FBDIMM as including a recited interface configured to couple the
`
`enumerated signals between the host and the memory devices. EX1001, 21:38-55.
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`Third, consistent with Dr. Wolfe’s and Dr. Mangione-Smith’s testimony,
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`Netlist’s technology tutorial shows that information encoding data, address and
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`control—as opposed to the recited “data, address and control signals”—is received
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`at the DIMM interface. Reply 7-8.
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`Thus, Samsung has not established that Grounds 1-3 disclose or suggests
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`elements 1.b., 16.b, 23.b or claims 8 and 24.
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`C. A POSITA Would Not Have Used Four Converters in Grounds 1-
`3 (Reply, 9-18)
`1. Harris Uses a Single Converter to Provide Multiple Different
`Voltages (Reply, 10-13)
`Even if “buck converters were well-known switching devices commonly used
`
`to step down an input voltage to a lower output voltage,” it does not follow that it
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`would have been obvious to use as many buck converters as possible, especially
`
`given that Harris expressly discloses a switching regulator outputting multiple
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`voltage levels, consistent with the state of art. Contra Reply 10; EX1023, [0010];
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`EX2020, p.5, Table 1-1. Samsung has not articulated any advantage of using one
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`converter per voltage if Harris already uses a single converter for at least two
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`voltages. Reply 10-13; EX1023, [0010].
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`Samsung disputes Dr. Mangione-Smith’s testimony that Harris’s reference to
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`“a high-frequency switching voltage converter” means a single converter. Reply 11;
`
`EX2031, ¶¶79-80. Samsung argues that “a” means “one or more” in patent parlance.
`
`Reply 13. But that principle applies to “open-ended claims,” not patent
`
`specifications. See Baldwin Graphic Sys., Inc. v. Siebert, Inc., 512 F.3d 1338, 1342-
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`43 (Fed. Cir. 2008). When Harris meant there to be multiple VRMs, he said so.
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`EX1023, [0014] (describing “[a] plurality of on-board VRMs ….”); FIG. 1B (block
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`122-K labeled “Voltage Regulator Modules”).4
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`There are good reasons why a POSITA would have minimized the number of
`
`buck converters. For example, while “space” is not a claim element, it is relevant to
`
`determining whether the claims are obvious under Petitioner’s unpatentability
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`theory. Contra Reply 13; Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821
`
`F.3d 1359, 1368 (Fed. Cir. 2016) (shortcoming not relevant to demonstrating
`
`
`4 Harris’s claims recite “at least one voltage regulator module,” consistent with its
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`Figure 1B embodiment with multiple VRMs for multiple voltage sources, each
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`VRM generating multiple voltages.
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`whether claimed inventions could be met was relevant to motivation to combine).
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`Harris discloses accommodating the VRM for a 2-rank FBDIMM in a 1 square-inch
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`space (both sides). Harris, [0013]. Petitioner’s own evidence shows that each
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`converter package would be about 0.193" by 0.236", with LC filter and other
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`peripheral components occupying multiples of that area. EX1078, 20-23 (below).
`
`Petitioner has not shown that four such assemblies, as proposed, could fit in the
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`allocated area or the spare area of FBDIMM in general. See below; EX2101, pp.22,
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`25-26.
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`Independent voltage sources for different voltages would also require specific
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`control circuitry to delay and more precisely control each voltage source’s ramping
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`rate, adding complexity and cost without commensurate benefits. EX2031, ¶90.
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`Samsung attempts to analogize Harris’ VRM with the ’918 patent’s dual buck
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`converter. Reply 12. Harris does not characterize its “high-frequency switching
`
`voltage converter” as a “dual” converter. EX1023, FIG. 1A, [0010]. And the ’918
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`patent makes clear that a “dual buck converter” comprises two buck converters, e.g.,
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`“the first and third buck converters.” EX1001, 38:53-55.
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`Similarly, EX1048’s inclusion of two buck converters in its “DC-DC
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`Converter” does not show that Harris’s “switching voltage converter” also has
`
`multiple buck converters. This is because (1) EX1048 is a “DRAFT” which may
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`include typos; (2) EX1048 confirms that one buck converter (in green box below)
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`can generate two output voltages (Vout2, Vout3) from one input voltage (Vin),
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`consistent with other evidence showing the same (EX1075, 223:11-22; EX2020, p.5,
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`Table 1-1; EX2003, EX2004);5 (3) Samsung hasn’t established that Harris uses the
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`DC-DC Converter of EX1048,6 or that it is industry convention to describe dual
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`converters as a single converter.
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`
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`5 A buck converter needs “an LC-filter just after the power switch ….” EX2020,
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`p.22. Thus, the number of inductors reflects the number of buck converters. See
`
`EX1078, 12 (LC filter); EX1075, 129:13-19 (EX1048, p.2 shows two buck
`
`converters, each with an inductor); contra Reply 12.
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`6 MPD4S014S, designed for input voltages up to 13.2V (EX1048, 2), is unsuitable
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`for Harris’s 12V input having a ±15% tolerance (i.e., 10.2–13.8V).
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`Given the state of the art, a PSOITA would have understood that Harris’s
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`reference to “a high-frequency switching voltage converter capable of generating
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`tightly-controlled voltage levels” means a single converter with multiple outputs, not
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`multiple converters. EX2031, ¶¶79-80.
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`2.
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`Samsung’s Argument That Using Different Converters for
`Voltages Having Different Functions is Improper and
`Unsupported (Reply, 13-15)
`Samsung argues that it was obvious to use different converters for
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`VDD/VDDL/VDDQ because the JEDEC specification for SDRAM devices7—as
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`opposed to the specification for FBDIMM—has an “option” that treated them
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`individually. Reply 13-14. But Grounds 1-3 propose modification starting from a
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`standard FBDIMM, which generates VDD/VDDL/VDDQ from VDD pins and
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`generates VCC/VCCFBD from VCC pins. See EX1028 at 11-12; EX2031, ¶87;
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`POR 21-22; EX2101, p.27 (no separate regulators for 1.8V or 1.5V); see also
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`EX2031, ¶¶ 88-90, 93; POR, 23-24 (reasons why a single converter for
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`VDD/VDDL/VDDQ).
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`7 EX1026 and EX1046 are SDRAM device specification, not DIMM
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`specifications.
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`That is, standard FBDIMMs already have circuits that can generate the needed
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`VDD/VDDQ/VDDL (or VCC/VCCFBD) from a single 1.8V (1.5V) power source. See
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`illustration below. Petitioner provides no reason why, starting from a standard
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`FBDIMM, a POSITA would have ignored those existing circuits and used multiple
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`converters instead. POR 22.
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`Standard FBDIMM
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`Harris’s FBDIMM
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`In fact
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