throbber

`
`Paper No. 25
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`v.
`NETLIST, INC.,
`Patent Owner
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`
`
`PETITIONER’S REPLY
`TO PATENT OWNER’S RESPONSE
`
`
`
`
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`
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`

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`
`
`I.
`II.
`
`TABLE OF CONTENTS
`
`Page
`INTRODUCTION ........................................................................................... 1
`ARGUMENT ................................................................................................... 1
`A.
`There was no improper incorporation by reference (POR 1) ............... 1
`B.
`Construction of “memory module” (POR 1-3) ..................................... 1
`C.
`Grounds 1-3 (POR 3-44) ....................................................................... 2
`1.
`Ground 1 (Harris+FBDIMM Standards) discloses edge
`connections to receive power from the host system (POR 3-
`11) ............................................................................................... 2
`Harris discloses receiving “data, address, and control
`signals” from the host (POR 11-15) ........................................... 7
`Harris and the FBDIMM Standards render obvious using
`four converters (POR 15-31) ...................................................... 9
`a)
`Harris is not limited to one or two buck converters
`(POR 17-21) ....................................................................10
`It was obvious to use different converters for voltages
`that have different functions (POR 21-27) .....................13
`It was obvious to use a third buck converter for VTT
`(POR 27-30) ....................................................................15
`It was obvious to use a buck converter for VDDSPD
`(POR 30-31) ....................................................................18
`It was obvious to combine Amidi’s battery backup with
`Harris (POR 31-38) ...................................................................18
`Grounds 1-3 disclose “pre-regulated input voltage” (POR
`38) .............................................................................................20
`Overvoltage protection in claims 5, 16, 24 and dependents
`(POR 38-42) ..............................................................................20
`Non-volatile memory for claims 10-11, 15, 22 (POR 43) ........23
`7.
`8. Write operation for claims 11-12, 18-19, 25-26 (POR 43-
`44) .............................................................................................23
`D. Grounds 4-5 (POR 44-76) ...................................................................23
`1.
`Spiers’s PCI card is a “memory module” (POR 44-48) ............23
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`b)
`
`c)
`
`d)
`
`
`
`ii
`
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`
`

`

`
`
`2.
`
`3.
`
`b)
`
`Spiers+Amidi renders obvious four regulated voltages
`(POR 48-59) ..............................................................................26
`a)
`Spiers is not limited to older SDR SDRAM memory
`(POR 48-52) ....................................................................26
`It would be obvious to use newer, more efficient
`DDR2/DDR3 memory (POR 53-69) ..............................27
`It would be obvious to use four buck converters with
`Spiers+Amidi (POR 60-69) ......................................................29
`a)
`Buck converter for VTT (POR 60-63) .............................29
`b) Multiple 1.8V buck converters (POR 63-64) .................30
`c)
`Two buck converters for 1.5V and 1.8V (POR 64-65) ..30
`d)
`Buck converter for 5V-to-3.3V (POR 65-69) ................31
`Grounds 4-5 disclose pre-regulated input voltage (POR 69-
`71) .............................................................................................33
`Claim 23 (POR 71-72) ..............................................................33
`Claim 13 (POR 72-73) ..............................................................34
`Claims 5-7, 9-13, 16-22, 24-27 (POR 73-75) ...........................35
`Registered plurality of C/A signals for claims 8, 14 (POR
`75-76 .........................................................................................37
`III. CONCLUSION ..............................................................................................37
`
`
`4.
`
`5.
`6.
`7.
`8.
`
`
`
`iii
`
`
`
`

`

`
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`Baldwin Graphic Sys., Inc. v. Siebert, Inc.,
`512 F.3d 1338 (Fed. Cir. 2008) ............................................................................11
`Dome Pat. L.P. v. Lee,
`799 F.3d 1372 (Fed. Cir. 2015) ................................................................. 7, 18, 30
`Intel Corp. v. PACT XPP Schweiz AG,
`61 F.4th 1373 (Fed. Cir. 2023) ...................................................................... 29, 30
`Intel Corp. v. Qualcomm Inc.,
`21 F.4th 784 (Fed. Cir. 2021) ...............................................................................28
`Kaufman v. Microsoft Corp.,
`34 F.4th 1360 (Fed. Cir. 2022) ............................................................................... 9
`
`
`
`
`
`iv
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`EXHIBIT LIST
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`U.S. Patent No. 11,016,918
`
`File History of U.S. Patent No. 11,016,918
`
`Declaration of Dr. Andrew Wolfe
`
`Curriculum Vitae of Dr. Andrew Wolfe
`
`File History of U.S. Provisional Application No. 60/941,586
`
`File History of U.S. Patent Application No. 12/131,873
`
`File History of U.S. Patent Application No. 12/240,916
`
`File History of U.S. Provisional Application No. 61/512,871
`
`File History of U.S. Patent Application No. 13/559,476
`
`File History of U.S. Patent Application No. 14/489,269
`
`File History of U.S. Patent Application No. 14/840,865
`
`File History of U.S. Patent Application No. 15/934,416
`
`[Intentionally Omitted]
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 1 (PTAB
`June 20, 2014) (833 Patent IPR Petition)
`
`SanDisk Corp. v. Netlist, Inc., IPR2014-00994, Paper No. 8 (PTAB
`Dec. 16, 2014) (833 Patent Institution Decision)
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 8 (PTAB Sept. 22, 2014) (833 Patent IPR Corrected Petition)
`
`Smart Modular Techs. Inc. v. Netlist, Inc., IPR2014-01370, Paper
`No. 13 (PTAB Mar. 13, 2015) (833 Patent Institution Decision)
`
`v
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`1018
`
`1019
`
`1020
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 1
`(PTAB Jan. 13, 2017) (833 Patent IPR Petition)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00649, Paper No. 7
`(PTAB July 24, 2017) (833 Patent Institution Decision)
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 1
`(PTAB Jan. 17, 2017) (831 Patent IPR Petition)
`
`1021
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper No. 25
`(PTAB July 5, 2018) (831 Patent Final Written Decision)
`1022 Micron Tech., Inc. et al. v. Netlist, Inc., IPR2022-00418, Paper No. 2
`(PTAB Jan. 14, 2022) (833 Patent IPR Petition)
`
`1023
`
`U.S. Patent Application Publication No. 2006/0174140 to Harris et
`al.
`
`1024
`
`U.S. Patent No. 7,724,604 to Amidi et al.
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`U.S. Patent Application Publication No. 2006/0080515 to Spiers et
`al.
`
`JEDEC Standard, DDR2 SDRAM Specification, JESD79-2B
`(January 2005) (“JESD79-2B”)
`
`JEDEC Standard, FBDIMM: Advanced Memory Buffer (AMB),
`JESD82-20 (March 2007) (“JESD82-20”)
`
`JEDEC Standard, FBDIMM Specification: DDR2 SDRAM Fully
`Buffered DIMM (FBDIMM) Design Specification, JESD205 (March
`2007) (“JESD205”)
`
`Declaration of Julie Carlson for JESD82-20 and JESD205
`
`U.S. Patent No. 7,719,866 to Boldo
`
`PCI Local Bus Specification Revision 2.2 (1998)
`
`vi
`
`
`
`

`

`
`
`
`
`Exhibit #
`Description
`1032 Mohan et al., Power Electronics: Converters, Applications, and
`Design (2d ed. 1995)
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`U.S. Patent No. 7,721,130 to Prete et al.
`
`U.S. Patent No. 6,798,709 to Sim et al.
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0238536 to Hayashi et
`al.
`
`1038
`
`U.S. Patent No. 6,856,556 to Hajeck
`
`1039
`
`U.S. Patent Application Publication No. 2010/0257304 to Rajan et
`al.
`
`1040
`
`Texas Instruments, TPS51020 Datasheet (December 2003)
`
`1041
`Fairchild Semiconductor, FAN5026 Datasheet (October 2005)
`1042 Murata Power Supply Reference Guide for Xilinx FPGAs
`(September 2006)
`1043 Murata Power Supply Reference Guide for Altera FPGAs (February
`2008)
`
`1044
`
`1045
`
`1046
`
`U.S. Patent Application Publication No. 2010/0205470 to Moshayedi
`et al.
`
`JEDEC Standard, Double Data Rate (DDR) SDRAM Specification,
`JESD79 (June 2000) (“JESD79”)
`
`JEDEC Standard, DDR3 SDRAM, JESD79-3A (September 2007)
`(“JESD79-3A”)
`
`1047
`
`U.S. Patent No. 7,023,187 to Shearon et al.
`
`vii
`
`
`
`

`

`
`
`
`
`Exhibit #
`Description
`1048 Murata, DC-DC Converter Specification (DRAFT), MPD4S014S
`Datasheet (Jan. 21, 2008)
`
`1049 Micron, NAND Flash Memory Datasheet (January 2006)
`
`1050
`
`1051
`
`1052
`
`1053
`
`1054
`
`1055
`
`1056
`
`1057
`
`1058
`
`1059
`
`1060
`
`1061
`
`1062
`
`1063
`
`1064
`
`U.S. Patent No. 7,692,938 to Petter
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`[Intentionally Omitted]
`
`U.S. Patent Application Publication No. 2008/0101147 to Amidi
`
`U.S. Patent No. 5,563,839 to Herdt et al.
`
`U.S. Patent No. 6,693,840 to Shimada et al.
`
`Lenk, John D., Simplified Design of Switching Power Supplies
`(1995)
`
`U.S. Patent No. 7,061,214 to Mayega et al.
`
`U.S. Patent No. 5,630,096 to Zuravleff et al.
`
`Analog Devices, ADM1066 Datasheet (2006)
`
`Alan Moloney, Power-Supply Management—Principles, Problems,
`and Parts, Analog Dialogue (May 2006)
`
`National Semiconductor, LMC6953 PCI Local Bus Power
`Supervisor Datasheet (October 1996)
`
`U.S. Patent Application Publication No. 2007/0136523 to Bonella et
`al.
`
`1065
`
`U.S. Patent Application Publication No. 2009/0034354 to Resnick
`
`viii
`
`
`
`

`

`
`
`
`
`Exhibit #
`
`Description
`
`1066
`
`1067
`
`1068
`
`1069
`
`1070
`
`1071
`
`1072
`
`1073
`
`1074
`
`U.S. Patent No. 10,672,458 to Shaeffer et al.
`
`LatticeXP Family Data Sheet (March 2006)
`
`Complaint for Declaratory Judgment of Non-Infringement and
`Unenforceability; Breach of Contract, Samsung Electronics Co., Ltd.
`et al. v. Netlist, Inc., No. 1:21-cv-01453 (D. Del. filed Oct. 15, 2021)
`
`First Amended Complaint for Declaratory Judgment of Non-
`Infringement and Unenforceability; Breach of Contract, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Jan. 18, 2022)
`
`Netlist’s motion to dismiss the First Amended Complaint, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., No. 1:21-cv-01453 (D.
`Del. filed Feb. 16, 2022)
`
`Complaint in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Dec. 20, 2021)
`
`Answer in Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Apr. 12, 2022)
`
`Amended Complaint in Netlist, Inc. v. Samsung Electronics Co., Ltd.
`et al., No. 2:21-cv-00463 (E.D. Tex. filed May 3, 2022)
`
`Email from counsel for Samsung to counsel for Patent Owner re:
`stipulation not to pursue certain invalidity defenses if an IPR
`proceeding is instituted
`
`1075
`[NEW]
`
`1076
`[NEW]
`
`Transcript of deposition of William Mangione-Smith, Ph.D. (June
`12, 2023)
`
`Redline comparing Dr. Mangione-Smith’s declaration in IPR2022-
`00996 (EX2031) to his declaration in IPR2022-00999 (EX2061)
`
`1077
`[NEW] Netlist’s Technology Tutorial
`
`ix
`
`
`
`

`

`
`
`
`
`
`
`
`Exhibit #
`
`Description
`
`1078
`[NEW] Datasheet for ADP1821 Step-Down DC-to-DC Controller
`
`
`
`x
`
`
`
`

`

`
`
`
`
`CLAIM LISTING
`
`Ref. #
`1.a
`
`1.b
`
`1.c
`
`1.d
`
`1.e
`
`1.f
`
`1.g
`
`1.h
`
`1.i
`
`2
`
`Listing of Challenged Claims
`1. A memory module comprising:
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`a first buck converter configured to provide a first regulated voltage
`having a first voltage amplitude;
`a second buck converter configured to provide a second regulated
`voltage having a second voltage amplitude;
`a third buck converter configured to provide a third regulated voltage
`having a third voltage amplitude;
`a converter circuit configured to provide a fourth regulated voltage
`having a fourth voltage amplitude; and
`a plurality of components coupled to the PCB, each component of the
`plurality of components coupled to one or more regulated voltages of
`the first, second, third and fourth regulated voltages, the plurality of
`components comprising:
`a plurality of synchronous dynamic random access memory (SDRAM)
`devices coupled to the first regulated voltage, and
`[1] at least one circuit coupled between a first portion of the plurality of
`edge connections and the plurality of SDRAM devices,
`[2] the at least one circuit operable to (i) receive a first plurality of
`address and control signals via the first portion of the plurality of edge
`connections, and (ii) output a second plurality of address and control
`signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated voltage
`and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`2. The memory module of claim 1, wherein the first and third buck
`converters are further configured to operate as a dual buck converter.
`
`xi
`
`
`
`

`

`
`
`
`
`Ref. #
`3
`
`4
`5.a
`
`5.b
`
`6
`
`7
`
`8.a
`
`8.b
`
`9
`
`10.a
`
`10.b
`
`Listing of Challenged Claims
`3. The memory module of claim 1, wherein the first voltage amplitude
`is 1.8 volts.
`4. The memory module of claim 1, wherein the second, third, and fourth
`voltage amplitudes are 2.5 volts, 1.2 volts, and 3.3 volts, respectively.
`5. The memory module of claim 1, further comprising:
`a voltage monitor circuit configured to monitor a power input voltage
`received via a second portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a trigger signal in
`response to the power input voltage having a voltage amplitude that is
`greater than a first threshold voltage.
`6. The memory module of claim 5, wherein the voltage monitor circuit
`is further configured to produce the trigger signal in response to the
`power input voltage having a voltage amplitude that is less than a
`second threshold voltage.
`7. The memory module of claim 6, wherein the second threshold voltage
`corresponds to a voltage level that is ten percent less than a specified
`operating voltage.
`8. The memory module of claim 1, the plurality of components further
`comprising:
`[1] one or more registers coupled to one of the first, second, third and
`fourth regulated voltages,
`[2] the one or more registers configured to register, in response to a
`clock, the first plurality of address and control signals,
`[3] wherein the one of the first, second, third and fourth regulated
`voltages is selectively switched off to turn power off to the one or more
`registers while one or more components of the plurality of components
`are powered on.
`9. The memory module of claim 5, wherein the first threshold voltage
`corresponds to a voltage level that is ten percent greater than a specified
`operating voltage.
`The memory module of claim 5, the plurality of components further
`comprising:
`a logic element including a non-volatile memory, the non-volatile
`memory is configured to store configuration information.
`
`xii
`
`
`
`

`

`
`
`
`
`Ref. #
`
`11
`
`12.a
`12.b
`
`12.c
`
`13
`
`14
`
`15.a
`
`15.b
`
`Listing of Challenged Claims
`11. The memory module of claim 10, wherein, in response to the trigger
`signal, the logic element writes information into the non-volatile
`memory.
`12. The memory module of claim 5, the plurality of components further
`comprising:
`a non-volatile memory; and
`a controller configured to receive the trigger signal, wherein, in
`response to the trigger signal, the controller performs a write operation
`to the non-volatile memory.
`13. The memory module of claim 5, wherein the power input voltage is
`coupled to the first, second, and third buck converters and the converter
`circuit.
`14. The memory module of claim 8, wherein, in response to selectively
`switching on the one of the first, second, third and fourth regulated
`voltages to the one or more registers, the one or more registers is
`configured to output the registered first plurality of address and control
`signals to the plurality of SDRAM devices.
`15. The memory module of claim 1, the plurality of components further
`comprising:
`a logic element including one or more integrated circuits and discrete
`electrical elements, the one or more integrated circuit including an
`internal non-volatile memory, wherein the non-volatile memory is
`configured to store configuration information.
`16.a A memory module comprising:
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`first, second, and third buck converters configured to receive a pre-
`regulated input voltage and to produce first, second and third regulated
`voltages, respectively;
`
`16.b
`
`16.c
`
`xiii
`
`
`
`

`

`
`
`
`
`Ref. #
`
`16.d
`
`16.e
`
`16.f
`
`17
`
`18.a
`
`18.b
`
`19
`
`20
`
`21.a
`
`Listing of Challenged Claims
`[1] a converter circuit configured to reduce the pre-regulated input
`voltage to provide a fourth regulated voltage,
`[2] wherein the first, second, third and fourth regulated voltages have
`first, second, third, and fourth voltage amplitudes, respectively;
`a plurality of components coupled to the PCB, the plurality of
`components including a plurality of synchronous dynamic random
`access memory (SDRAM) devices, each component of the plurality of
`components coupled to one or more regulated voltages of the first,
`second, third and fourth regulated voltages; and
`a voltage monitor circuit configured to monitor an input voltage
`received via a first portion of the plurality of edge connections, the
`voltage monitor circuit configured to produce a signal in response to the
`input voltage having a voltage amplitude that is greater than a first
`threshold voltage.
`17. The memory module of claim 16, wherein the second and third buck
`converters are configured to operate as a dual buck converter.
`18. The memory module of claim 16, the plurality of components
`further including:
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein the controller executes a write operation in
`response to the signal.
`19. The memory module of claim 18, wherein the write operation
`includes writing data information into non-volatile memory.
`20. The memory module of claim 16, wherein the plurality of SDRAM
`devices are configured to receive at least one of the first, second, third
`and fourth regulated voltages having a voltage amplitude of 1.8 volts.
`21. The memory module of claim 16, the plurality of components
`further including:
`
`xiv
`
`
`
`

`

`
`
`
`
`Ref. #
`
`21.b
`
`Listing of Challenged Claims
`[1] at least one circuit coupled between the interface and the plurality of
`SDRAM devices,
`[2] the at least one circuit operable to receive a first plurality of address
`and control signals via a second portion of the plurality of edge
`connections and to output a second plurality of address and control
`signals to the plurality of SDRAM devices,
`[3] the at least one circuit coupled to both the second regulated voltage
`and the fourth regulated voltage,
`[4] wherein a first one of the second and fourth voltage amplitudes is
`less than a second one of the second and fourth voltage amplitudes.
`22. The memory module of claim 16, the plurality of components
`further including:
`a logic element including an internal non-volatile memory, wherein the
`non-volatile memory is configured to store configuration information,
`wherein the configuration information is used to program the logic
`element.
`23.a A memory module comprising:
`
`a printed circuit board (PCB) having an interface configured to fit into
`a corresponding slot connector of a host system, the interface including
`a plurality of edge connections configured to couple power, data,
`address and control signals between the memory module and the host
`system;
`[1] a plurality of components coupled to the PCB, each component of
`the plurality of components coupled to one or more regulated voltages
`of first, second, third and fourth regulated voltages,
`[2] the plurality of components including a plurality of synchronous
`dynamic random access memory (SDRAM) devices and one or more
`registers, the plurality of SDRAM devices coupled to the first regulated
`voltage, the one or more registers coupled to (i) the second regulated
`voltage, (ii) a portion of the plurality of edge connections, and (iii) the
`plurality of SDRAM devices,
`[3] wherein a plurality of address and control signals are coupled to the
`one or more registers via the portion of the plurality of edge
`connections;
`first, second, and third buck converters configured to provide the first,
`second and third regulated voltages, respectively; and
`
`22.a
`
`22.b
`
`23.b
`
`23.c
`
`23.d
`
`xv
`
`
`
`

`

`
`
`
`
`Ref. #
`23.e
`
`23.f
`
`23.g
`
`23.h
`
`24.a
`
`24.b
`
`25.a
`
`25.b
`
`26
`
`27
`
`28
`
`29
`
`Listing of Challenged Claims
`a converter circuit configured to provide the fourth regulated voltage,
`wherein the second regulated voltage is configured to be selectively
`switched on or off to the one or more registers while at least the plurality
`of SDRAM devices are powered on,
`wherein if the second regulated voltage is switched on while at least the
`plurality of SDRAM devices are powered on, the one or more registers
`are configured to couple the first plurality of address and control signals
`to the plurality of SDRAM devices, and
`wherein if the second regulated voltage is switched off while the
`plurality of SDRAM devices are powered on, the one or more registers
`are configured to decouple the plurality of SDRAM devices from the
`first plurality of address and control signals.
`24. The memory module of claim 23, further comprising:
`a voltage monitor circuit configured to monitor an input voltage
`received from the host system via the interface, the voltage monitor
`circuit configured to produce a signal in response to the input voltage
`having a voltage amplitude that is greater than a first threshold voltage.
`25. The memory module of claim 24, the plurality of components
`further including:
`a controller coupled to the voltage monitor circuit and configured to
`receive the signal, wherein, in response to the signal, the controller
`executes a write operation.
`26. The memory module of claim 25, wherein the write operation
`includes writing data information to non-volatile memory.
`27. The memory module of claim 24, wherein the voltage monitor
`circuit is further configured to produce the signal in response to the
`input voltage having a voltage amplitude that is less than a second
`threshold voltage.
`28. The memory module of claim 23, wherein the second and third buck
`converters are configured to operate as a dual buck converter.
`29. The memory module of claim 23, wherein the plurality of SDRAM
`devices are configured to receive at least one of the first, second, third
`and fourth regulated voltages having a voltage amplitude of 1.8 volts.
`
`xvi
`
`
`
`

`

`
`
`
`
`
`
`Ref. #
`
`30
`
`Listing of Challenged Claims
`30. The memory module of claim 23, wherein the first, second, and third
`buck converters are configured to receive a pre-regulated input voltage
`and to provide the first, second and third regulated voltages,
`respectively, and wherein the converter circuit is configured to reduce
`the pre-regulated voltage input to provide the fourth regulated voltage.
`
`xvii
`
`
`
`

`

`
`
`I.
`
`INTRODUCTION
`The Institution Decision (“ID”) correctly found all claims obvious. Netlist’s
`
`Patent Owner Response (“POR”) repeats many of the arguments that the ID already
`
`rejected.
`
`II. ARGUMENT
`A. There was no improper incorporation by reference (POR 1)
`The Petition did not “improperly incorporat[e]” from the expert declaration,
`
`POR 1, but rather provided cross references within the Petition for later limitations
`
`that were nearly identical to earlier limitations and thus “obvious for at least the
`
`same reasons above,”1 Pet. 50-51, 70-73, 123-26.
`
`B. Construction of “memory module” (POR 1-3)
`The Board properly found that Harris, the FBDIMM Standards, Amidi, and
`
`Spiers all disclose a “memory module,” ID 14-15, 17-18, 34-37, 45, as explained
`
`by the Petition, Pet. 19-20, 82-83; see also infra pp.23-26. After institution, the
`
`District Court held that “memory module” in the preamble is “[l]imiting,” EX2032,
`
`35, consistent with the Board’s assumption, ID 18 n.2. Contrary to Netlist’s
`
`suggestion, neither the District Court nor Dr. Wolfe further limited “memory
`
`module” to only “main memory modules…designed to connect to the primary
`
`memory controller,” POR 2. See EX2032, 26-28, 35; EX2030, 125:12-127:13;
`
`
`1 Unless otherwise noted, emphases are added and internal quotes are omitted.
`
`1
`
`

`

`
`
`EX2056, 100:15-101:19.
`
`C. Grounds 1-3 (POR 3-44)
`The Board properly rejected Netlist’s arguments about Grounds 1-3. ID 13-
`
`41.
`
`1. Ground 1 (Harris+FBDIMM Standards) discloses edge
`connections to receive power from the host system (POR 3-
`11)
`The Board correctly found that Ground 1 (Harris+FBDIMM Standards)
`
`teaches “edge connections configured to couple power…signals,” rejecting
`
`arguments similar to those repeated by Netlist here. ID 18-20; POR 3-11.
`
`Netlist does not dispute that the FBDIMM Standards (part of Ground 1)
`
`teach supplying power via edge connections, Pet. 16-21, and Netlist’s expert
`
`admits that such edge connections were “standard,” EX1075, 97:16-98:18, 163:16-
`
`20; EX1077, 9.
`
`Netlist argues that Harris’s reference to “externally supplied voltage” (e.g.,
`
`yellow below) requires power “external” to the entire “host system,” POR 3-11,
`
`but Harris merely requires power “external” to the DIMM memory module,
`
`EX2030, 66:7-:19, 67:20-68:21, 91:22-92:7, 129:24-130:17; Pet. 21-22.
`
`
`
`2
`
`
`
`

`

`
`
`POR 5.
`
`
`
`Netlist wrongly annotates Figure 1A (above) to suggest that Harris would
`
`never utilize edge connections at the bottom for power, POR 4-5, but Figure 3 of
`
`Harris, below, illustrates memory boards 306 coupled to the host system only
`
`through their edge connections (red), meaning power would also come from those
`
`edge connections:
`
`
`
`3
`
`
`
`

`

`
`
`
`
`EX1023, Fig.3. Indeed, Figure 3 of Harris above is nearly identical to a drawing
`
`by Intel where the memory modules admittedly receive power through the edge
`
`connections from the host system. EX1075, 171:4-:17; EX2101, 4. Harris also
`
`confirms that, “[a]lthough not explicitly shown in this FIGURE [3, above], each
`
`memory board also receives a supply voltage …[which] may be sourced from the
`
`memory controller 302 [which is part of the host system, EX1075, 167:23-168:1]
`
`or from a separate voltage source.” EX1023, [0017]. As explained by Dr. Wolfe,
`
`it was common for the host to supply power through edge connectors “alongside
`
`the memory controller signals.” EX2030, 131:3-:5.
`
`Netlist misinterprets paragraph [0019] of Harris to conclude that “system
`
`
`
`4
`
`
`
`

`

`
`
`board power supply…[is] eliminated” entirely. POR 4-5, 8, 10-11. To the
`
`contrary, Harris proposes avoiding the need for different system board voltages —
`
`such as “3.3V, 2.5V, 1.8V, 1.5V and beyond,” EX1023, [0002] — by simply
`
`supplying a single voltage (i.e., “12V”)2 to the memory module, id. [0012-13], so
`
`that an “on-board voltage regulator module [e.g., 102 above] [can] generate
`
`appropriate local voltage levels” on the memory module, id. [0003]. As Dr. Wolfe
`
`explained, Harris’s “technology-independent voltage distribution scheme”
`
`eliminates the need for a “system-board-specific power supply,” id. [0019], not all
`
`power, EX2030, 116:10-117:6.
`
`Using edge connectors like those illustrated in Figure 3 above to supply
`
`
`2 Netlist’s expert admitted that it was common at the time for the host system to
`
`provide a regulated “12V power supply.” EX2031, ¶65; EX1075, 180:14-183:3;
`
`EX2038, 8, 13. Netlist argues that Harris is limited to receiving an unregulated
`
`12V supply, POR 6-7, when in fact Harris teaches that the input voltage can be
`
`“regulated or unregulated,” EX1023 [0014]. Indeed, both experts agree that
`
`Harris’s disclosure of a 12V supply with “wide tolerance (e.g., around +/-15%),”
`
`id. [0013], means that the voltage is regulated to stay within those limits. EX1003,
`
`¶487; EX1075, 179:21-180:6, 183:7-184:11; EX2030, 65:23-66:6, 273:7-:12,
`
`274:17-275:3.
`
`
`
`5
`
`
`
`

`

`
`
`power is also consistent with Harris’s use of the known FB-DIMM (“FBD”)
`
`design, except with “few[er]” power pins given the higher 12V input voltage.
`
`EX1023, [0012]; EX2030, 100:12-101:19, 102:17-:25, 103:11-104:23. To prevent
`
`“accidental damage” due to this change in the power pins of the edge connector,
`
`Harris teaches changing “the board’s connector keyway” so that it is “not
`
`interchangeable with the standard DIMM.” EX1023, [0013]; EX2030, 117:7-:21.
`
`This was a standard technique for memory modules receiving power from the host
`
`via the edge connections:
`
`EX2016, 6-7; see also EX2101, 21-22; EX1075, 171:21-175:20.
`
`Netlist’s argument that “[s]upplying power…from [the] side…was known,”
`
`
`
`6
`
`
`
`
`
`

`

`
`
`POR 5, misses the point: regardless of whether a side connection was possible, that
`
`would not negate the obviousness of using edge connections for power, as was
`
`highly common. See Dome Pat. L.P. v. Lee, 799 F.3d 1372, 1381 (Fed. Cir. 2015)
`
`(existence of a better alternative “does not mean that an inferior combination is
`
`inapt for obviousness purposes”). Indeed, Netlist’s expert admitted that using both
`
`was a known option, consistent with the combination for Grounds 2-3: the side
`
`connection could be used for battery backup (as taught by Amidi), and the edge
`
`connections could be used for power from the host system during normal operation
`
`(as taught by Harris):
`
`
`
`EX2035, 39; EX1075, 165:10-166:12.
`
`2. Harris discloses receiving “data, address, and control
`signals” from the host (POR 11-15)
`As shown below by Netlist’s technology tutorial, an FBDIMM (second
`
`below) receives signals for data (DQ), address (ADDR), and control (CMD),
`
`
`
`7
`
`
`
`

`

`
`
`similar to an RDIMM memory module (first below):
`
`
`
`
`
`EX1077, 8-9; EX1075, 91:23-92:19, 95:14-96:13, 97:16-98:18.
`
`Netlist incorrectly argues that Harris’s FBDIMM (or FBD) does not receive
`
`data, address, and control “signals” from the host system because, under the
`
`FBDIMM standard, those signals are encoded first into a packetized signal that can
`
`be sent to the AMB (shown above) on fewer wires than if the signals were all sent
`
`separately. POR 11-12; EX2031, ¶31; EX1075, 155:22-157:1; EX2030, 8:3-11:6.
`
`
`
`8
`
`
`
`

`

`
`
`In essence, Netlist is trying to rewrite the claims (and its expert’s testimony) to
`
`require “dedicated pins” for address, command, and data, EX1075, 212:3-:8,
`
`213:3-215:20, 219:13-220:9, 226:7-228:8, even though that is not what the claims
`
`say, and the specification specifically identifies FBDIMM as an embodiment of the
`
`invention. EX1001, 21:46-:55 (“fully-buffered (FBDIMM)”). Excluding a
`
`preferred embodiment from the claims is “rarely, if ever correct.” Kaufman v.
`
`Microsoft Corp., 34 F.4th 1360, 1372 (Fed. Cir. 2022).
`
`Indeed, Netlist concedes that the signals received by the AMB on the
`
`FBDIMM result in “data, address, and control signals needed by the DDR2
`
`SDRAMs.” EX2031, ¶31. And the FBDIMM standard confirms that “[a]ll
`
`memory control for the DRAM resides in the host, including memory request
`
`initiation,” and the AMB “[a]cts as DRAM memory buffer for all read, write, and
`
`configuration accesses addressed to the DIMM.” EX1027, p.1. As a buffer for all
`
`such commands to the FBDIMM, the AMB must necessarily couple data, address,
`
`and control signals from the host system to the memor

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