UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS COC0., LTD.,
`Petitioner.,
`
`V.
`
`NETLIST, INC.,
`Patent Owner.
`
`Case No. IPR2022-009962022-00999
`Patent No. 11,016,91811,232,054
`
`DECLARATION OF DR. WILLIAM HENRY MANGIONE-SMITH
`
`I declare that all statements made here on my own knowledge are true and that all
`statements made contain information and belief are believed to be true, and further, that
`these statements were made with the knowledge that willful false statements and
`the like so made are punishable by fine or imprisonment, or both, under Section 1001
`or Title 18 of the United States Code.
`
`Date: 3/29/22
`
`Ďr. Willam Henry
`Mangione-Smith
`
`Samsung Ex. 1076, p. 1
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS COC0., LTD.,
`Petitioner.,
`
`V.
`
`NETLIST, INC.,
`Patent Owner.
`
`Case No. IPR2022-009962022-00999
`Patent No. 11,016,91811,232,054
`
`DECLARATION OF DR. WILLIAM HENRY MANGIONE-SMITH
`
`I declare that all statements made here on my own knowledge are true and that all
`statements made contain information and belief are believed to be true, and further, that
`these statements were made with the knowledge that willful false statements and
`the like so made are punishable by fine or imprisonment, or both, under Section 1001
`or Title 18 of the United States Code.
`
`Date: 3/29/22
`
`Ďr. Willam Henry
`Mangione-Smith
`
`Samsung Ex. 1076, p. 1
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
`
`
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`1
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`Netlist Ex 2061-p. 1
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`IPR2022-00999
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`Samsung Ex. 1076, p. 2
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner, v.
`
`NETLIST, INC., Patent Owner.
`
`Case No. IPR2022-00999 Patent No. 11,232,054
`
`DECLARATION OF DR. WILLIAM HENRY MANGIONE-SMITH
`
`I declare that all statements made here on my own knowledge are true and that all
`statements made contain information and belief are believed to be true, and
`further, that these statements were made with the knowledge that willful false
`statements and the like so made are punishable by fine or imprisonment, or both,
`under Section 1001 or Title 18 of the United States Code.
`
`Date:
`
`Dr. William Henry Mangione-Smith
`
`1
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`Samsung Ex. 1076, p. 3
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`1
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`Netlist Ex 2031-p. 1 Samsung v Netlist
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`IPR2022-00996
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`2
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`Samsung Ex. 1076, p. 4
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`DECLARATION OF DR. WILLIAM HENRY MANGIONE-SMITH, PH.D
`
`I, William Henry Mangione-Smith, do hereby declare as follows:
`
`INTRODUCTION
`I have been retained on behalf of Netlist, Inc. (“Patent Owner”) as an
`
`expert
`
`to
`
`evaluate
`
`certain
`
`technical
`
`aspects of U.S. Patent No.
`
`11,016,91811,232,054 (“the ’918054 patent”), and to provide certain related
`
`opinions. I am personally knowledgeable about the matters stated herein and am
`
`competent to make this declaration.
`
`I understand that Patent Owner will
`
`submit
`
`this declaration
`
`(“Declaration”) in connection with IPR2022-009962022-00999 (“Proceeding”),
`
`which I have been informed is an inter partes review (IPR) proceeding before the
`
`Patent Trial and Appeal Board challenging the patentability of claims 1-30 of the
`
`’918054 patent.
`
`I receive compensation at my normal consulting rate for my time
`
`working on this matter, plus expenses. I have no financial interest in Patent Owner
`
`or in the patents involved in this litigation, and my compensation is not dependent
`
`on the outcome of this litigation. The opinions I present are due to my own judgment.
`
`All “EX10XX” cites herein are to exhibits I understand were submitted
`
`by Petitioner and all “EX20XX” cites herein are to exhibits I understand have or
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`will be submitted by the Patent Owner in this Proceeding. All “Appendix _” cites
`
`3
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`Samsung Ex. 1076, p. 5
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`followed by a letter are to appendices to this Declaration. All citations to “Section
`
`XX” are internal citations to the sections of this Declaration. All citations to
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`“Paragraph XX” are internal citations to the paragraphs of this Declaration.
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`BACKGROUND AND QUALIFICATIONS
`I received my Bachelor of Science in Engineering in 1987 and my
`
`Master of Science in Engineering in 1992, both from the University of Michigan. I
`
`also received my Doctorate in Engineering from the University of Michigan.
`
`I am a Member of the Association for Computing Machinery (ACM)
`
`and the Institute of Electrical and Electronics Engineers (IEEE). I've served as the
`
`Program Chair and the General Chair for the 26th and 36th International
`
`Symposiums on Microarchitecture, respectively. I have served as the Associate
`
`Editor of IEEE Transactions on Computers, the Associate Editor of ACM
`
`Transactions on Embedded Computing Systems, and the Associate Editor of IEEE
`
`Computer. I have served on various Program Committees, including ISCA,
`
`Network Processors Workshop, Complexity-Effective Design, and Workshop on
`
`Mediaprocessors and DSP. I have published numerous journal articles on
`
`computing, given 49 conference presentations, and authored several book
`
`chapters and magazine articles on such issues. I am listed as an inventor on 121
`
`patents nearly all of which are related to microprocessor and memory technology,
`
`and am listed on more than 200 pending patent applications.
`
`I have an extensive background working with electronics and computer
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`4
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`patents. I currently work as a consultant on intellectual property matters, including
`
`reviewing and valuing patents and patent portfolios for Phase Two LLC, and I
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`have held this position since 2009. Prior to that, from 2005-2008, I was employed
`
`at Intellectual Ventures, working on patent valuation, with a focus on computer
`
`patents, and outbound licensing in consumer electronics, among other focuses.
`
`During my time at Intellectual Ventures the company developed intellectual
`
`property that resulted in several successful startups. I was not involved in any of
`
`the litigation while I was at Intellectual Ventures, focusing instead on developing
`
`new ideas. From 1995-2005, I worked as an Assistant and an Associate Professor
`
`in electrical engineering at the University of California, Los Angeles. From
`
`1993-1995, I worked as a Systems Architect for the Motorola Wireless Data
`
`Group, where I worked on designing and developing the microprocessor for an
`
`early smartphone. From 1991- 1992, I worked with Motorola Corporate research,
`
`focusing on parallel computer performance monitoring and low-power processor
`
`architecture. Finally, from 1986- 1987, I worked as a Software Architect at
`
`Chrysler Corporation, where I operated supercomputers related to designing,
`
`testing, and simulating car designs. I have been accepted by various courts as an
`
`expert in the fields of computer engineering, including computer architecture and
`
`microarchitecture.
`
`A current curriculum vitae is attached as Appendix A and includes the
`
`5
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`above listed credentials, additional background and information, and my
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`experience as an expert witness from the previous four years.
`
`MATERIALS CONSIDERED
`I have considered information from various sources in forming my
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`opinions. Besides drawing from my decades of experience in the computer
`
`industry, I have reviewed the Petition and supporting declaration from Dr. Wolfe,
`
`the ’918054 patent and its file history, the prior art discussed below, Dr. Wolfe’s
`
`deposition transcript, along with the other documents and references cited here.
`
`I have also reviewed the declaration submitted by Dr. Khatri in support
`
`of the preliminary patent owner response submitted in this Proceeding. Because of
`
`significant overlaps with points that I make throughout my report, in some
`
`instances I have adopt his positions as my own.
`
`LEGAL STANDARDS
`I have relied on instructions from counsel as to the applicable legal
`
`standards to use in arriving at my opinions in this Declaration. I am relying only on
`
`instructions from Netlist’s attorneys for these legal standards.
`
`I understand that a patent claim is unpatentable and invalid if the subject
`
`matter of the claim as a whole would have been obvious to a person of ordinary
`
`skill in the art of the claimed subject matter, as of the time of the invention at
`
`issue.
`
`I have been informed and understand that a patent claim can be
`
`6
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`considered to have been obvious to a person of ordinary skill in the art at the time
`
`of the alleged invention. This means that, even if all the requirements of a claim
`
`are not found in a single prior art reference, the claim is not patentable if the
`
`differences between the subject matter in the prior art and the subject matter in the
`
`claim, would have been obvious to a person of ordinary skill in the art at the time
`
`of the alleged invention.
`
`I understand that the following factors must be evaluated to determine
`
`whether the claimed subject matter is obvious: (1) the scope and content of the
`
`prior art; (2) the difference or differences, if any, between each claim of the patent
`
`and the prior art; and (3) the level of ordinary skill in the art at the time the patent
`
`was filed.
`
`I have been informed and understand that the teachings of two or more
`
`references may be combined if such a combination would have been obvious to
`
`one having ordinary skill in the art. In determining whether a combination based
`
`on multiple references would have been obvious, it is appropriate to consider,
`
`among other factors: (1) whether the teachings of the prior art references disclose
`
`known concepts combined in familiar ways, and when combined, would yield
`
`predictable results; (2) whether a person of ordinary skill in the art could
`
`implement such a combination, and would see the benefit of doing so; (3) whether
`
`the claimed elements represent one of a limited number of known design choices,
`
`7
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`and would
`
`have a reasonable expectation of success by those skilled in the art; (4) whether a
`
`person of ordinary skill would have recognized a reason to combine known
`
`elements in the manner described in the claim; (5) whether there is some teaching
`
`or suggestion in the prior art to make the modification or combination of elements
`
`claimed in the patent; and (6) whether the claimed invention applies a known
`
`technique that had been used to improve a similar device or method in a similar
`
`way.
`
`I have been informed and understand that one of ordinary skill in the
`
`art has ordinary creativity, and is not an automaton.
`
`I have been informed and understand that in considering obviousness,
`
`it is important not to determine obviousness using the benefit of hindsight derived
`
`from the patent being considered.
`
`THE ’918054 PATENT
`The ’918054 patent generally relates to memory modules. In one preferred
`
`embodiment, the memory system 1010 comprises a PCB 1020 having DRAM
`
`(volatile) memory subsystem 1030 and NAND (nonvolatile) memory subsystem
`
`1040, both of which may be operatively coupled to a controller unit 1062. See,
`
`e.g., EX1001, Fig. 12 (reproduced below); see also id., 21:14-23.
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`8
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`As shown in the embodiment of FIG. 12, the controller 1062 includes
`
`a microcontroller unit (MCU) 1060 and a logic element (comprising a field-
`
`programmable gate array (FPGA)) 1070. See id., 23:1-22, 24:35-37. However, in
`
`other embodiments the FPGA 1070 may be integrated with the microcontroller
`
`1060. See id., 23:19-22, Fig. 14. The ’918054 patent explains that the
`
`microcontroller 1060 provides memory management and controls data transfer
`
`between the non-volatile memory 1040 and volatile memory 1030. See id.,
`
`24:38-41. The FPGA logic element 1070 provides signal level translation and
`
`address translation between the volatile memory and non-volatile memory. “The
`
`logic element 1070 can provide
`
`signal level translation between the volatile memory elements 1032 (e.g., 1.8V SSTL-2
`9
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`for DDR2 SDRAM elements) and the non-volatile memory elements 1042 (e.g., 3V TTL
`for NAND flash memory elements),” and “address/address translation between the
`volatile memory subsystem 1030 and the non-volatile memory subsystem 1040.” Id.,
`24:48-56.
`
`The ’918054 patent further discloses that the PCB includes a DIMM
`
`interface 1022, which comprises edge connections via which it provides “power
`
`voltage as well as data, address and control signals between the memory system
`
`1010 and [a] host system.” Id., 22:1-6.
`
`The ’918054 patent also discloses a voltage monitor circuit 1050 on the
`
`PCB that “monitors the voltage supplied by the host system via the [DIMM]
`
`interface 1022.” Id., 25:8-10, Fig. 12. Upon detecting an abnormal condition, “the
`
`voltage monitor circuit 1050 may transmit a signal to the controller 1062
`
`indicative of the detected condition.” Id., 25:11-14. The controller 1062 may in
`
`turn transmit a signal to switch 1052 for it to operatively couple the volatile
`
`memory and the non- volatile memory, thereby effecting a transition from the first
`
`state to the second state. See id., 25:15-20. In certain embodiments, the voltage
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`monitor circuit 1050 may be part of the controller 1062. See id., 25:27-31.
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`10
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`SKILL LEVEL OF A POSITA
`I note that Dr. Wolfe contends that a person having ordinary skill in the
`
`art (“POSITA”) in the field of the ’918054 patent in 2008 would have been
`
`someone with an advanced degree in electrical or computer engineering, or a
`
`related field, and two years working or studying in the field of design or
`
`development of memory systems, or a bachelor’s degree in such engineering
`
`disciplines and at least three years of work experience in the field. See EX1003, ¶
`
`6761.
`
`For purposes of the opinions I set forth herein, and to simplify the
`
`issues, I have adopted that understanding as to the level of skill in the relevant
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`field at the time of the invention, noting that none of the opinions I express herein
`
`would
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`change if a somewhat higher or somewhat lower level of skill were adopted.
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`However, I reserve the right to separately analyze the appropriate level of skill at
`
`the time of the invention, and to propose a different ordinary level of skill in the
`
`art based on that analysis.
`
`THE PRIOR ART
`The Petition challenges the claims of the ’918054 patent based primarily
`
`on U.S. Patent Publication No. 2006/0174140 (“Harris”), certain JEDEC
`
`published standards for Fully Buffered DIMM (FBDIMM) memory modules
`
`(EX1027 and EX1028), U.S. Patent No. 7,724,604 (“Amidi”), U.S. Patent
`
`Publication No. 2006/0080515 (“Spiers”), and U.S. Patent No. 6,856,556
`
`(“Hajeck”). Below I provide a brief overview of those references.
`
`A.
`
`Harris (EX1023)
`U.S. Patent Publication No. 2006/0174140 to Harris et al. (“Harris”),
`
`titled “Voltage Distribution System and Method for a Memory Assembly,”
`
`discloses a “memory assembly module including an on-board voltage regulator
`
`for converting an externally supplied voltage into appropriate voltage levels for
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`powering memory devices of the memory assembly module.” EX1023, Title,
`
`Abstract, FIG. 1A.
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`As Harris explains, conventional memory modules, such as industry
`
`standard Dual In-line Memory Modules (DIMM) “are provided with power
`
`supply rails (on a relatively large number of pins) that are powered from system
`
`board or main board voltage sources, and are specific to the memory technology.”
`
`Id.,
`
`[0002]. Harris, on
`
`the other hand,
`
`aims
`
`to
`
`“provide[]
`
`a
`
`technology-independent voltage distribution scheme for memory devices wherein
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`system board power supply and associated voltage plane(s) are eliminated.” Id.,
`
`[0019]. Using a fully-buffered DIMM as an example, Harris achieves its goal by
`
`“replacing the[] power supply interface pins with … +12V pins (from an external
`
`power source), with local conversion to VDD (to DRAM) and VCC (to buffer/logic)
`
`being added.” Id., [0012].
`
`In other words, instead of obtaining power from the host via power
`
`supply interface pins on the interface that fits into a corresponding memory slot in a host
`system, Harris’ design derives its power from an external power source that is
`subsequently converted to the appropriate voltage levels depending on the design. See
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`id., [0012]; [0016] (“voltage is supplied to a memory board assembly from an external
`source, e.g., an unregulated source generating fairly high voltages (illustratively, at
`+12V) with a wide tolerance. The voltage distribution method then involves locally
`converting the supply voltage using an on-board VRM to generate appropriate levels of
`voltage for powering on-board memory devices. … [T]he local voltage levels preferably
`depend on the application….”).
`In an alternative embodiment, more than one voltage source may be
`
`provided “wherein each VRM is operable with an independent voltage supply
`
`path for locally converting an external supply voltage into appropriate local
`
`voltage levels.” Id., [0014]. The embodiment utilizes multiple VRMs “120-1
`
`through 120- K, [which] refer to K supply voltage paths which may be coupled to
`
`various voltage sources provided within the electronic system (e.g., a computer
`
`system).” Id. This embodiment contemplates one voltage regulator module per
`
`external voltage source, and does not contemplate multiple voltage regulator
`
`modules for a single voltage source. In this embodiment, a “logic module 124 is
`
`provided for selecting among the plurality of like voltage outputs from the VRMs
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`122-K in order to energize the Vdd and Vcc paths 108, 106, respectively.” Id.,
`
`[0015].
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`B.
`
`FBDIMM Standard (EX1027 & EX1028)
`“JESD82-20” (EX1027) is the JEDEC specification for the Advanced
`
`Memory Buffer (AMB) of a fully- buffered DIMM module (FBDIMM).
`
`JESD82-20 describes the AMB as “responsible for handling FBD channel and
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`memory requests to and from the local DIMM and for forwarding requests to
`
`other DIMMs on the FBD channel.” JESD82- 20 at 1. JESD82-20 describes the
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`power supplies to the AMB.
`
`(EX1027, p. 83)
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`“JESD205” (EX1028) is the JEDEC specification that “defines the
`
`electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-
`
`6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual
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`In- Line Memory Modules (DDR2 SDRAM FB-DIMMs).” EX1028, 9. JESD205
`
`notes the following supply voltages to the FBDIMM via the FBDIMM pins.
`
`(EX1028, p.11)
`
`FBDIMM uses packetized serial signaling to exchange data, address
`
`and control information with the host. This contrasts with common DIMM
`
`formats like RDIMMs, UDIMMs and SODIMMs. This is evident from the pinout
`
`of the DIMM. As such, the AMB receives data, address, and control information,
`
`decodes it, and generates the data, address, and control signals needed by the
`
`DDR2 SDRAMs. This can be seen from the fact that in the pin description for
`
`AMB, there are dedicated pins for data, address or control under the heading for
`
`“FB-DIMM Channel Signals” (i.e., signals exchanged with between the AMB and
`
`the host). Instead, the signals received from the host are denoted as PS[9:0] and its
`
`complement PS[9:0]_bar; and the signals sent to the host are PN[13:0] and their
`
`complement PN[13:0]_bar.
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`(EX1028, p. 29)
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`Signals such as DQ[63:0], A[15:0], BA[2:0], RAS, RAS bar, CAS,
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`CAS_bar, WE, WE_bar, CS, CS_bar are all under the heading “DDR2 Interface
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`Signals,” and are signals exchanged between the AMB and the DDR2 SDRAMs.
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`As Intel’s presentation indicates, these signals are generated within the
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`AMB after deserializing and decoding the serialized packets (PS[9:0]) from the host.
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`(Note, Intel was a key proponent of the FBDIMM technology).
`
`(EX2101, p.5)
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`As such, the information the AMB receives is decoded and used to
`
`generate the data, address and control signals to be sent on dedicated wires to
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`SDRAMs. This is further confirmed by datasheets for AMBs by component
`
`suppliers such as IDT, which shows the differential signaling PS[9:0] and
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` PS[9:0]_bar pass through a series logic and control blocks to generate the data,
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`control and address signals for SDRAMs. See, e.g., EX2039, p.2.
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`19
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`C.
`
`B.Amidi (EX1024)
`U.S. 7,724,604 to Amidi et al. (“Amidi”) relates to “Clock and power
`
`fault detection for memory modules.” EX1024, Title. Amidi provides a way of
`
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`“keeping data in volatile memory even when a surrounding system loses power” or
`
`“suffers some form of error which causes a clock to malfunction.” Id. at 1:28-33. In
`
`one embodiment, Amidi attempts to solve this problem by combining a “battery,
`
`battery regulation circuitry, volatile memory, memory control state machine,
`
`controller, clock detection circuit and voltage detection circuit.” Id., Abstract, 2:27-
`
`39; see also FIG. 4.
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`21
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`Samsung Ex. 1076, p. 23
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`Amidi’s disclosed structure includes a “[p]ower management block
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`500, include[ing] the actual power management module 510, an incoming system
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`supply 520, an incoming battery supply 530, and an outgoing memory power
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`supply 540.” Id., 4:16-19; FIG 5. This power management block 500 is “used to
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`attempt to ensure a stable power supply even in the face of disruptions in system
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`supply 520.” Id., 4:19-22.
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`22
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`Samsung Ex. 1076, p. 24
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`Power management block 600, depicted in FIG 6, provides an example
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`implementation of the internals of power management block 500. Id., 4:23-27.
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`The block 600 includes circuitry related to powering and managing battery 630,
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`including charging circuitry 620, discharging circuitry 635, gas gauge circuitry.
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`Id., 4:30-35. Battery 630’s output is provided to a boost converter 680, boost/buck
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`converter 690, and buck converter 640 when enabled by signal 670. Id., 4:35-39.
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`When enabled, buck converter 640 “produces battery power 650 as an input to
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`power switch multiplexer 655,” which “switch[es] between battery power 650 and
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`system supply 605 based on a signal 670.” Id., 4:39-43.
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`23
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`Samsung Ex. 1076, p. 25
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`“Signal 670 is controlled by voltage supervisory block 665, which
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`receives system supply 605 and a reference voltage 675, and compares the two.”
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`Power switch multiplexer 655 chooses system supply 605 as a source for memory
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`supply 660 unless it falls below reference voltage 675. Id., 4:46-52.
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`Thus, at both a high-level and in its most specific embodiments, Amidi
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`tailored to the problem of keeping volatile memory powered when there is an
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`undervoltage condition. It achieves this by including a backup battery on the
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`memory module that is used only when the supply voltage falls below a particular
`
`voltage level.
`
`24
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`Samsung Ex. 1076, p. 26
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`
`
`D.
`
`C.Spiers (EX1025)
`U.S. 2006/0080515 to Spiers et al. (“Spiers”) relates to “Non-Volatile
`
`Memory Backup for Network Storage System.” EX1025, p. 1 (title). Spiers aims
`
`to reduce the amount of time it takes to report data that is written into a storage
`
`media while minimizing the risk of data loss. See id., [0003].
`
`To achieve its objective, Spiers provides a backup storage system to the
`
`main storage device (such as a hard disk drive). See id., [0007]-[0008], Fig. 3.
`
`Spiers describes its implementation with reference to network attached storage
`
`(NAS) devices. See id., [0029], Fig. 1. The NAS device “receive[s] data from
`
`applications 104, and acknowledge back to the application 104 that the data is
`
`securely stored at the NAS device 108, before the data is actually stored on
`
`storage media located within the NAS 108.” Id., [0030]. This allegedly improves
`
`the NAS’s performance as the NAS device can report that the data has been stored
`
`without waiting for the data to be actually stored at the storage media. See id.,
`
`[0030]-[0031], Figs. 2-3. Spiers achieves this by sending a command to the
`
`backup device to store the data and reports the data as having been stored if the
`
`backup device reports that that data is store. See id., [0040], Fig. 6.
`
`25
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`Samsung Ex. 1076, p. 27
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`
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`In addition to components that interface with the network, Spiers’ NAS
`
`device includes a main storage device 140 with write-back cache and a backup
`
`device 144, as shown in FIG. 3 above. See id., [0031]-[0032].
`
`Spiers’ backup storage device 144 includes a volatile memory (such as
`
`SDRAM), a non-volatile memory (such as a NAND flash), and a processor. See
`
`id., [0007], [0010], [0032], [0036], Fig. 4. The processor is “for causing a copy of
`
`data provided to the [main] storage device to be provided to the [backup] storage
`
`device volatile memory, and in the event of a power interruption, moving the data
`
`from the [backup] data storage device volatile memory to the [backup] data
`
`storage device non-volatile memory.” Id. In this manner, the data written to main
`
`storage’s write- back cache would be retained even in the event of a power
`
`interruption, which in
`
`26
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`20312061-p. 26
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`Samsung Ex. 1076, p. 28
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`
`
`turn reduces the risk of data loss. See id., [0007], [0034]. A high-level block
`
`diagram for the backup device is shown in Figure 4.
`
`Spiers explains that in the example backup device 144, there exists an
`
`interface 152 “utilized to communicate with [a] storage controller 132” shown in
`
`Figure 3. Id., [0036]. The interface 152 is connected to a processor 156 in the
`
`backup device 144, and the processor “controls operations within the backup
`
`device 144.” Id. Connected to the processor 156 are volatile memory 160 (e.g.,
`
`SDRAM) and non-volatile memory 164 (e.g., flash). Id. The backup device 144
`
`also includes a power supply 168, which is used “upon detecting a power failure”
`
`to supply power for moving data from the volatile memory 160 to the non-volatile
`
`27
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`Samsung Ex. 1076, p. 29
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`
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`memory 164. Id.
`
`“After the data from the volatile memory 160 is stored in the non-volatile memory
`
`164, the processor 156 shuts down the backup device 144.” Id.
`
`One example of a backup power supply 168 is a capacitor array, which
`
`is “charged when the backup device 144 is powered up.” Id. In the event of a
`
`power interruption, “the backup device 144 receives power from the capacitors
`
`when moving the data. After the data is securely stored in the non-volatile
`
`memory 164, the power is switched off from the capacitor(s).” Id.
`
`Spiers’ Figure 5 illustrates an example of such an implementation
`
`which is reproduced below with the annotations included in the Petition. A red
`
`box has been added around the components that correspond to the backup power
`
`supply 168 in Figure 4. See Petition at 83.
`
`28
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`Samsung Ex. 1076, p. 30
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`
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`NAND Flash module 194, SDRAM module 190, processor 198 and 64-
`
`bit PCI interface 172 correspond respectively to the non-volatile memory 164,
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`volatile memory 160, processor 156 and interface 152 of Figure 4. See EX1025,
`
`[0037].
`
`Spiers references only two voltage regulators: (1) the 5V-to-3.3V
`
`regulator 184, and (2) regulator 206 that outputs 1.8V “required for the [processor]
`
`core.” Id., [0037], Fig. 5.
`
`In Figure 5, the power supply includes two 50F super capacitors
`
`connected in a parallel. See id., [0037]. “The capacitors 176 are connected to a
`
`diode 180[,] a voltage regulator 184, and a charger 186.” Id. The charger 186
`
`draws power from the PCI interface and “charge[s] the capacitors.” Id. “[I]n the
`
`event of a power failure[,] the capacitors are used as the power source to power
`
`the backup device 144 when moving data from the volatile memory to the
`
`non-volatile memory.” Id.; see also Fig. 5 (showing “+5V_PCI Detector” block).
`
`E.
`
`D.Hajeck (EX1038)
`U.S. 6,856,556 to Hajeck (“Hajeck”) uses a charge pump in a storage
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`subsystem (such as a flash memory card) as a backup power supply when power
`
`signals from an associated host system is interrupted. EX1038, Abstract. In
`
`response to detecting such an interruption, a busy signal is asserted to block the
`
`host system from performing write operations to the storage subsystem. Id. In
`
`29
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`Samsung Ex. 1076, p. 31
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`
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`turn, the backup, regulated power provided by the charge pump provides
`
`sufficient power for the controller to complete all outstanding operations. Id. Such
`
`a setup reduces the incidences of “data loss, data corruption, and circuitry damage
`
`caused by interruptions and other irregularities in the power signal supplied by the
`
`host system.” EX1038, 1:15-18, 1:34-36, 1:49-61 (“In addition to providing
`
`backup power, the charge pump circuit protects the controller from potential
`
`damage caused by power surges and spikes”), 1:62-2:7 (with the disclosed charge
`
`pump based design, “[t]he likelihood that data will be lost as the result of the
`
`power signal anomaly is …. significantly reduced”).
`
`CLAIM CONSTRUCTION
`I note that the term “memory module” appears in the preamble of each
`
`of the independent claims of the ’918054 patent, and that this term provides an
`antecedent basis for the same term in the body of the text. See EX1001, Claims 1, 16,
`23independent claims 1 and 16, and in the body of dependent claims 4, 6, 11, and 25.
`30
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`Samsung Ex. 1076, p. 32
`Samsung Electronics Co., Ltd. v. Netlist, Inc., IPR2022-00996
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`
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`I understand that the District Court found that the preamble was limiting
`
`because “a skilled artisan would understand a ‘memory module’ is distinct from,
`
`and has essential structural requirements not necessarily found in, other modular
`
`computer accessories. That includes the structure necessary to connect to a
`
`memory controller.” EX2032, 28. I understand that the district court made this
`
`ruling after reviewing the entire specification and based its ruling on the
`
`specification’s disclosures. For instance, the specification states in the Overview
`
`section that the memory module is particularly “couplable to a memory controller
`
`of a host system.” EX1001, 3:66–67 (emphasis added); see also id., 1:66–67
`
`(“[t]he present disclosure relates generally to computer memory devices”).
`
`I also note that Dr. Wolfe testified that the term “memory modules”
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`typically refers to “main memory modules,” which “are designed to connect to the
`
`primary memory controller for the purpose of the holding general purpose code
`
`and data in a computer system.” EX20302060, 123:14-25. I agree, and in my
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`experience, at the time of the invention and in the context of th
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