`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`
`SAMSUNG ELECTRONICS CO., LTD, MICRON TECHNOLOGY, INC.,
`MICRON SEMICONDUCTOR PRODUCTS, INC., and MICRON
`TECHNOLOGY TEXAS LLC,1
`Petitioners.
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`
`
`___________________
`
`Case IPR2022-00996
`Patent No. 11,016,918
`___________________
`
`
`
`
`PATENT OWNER NETLIST, INC.’S NOTICE OF APPEAL
`
`
`
`1 Micron Technology, Inc., Micron Semiconductor Products, Inc., and
`Micron Technology Texas LLC filed a motion for joinder and a petition in
`IPR2023-00406 and have been joined as petitioners in this proceeding.
`
`
`11314258
`
`
`
`
`
`Case IPR2022-00996
`Patent No. 11,016,918
`
`
`Pursuant to 35 U.S.C. §§ 141, 142, and 319, and in accordance with 37 C.F.R.
`
`§§ 90.2-90.3, Patent Owner Netlist, Inc. (“Netlist”) appeals to the United States
`
`Court of Appeals for the Federal Circuit from the Final Written Decision of the
`
`Patent Trial and Appeal Board (“Board”) entered on December 6, 2023 in IPR2022-
`
`00996 (Paper No. 49) (“Final Written Decision”), attached as Exhibit A; the Order
`
`denying Director Review of the Final Written Decision dated March 18, 2024 (Paper
`
`53) (“Decision on Director Review Request”), attached as Exhibit B; and from all
`
`underlying findings, determinations, rulings, opinions, orders, and decisions
`
`regarding the inter partes review (Case IPR2022-00996) of U.S. Patent No.
`
`11,016,918 (the “'918 Patent”).
`
`In accordance with 37 C.F.R. § 90.2(a)(3)(ii), Netlist states that the issues on
`
`appeal include, but are not limited to: the Board’s determination that Claims 1
`
`through 30 of the '918 Patent have been shown by a preponderance of the evidence
`
`to be unpatentable; the Board’s construction of the challenged claims and application
`
`of its construction of the claims to the facts of record; the Board’s procedural rulings,
`
`including its rulings regarding the adequate and timely preservation of certain of the
`
`parties’ arguments and denial of submission of supplemental evidence that came into
`
`being after the sur-reply; the adequacy of the Board’s consideration of the expert
`
`testimony, prior art, and other evidence in the record, including, but not limited to,
`
`evidence and testimony from related district court proceedings between Petitioner
`
`
`
`
`
`
`
`
`Case IPR2022-00996
`Patent No. 11,016,918
`
`and Patent Owner; the Board’s factual findings, conclusions of law, or other
`
`determinations supporting or related to those issues (such as motivation to combine
`
`or reasonable expectation of success);
`
`the Board’s compliance with
`
`the
`
`Administrative Procedure Act, including whether the Final Written Decision, the
`
`denial of Director Review and the denial of Netlist’s request for submitting
`
`supplemental evidence are arbitrary, capricious, an abuse of discretion, not in
`
`accordance with law, or in excess of the Board’s jurisdiction, and any procedural
`
`irregularities associated with the review proceeding; as well as all other issues
`
`decided adversely to Netlist in any orders, decisions, rulings, and opinions.
`
`This Notice of Appeal is being e-filed with the Clerk’s Office for the United
`
`States Court of Appeals for the Federal Circuit, along with payment of the required
`
`docketing fees. In addition, a copy of this Notice of Appeal is being filed
`
`simultaneously with the Patent Trial and Appeal Board and filed by e-mail to the
`
`Director of the United States Patent and Trademark Office at efileSO@uspto.gov.
`
`
`
`
`
`
`
`
`
`
`- 3 -
`
`
`
`Case IPR2022-00996
`Patent No. 11,016,918
`
`Dated: May 20, 2024
`
`
`
`
`
`
`
`
`Respectfully submitted,
`
`/Hong Zhong/
`H. Annita Zhong (Reg. No. 66,530)
`Jason Sheasby (pro hac vice)
`IRELL & MANELLA LLP
`1800 Avenue of the Stars, Suite 900
`Los Angeles, CA 90067
`Tel: (310) 277-1010
`Fax: (310) 203-7199
`HZhong@irell.com
`JSheasby@irell.com
`Philip Warrick (Reg. No. 54,707)
`IRELL & MANELLA LLP
`750 17th Street NW, Ste. 850
`Washington, DC 20006
`Tel: (202) 777-6500
`pwarrick@irell.com
`
`
`
`
`
`- 4 -
`
`
`
`Case IPR2022-00996
`Patent No. 11,016,918
`
`
`
`
`CERTIFICATE OF SERVICE
`
`Pursuant to 37 C.F.R. § 42.6, the undersigned certifies that on May 20,
`
`2024, a copy of the foregoing PATENT OWNER’S NOTICE OF APPEAL was
`
`served by electronic mail, as agreed to by the parties, upon the following:
`
`BAKER BOTTS L.L.P.
`Eliot D. Williams, Reg. No. 50,822
`Theodore W. Chandler, Reg. No. 50,319
`Ferenc Pazmandi, Reg. No. 66,216
`Aashish Kapadia, Reg. No. 78,844
`Brianna L. Potter, Reg. No. 76,748
`DLSamsungNetlistIPRs@BakerBotts.com
`
`WINSTON & STRAWN LLP
`Juan C. Yaquian, Reg. No. 70,755
`Michael R. Rueckheim, pro hac vice
`Winston-IPR-Netlist@winston.com
`
`I also certify that in addition to being filed electronically with the Board, a
`
`copy of this Notice of Appeal was filed on May 20, 2024, for delivery to the
`
`Director of the United States Patent and Trademark Office at the following e-mail
`
`address: efileSO@uspto.gov.
`
`I further certify that a copy of the foregoing Notice of Appeal is being filed
`
`via CM/ECF on May 20, 2024, with the United States Court of Appeals for the
`
`Federal Circuit.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`/Susan M. Langworthy/
` Susan M. Langworthy
`
`- 5 -
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`EXHIBIT A
`EXHIBIT A
`
`
`
`
`
`
`
`Trials@uspto.gov
`571-272-7822
`
`Paper 49
`Entered: December 6, 2023
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`SAMSUNG ELECTRONICS CO., LTD., MICRON TECHNOLOGY, INC.,
`MICRON SEMICONDUCTOR PRODUCTS, INC., and MICRON
`TECHNOLOGY TEXAS LLC, 1
`Petitioner,
`v.
`NETLIST, INC.,
`Patent Owner.
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`
`
`
`Before PATRICK M. BOUCHER, JON M. JURGOVAN, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`JURGOVAN, Administrative Patent Judge.
`
`
`
`
`DECISION
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`Dismissing Petitioner’s Motion to Exclude
`35 U.S.C. § 318(a)
`
`
`1 Micron Technology, Inc., Micron Semiconductor Products, Inc., and
`Micron Technology Texas LLC filed a motion for joinder and a petition in
`IPR2023-00406 and have been joined as petitioners in this proceeding. See
`Paper 26.
`
`
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`INTRODUCTION
`I.
`Samsung Electronics Co., Ltd. (“Samsung”) filed a Petition (Paper 1,
`“Pet.”) for inter partes review of claims 1–30 (“challenged claims”) of U.S.
`Patent 11,016,918 B2 (Ex. 1001, “the ’918 patent”). Netlist, Inc. (“Patent
`Owner”) filed a Preliminary Response (Paper 7, “Prelim. Resp.”) to the
`Petition. We instituted inter partes review under 35 U.S.C. § 314(a).
`Paper 10 (“Inst. Dec.”).
`During the trial, Patent Owner filed a Response (Paper 21, “Resp.”),
`Petitioner filed a Reply (Paper 25), and Patent Owner filed a Sur-Reply
`(Paper 31). We joined Micron Technology, Inc., Micron Semiconductor
`Products, Inc., and Micron Technology Texas LLC as petitioners in this
`proceeding, and we refer to Samsung and these entities collectively as
`“Petitioner.” See Paper 26.
`Petitioner and Patent Owner requested oral argument (Papers 28 and
`29). A hearing was conducted on September 11, 2023. Paper 47 (“Tr.”).
`Petitioner objected to evidence (Paper 32) and filed a Motion to
`Exclude (Paper 33). Patent Owner filed an Opposition to Petitioner’s
`Motion to Exclude (Paper 34), and Petitioner filed a Reply (Paper 37) in
`support of its Motion to Exclude.
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is entered pursuant to 35 U.S.C. § 318(a). Having reviewed the
`complete trial record, we determine that Petitioner has shown, by a
`preponderance of the evidence, that the challenged claims are unpatentable.
`
`2
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`II. BACKGROUND
`Real Parties in Interest
`A.
`The identified real parties in interest on the Petitioner side are the
`following entities: Samsung Electronics Co., Ltd., Samsung Semiconductor,
`Inc., Micron Technology, Inc., Micron Semiconductor Products, Inc., and
`Micron Technology Texas LLC. Pet. 1; IPR2023-00406, Paper 3, 1.
`Patent Owner identifies itself as the sole real party in interest. Paper
`
`4, 1.
`
`Related Matters
`B.
`The parties advise that the ’918 patent is related to the following
`pending matters:
`• Samsung Electronics Co., Ltd. et al. v Netlist, Inc., No. 1:21-cv-
`01453 (D. Del. filed Oct. 15, 2021)
`• Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:21-
`cv-00463 (E.D. Tex. filed Dec. 20, 2021)
`• Netlist, Inc. v. Micron Technology, Inc., No. 2:22-cv-00203
`(E.D. Tex. filed June 13, 2022)
`• IPR2012-00999 (U.S. Patent No. 11,232,054)
`• U.S. Patent Application No. 17/582,797
`Pet. 1; Paper 4, 1; Paper 9, 2; Paper 12, 1.
`
`The parties advise that the following related proceeding is no longer
`pending:
`• IPR2017-00692 (U.S. Patent No. 8,874,831)
`Pet. 1; Paper 4, 1.
`
`3
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`C. Overview of the ’918 Patent (Ex. 1001)
`The ’918 patent is titled “Flash-DRAM Hybrid Memory Module.”
`Ex. 1001, code (54). Figure 12 of the ’918 patent is reproduced below.
`
`
`Figure 12 shows an example memory system 1010 of the ’918 patent.
`Id. at 21:14–16. The memory system 1010 includes a volatile memory
`subsystem 1030, a non-volatile memory subsystem 1040, and a controller
`1062 operatively coupled to the volatile memory subsystem 1030 and
`selectively coupled to the non-volatile memory subsystem 1040. Id. at
`21:16–22. Volatile memory 1030 may comprise elements 1032 of two or
`more dynamic random access memory (DRAM) elements such as double
`data rate (DDR), DDR2, DDR3, and synchronous DRAM (SDRAM). Id. at
`22:16–19. Non-volatile memory 1040 may comprise elements 1042 of flash
`memory elements such as NOR, NAND, ONE-NAND flash and multi-level
`
`4
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`cell (MLC). Id. at 22:35–40. Memory system 1010 may comprise a
`memory module or printed circuit board (PCB) 1020. Id. at 21:24–26.
`Memory system 1010 has an interface 1022 for power voltage, data, address,
`and control signal transfer between memory system 1010 and a host system.
`Id. at 22:3–6.
`
`Controller 1062 may include microcontroller unit 1060 and FPGA
`logic 1070, either as separate devices or integrated together. Id. at 24:35–37,
`23:19–22, Fig. 14. Microcontroller 1060 may transfer data between the
`volatile memory 1030 and non-volatile memory 1040. Id. at 24:35–41.
`Logic element 1070 provides signal level translation and address translation
`between the volatile memory and the non-volatile memory. Id. at 24:45–56.
`When the system is operating normally, controller 1062 controls
`switch 1052 to decouple the volatile memory 1030 from controller 1062 and
`the non-volatile memory 1040 (the ’918 patent refers to this as the “first
`state.”). Id. at 24:60–25:7. In response to a power interruption, for example,
`controller 1062 controls switch 1052 to couple the volatile memory 1030 to
`itself and non-volatile memory 1040, and transfers data from the volatile
`memory to the non-volatile memory to prevent its loss (the ’918 patent
`refers to this as the “second state”). Id. at 25:9–20.
`
`Memory system 1010 may comprise a voltage monitor 1050 to
`monitor voltage supplied from the host system via interface 1022. Id. at
`25:8–10. When the voltage monitor 1050 detects a low voltage condition,
`the voltage monitor transmits a signal to the controller 1062 to indicate the
`detected condition. Id. at 25:11–15.
`
`Power may be supplied from a first power supply (e.g., a system
`power supply) when the memory system 1010 is in the first state and from a
`
`5
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`second power supply 1080 when the memory system 1010 is in the second
`state. Id. at 25:54–58. Second power supply 1080 may comprise step-up
`transformer 1082, step-down transformer 1084, and capacitor bank 1086
`with one or more capacitors. Id. at 26:3–13.
`The memory system 1010 further has a third state in which controller
`1062 is decoupled from the volatile memory system 1030 and power is
`supplied to the volatile memory subsystem 1030 from a third power supply
`(not shown). Id. at 25:62–69. “[T]he third power supply may provide
`power to the volatile memory subsystem 1030 when the memory system
`1010 detects that a trigger condition is likely to occur but has not yet
`occurred.” Id. at 25:66–26:3.
`Figure 16 of the ’918 patent is reproduced below.
`
`Figure 16 shows power module 1100 of memory system 1010. Id. at
`27:59–61. Power module 1100 comprises conversion element 1120, first
`power element 1130, and second power element 1140. Id. at 28:7–15,
`
`
`
`6
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`28:20–22. Conversion element 1120 comprises sub-blocks 1122, 1124,
`1126 comprised of various converter circuits such as buck converters, boost
`converters, and buck-boost converters for providing various voltages 1102,
`1104, 1105, 1107 from the outputs of the first and second power elements
`1130, 1140. Id. at 29:18–54. The first power element 1130 may comprise a
`pulse-width modulation power controller generating voltage 1110 from
`voltages 1106, 1108. Id. at 28:13–15. Second power element 1140 may
`comprise capacitor array 1142, buck-boost converter 1144 receiving
`voltages 1106, 1108 and adjusting the voltage for charging the capacitor
`array, and voltage/current limiter 1146, which limits charge current to the
`capacitor array and stops charging the capacitor array 1142 when it reaches a
`certain charge voltage. Id. at 28:62–67. “[P]ower module 1100 provides
`power to [ ] components of the memory system 1010 using different
`elements based on a state of the memory system 1010 in relation to a trigger
`condition.” Id. at 27:61–65.
`Specifically, “[i]n a first state, the first voltage 1102 is provided to the
`memory system 1010 from the input 1106 and the fourth voltage 1110 is
`provided to the conversion element 1120 from the first power element
`1130.” Id. at 28:27–31. “In a second state, the fourth voltage 1110 is
`provided to the conversion element 1120 from the first power element 1130
`and the first voltage 1102 is provided to the memory system 1010 from the
`conversion element 1120.” Id. at 28:32–37. “In the third state, the fifth
`voltage 1112 is provided to the conversion element 1120 from the second
`power element 1140 and the first voltage 1104 is provided to the memory
`system 1010 from the conversion element 1120.” Id. at 28:34–38.
`Transition from the first state to the second state may occur when power
`
`7
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`module 1100 detects a power failure is about to occur, and transition from
`the second state to the third state may occur when it detects a power failure
`has occurred. Id. at 28:39–47.
`Illustrative Claim
`D.
`Of the challenged claims, claims 1, 16, and 23 are independent.
`Independent claim 1, reproduced below with brackets noting Petitioner’s
`identifiers, is illustrative of the claimed subject matter.
`1. [1.a] A memory module comprising:
`[1.b] a printed circuit board (PCB) having an interface
`configured to fit into a corresponding slot connector of a host
`system, the interface including a plurality of edge connections
`configured to couple power, data, address and control signals
`between the memory module and the host system;
`[1.c] a first buck converter configured to provide a first
`regulated voltage having a first voltage amplitude;
`[1.d] a second buck converter configured to provide a second
`regulated voltage having a second voltage amplitude;
`[1.e] a third buck converter configured to provide a third
`regulated voltage having a third voltage amplitude;
`[1.f] a converter circuit configured to provide a fourth
`regulated voltage having a fourth voltage amplitude; and
`[1.g] a plurality of components coupled to the PCB, each
`component of the plurality of components coupled to one or more
`regulated voltages of the first, second, third and fourth regulated
`voltages, the plurality of components comprising:
`[1.h] a plurality of synchronous dynamic random access
`memory (SDRAM) devices coupled to the first regulated
`voltage, and
`[1.i] [1.i.1] at least one circuit coupled between a first portion
`of the plurality of edge connections and the plurality of SDRAM
`devices, [1.i.2] the at least one circuit operable to (i) receive a
`first plurality of address and control signals via the first portion
`of the plurality of edge connections, and (ii) output a second
`plurality of address and control signals to the plurality of
`SDRAM devices, [1.i.3] the at least one circuit coupled to both
`
`8
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`Amidi
`
`Spiers
`
`FBDIMM
`Standards
`Hajeck
`
`
`
`the second regulated voltage and the fourth regulated voltage,
`[1.i.4] wherein a first one of the second and fourth voltage
`amplitudes is less than a second one of the second and fourth
`voltage amplitudes.
`Ex. 1001, 38:19–44.
`Evidence
`E.
`Petitioner relies on the following references (see Pet. 3, 10–14), as
`well as the Declaration of Dr. Andrew Wolfe (Ex. 1003).
`Reference Exhibit No.
`Patent/Printed Publication
`Harris
`1023
`U.S. Patent Pub. No. 2006/0174140 A1 to
`Harris, published August 3, 2006
`U.S. Patent No. 7,724,604 B2, issued May 25,
`2010
`U.S. Patent Pub. No. 2006/0080515 A1,
`published April 13, 2006
`1027, 1028 JESD82-20 and JESD205 standards published
`March 2007
`U.S. Patent No. 6,856,556 B1 to Hajeck, issued
`February 15, 2005
`Prior Art and Asserted Grounds
`F.
`Petitioner asserts that claims 1–30 are unpatentable on the following
`Grounds (Pet. 3):
`Claims Challenged 35 U.S.C. §
`1–3, 8, 14, 15, 23
`103(a)
`1–30
`103(a)
`1–30
`103(a)
`1–30
`103(a)
`1–30
`103(a)
`
`References
`Harris, FBDIMM Standards
`Harris, FBDIMM Standards, Amidi
`Harris, FBDIMM Standards, Amidi,
`Hajeck
`Spiers, Amidi
`Spiers, Amidi, Hajeck
`
`1024
`
`1025
`
`1038
`
`9
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`III. ANALYSIS OF CHALLENGED GROUNDS
`We now consider Petitioner’s asserted grounds of unpatentability and
`Patent Owner’s arguments to determine whether Petitioner has demonstrated
`by a preponderance of the evidence that the challenged claims would have
`been obvious under 35 U.S.C. § 103. See 35 U.S.C. § 316(e) (petitioner has
`the burden of proving unpatentability by a preponderance of the evidence).
`
`Principles of Law
`A.
`A claim is unpatentable under 35 U.S.C. § 103(a) if “the differences
`between the subject matter sought to be patented and the prior art are such
`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations, including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of skill in the art; and (4) objective evidence of nonobviousness,
`i.e., secondary considerations. See Graham v. John Deere Co., 383 U.S. 1,
`17–18 (1966).
`A patent claim “is not proved obvious merely by demonstrating that
`each of its elements was, independently, known in the prior art.” KSR, 550
`U.S. at 418. An obviousness determination based on the teachings of
`multiple references requires finding “both ‘that a skilled artisan would have
`been motivated to combine the teachings of the prior art references to
`achieve the claimed invention, and that the skilled artisan would have had a
`reasonable expectation of success in doing so.’” Intelligent Bio-Sys., Inc. v.
`Illumina Cambridge Ltd., 821 F.3d 1359, 1367–68 (Fed. Cir. 2016) (citation
`
`10
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`omitted); see also KSR, 550 U.S. at 418. Further, an assertion of
`obviousness “cannot be sustained by mere conclusory statements; instead,
`there must be some articulated reasoning with some rational underpinning to
`support the legal conclusion of obviousness.” KSR, 550 U.S. at 418; In re
`NuVasive, Inc., 842 F.3d 1376, 1383 (Fed. Cir. 2016) (a finding of a
`motivation to combine “must be supported by a ‘reasoned explanation’”).
`Level of Ordinary Skill in the Art
`B.
`Factors pertinent to a determination of the level of ordinary skill in the
`art include “(1) the educational level of the inventor; (2) type of problems
`encountered in the art; (3) prior art solutions to those problems; (4) rapidity
`with which innovations are made; (5) sophistication of the technology; and
`(6) educational level of active workers in the field.” Envtl. Designs, Ltd. v.
`Union Oil Co. of Cal., 713 F.2d 693, 696 (Fed. Cir. 1983) (citing Orthopedic
`Equip. Co. v. All Orthopedic Appliances, Inc., 707 F.2d 1376, 1381–82 (Fed.
`Cir. 1983)). “Not all such factors may be present in every case, and one or
`more of these or other factors may predominate in a particular case.” Id. at
`696–697. The prior art may reflect an appropriate level of skill. Okajima v.
`Bourdeau, 261 F.3d 1350, 1354–55 (Fed. Cir. 2001).
`Petitioner asserts a person of ordinary skill in the art “would have had
`an advanced degree in electrical or computer engineering, or a related field,
`and two years working or studying in the field of design or development of
`memory systems, or a bachelor’s degree in such engineering disciplines and
`at least three years working in the field.” Pet. 8–9 (citing Ex. 1003 ¶ 67).
`Petitioner contends that additional training can substitute for educational or
`research experience, and vice versa. Id. at 8. Petitioner asserts that such a
`hypothetical person would have been familiar with the JEDEC industry
`
`11
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`standards, and knowledgeable about the design and operation of
`standardized DRAM and SDRAM memory devices and memory modules
`and how they interacted with a memory controller and other parts of a
`computer system, including standard communication busses and protocols,
`such as PCI and SMBus busses and protocols. Id. at 8–9. Petitioner further
`contends that such “a hypothetical person would also have been familiar
`with the structure and operation of circuitry used to access and control
`computer memories, including sophisticated circuits such as ASICs, FPGAs,
`and CPLDs, and more low-level circuits such as tri-state buffers.” Id. at 9.
`Petitioner further asserts that such “a hypothetical person would further have
`been familiar with voltage supply requirements of such structures (e.g.,
`memory modules, memory devices, memory controller, and associated
`access and control circuitry), including voltage conversion and voltage
`regulation circuitry.” Id.
`Patent Owner indicates “[f]or the purposes of this [Response], Patent
`Owner is applying the level of ordinary skill in the art proposed by
`Petitioner” for this proceeding. Resp. 1.
`The evidence that Petitioner presents mostly applies to the educational
`level and experience of workers in the field, but also touches upon other
`factors as well, including problems and solutions in the prior art and
`complexity of the technology. See Pet. 7–8. We find Petitioner’s proposal
`is consistent with the level of ordinary skill in the art reflected by the ’918
`patent and the prior art of record, and, therefore, we adopt Petitioner’s
`proposed level of ordinary skill in the art, with the exception of the open-
`ended language “at least” which introduces ambiguity and may encompass
`skill levels beyond ordinary. See Okajima v. Bourdeau, 261 F.3d 1350,
`
`12
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`1355 (Fed. Cir. 2001) (the prior art may reflect an appropriate level of skill
`in the art).
`C. Claim Construction
`We construe claim terms “using the same claim construction standard
`that would be used to construe the claim in a civil action under 35 U.S.C.
`282(b).” 37 C.F.R. § 42.100(b) (2021). There is a presumption that claim
`terms are given their ordinary and customary meaning, as would be
`understood by a person of ordinary skill in the art in the context of the
`specification. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed.
`Cir. 2007). Nonetheless, if the specification “reveal[s] a special definition
`given to a claim term by the patentee that differs from the meaning it would
`otherwise possess[,] . . . the inventor’s lexicography governs.” Phillips v.
`AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005) (en banc) (citing CCS
`Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002)). “In
`determining the meaning of the disputed claim limitation, we look
`principally to the intrinsic evidence of record, examining the claim language
`itself, the written description, and the prosecution history, if in evidence.”
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312–17). Only disputed claim
`terms must be construed, and then only to the extent necessary to resolve the
`controversy. See Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co.
`Matal, 868 F.3d 1013, 1017 (Fed. Cir. 2017).
`“Memory Module”
`1.
`Patent Owner contends as follows:
`The term “memory module” appears in the preamble of the
`independent claims, which provides antecedent basis for the
`same term in the body of the text. The preamble is thus limiting
`
`13
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`as the District Court found after reviewing the specification in
`detail.The Court further explained that “a skilled artisan would
`understand a ‘memory module’ is distinct from, and has essential
`structural requirements not necessarily found in, other modular
`computer accessories. That includes the structure necessary to
`connect to a memory controller.
`Resp. 1–2 (citing Ex. 2032, 28; Ex.2034, 319). Patent Owner argues that the
`“court’s ruling is consistent with the specification which states in the
`Overview section that the invention is particularly ‘couplable to a memory
`controller of a host system.’” Id. at 2 (citing Ex. 1001, 1:66–67, 3:66–67).
`Patent Owner states that Petitioner “objected to the court’s finding that the
`memory module is limiting, but does not dispute the Court’[s] finding on
`what a ‘memory module’ means to a [person of ordinary skill in the art].”
`Id. (citing Ex. 2033, 4).
`As support for its argument, Patent Owner relies on a claim
`construction order issued by the District Court for the Eastern District of
`Texas, which states as follows:
`the entire patent “to gain an
`Having reviewed
`understanding of what the inventors actually invented and
`intended to encompass by the claim[s],” Catalina Mktg. Int'l, 289
`F.3d at 808–09, the Court finds the preamble limiting. While the
`claims recite many of the structural requirements of a “memory
`module,” the claims arguably read on other modular computer
`devices, such as a video card or network controller, despite no
`evidence the inventors intended to encompass such devices by
`the claims. To the contrary, as the Overview section [of the
`Court’s claim construction order] explains, the invention “is
`couplable to a memory controller of a host system,” [Ex. 1001]
`at 3:66–67 (emphasis added), not just the host system as recited
`in the claims. See also id. at 1:66–67 (“[t]he present disclosure
`relates generally to computer memory devices”). Thus, a skilled
`artisan would understand a “memory module” is distinct from,
`
`14
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`
`and has essential structural requirements not necessarily found
`in, other modular computer accessories. That includes the
`structure necessary to connect to a memory controller. See
`Memory Systems: Cache, DRAM, Disk, Dkt. No. 76-17 at 319
`(depicting, in FIG. 7.6, a memory controller connected to two
`memory modules). Accordingly, the preambles are limiting.
`
`
`Ex. 2032, 28) (alterations in original), cited in Resp. 2.
`Patent Owner argues that Petitioner’s expert, Dr. Wolfe, testified that
`the term “memory modules” typically refers to “main memory modules,”
`which “are designed to connect to the primary memory controller for the
`purpose of holding general purpose code and data in a computer system.”
`Id. at 2 (citing Ex. 2030, 123:14–25; Ex. 2056, 100:15–101:8 (by
`2004–2005, a memory module “was intended to go into a dedicated memory
`slot and not a general-purpose IO slot”)). Patent Owner contends that the
`’918 patent’s usage of “memory module” is consistent with that
`understanding, and asserts that we should adopt the District Court’s claim
`construction, including that the claimed “memory module” includes
`structures necessary to connect to a memory controller. Id. at 2–3 (citing
`Ex. 2031 ¶¶ 51–53); accord Sur-Reply 1.
`
`In Reply, Petitioner contends that we properly found that Harris, the
`FBDIMM Standards, Amidi, and Spiers all disclose a “memory module” in
`our Institution Decision. Reply 1–2 (citing Inst. Dec. 14–15, 17–18, 34–37,
`45; Pet. 19–20, 82–83; Reply 23–26). Petitioner contends that the District
`Court’s construction did not limit “memory module” to only “main memory
`modules . . . designed to connect to the primary memory controller.” Id. at
`1–2 (emphasis in original) (citing Resp. 2; Ex. 2032, 26–28, 35; Ex. 2030,
`125:12–127:13; Ex. 2056, 100:15–101:19).
`
`15
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`In Sur-Reply, Patent Owner disagrees with Petitioner’s contention that
`
`“memory module” is not limited to “main memory modules . . . designed to
`connect to the primary memory controller.” Sur-Reply 1 (emphasis in
`original) (citing Reply 1). Patent Owner argues that Petitioner’s contention
`“ignores the District Court’s finding based on intrinsic evidence—which
`[Petitioner] did not object to—that the ‘invention [i.e., the claimed memory
`module] ‘is couplable to a memory controller of a host system,’ [Ex. 1001]
`at 3:66–67 …, not just the host system as recited in the claims.”’ Id. (citing
`Ex. 2032, 28; Ex. 1001, 4:5–12, 4:14–24, 4:35–39, 4:45–51, 5:4–20, 4:36–
`50, 6:4–6, 6:25–29, 6:61–66, 7:1–4, 7:21–25, 7:29–34, 7:43–49, 7:54–57,
`21:24–25, 22:53–58, 23:19–22, 26:43–51, 23:41–44).
`
`The District Court’s Claim Construction Order (Ex. 2032) issued after
`our Institution Decision (Paper 10). Although Petitioner argued in the
`District Court litigation that the claim preambles were not limiting,
`Petitioner does not appear to maintain that argument here following the
`District Court’s determination that the preambles were limiting. Ex. 2032,
`28. Since the term is recited in both the preambles and bodies of these
`claims, there is evidence that the inventors of the ’918 patent intended the
`term to limit the claim, as the District Court determined. See Catalina Mktg.
`Int’l., Inc. v. Coolsavings,com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002)
`(citing Bell Commc’ns Rsch., Inc. v. Vitalink Communications Corp., 55
`F.3d 615, 620 (Fed.Cir.1995) (“dependence on a particular disputed
`preamble phrase for antecedent basis may limit claim scope because it
`indicates a reliance on both the preamble and claim body to define the
`claimed invention.”)).
`
`16
`
`
`
`IPR2022-00996
`Patent 11,016,918 B2
`
`We agree with Petitioner’s contention that “memory module” is not
`
`limited to “main memory modules . . . designed to connect to the primary
`memory controller.” Reply 1. The ’918 patent states
`In certain embodiments, the device contains a high density
`Flash memory with a low density DRAM, wherein the DRAM is
`used as a data buffer for read/write operation. The Flash serves
`as the main memory.
`Ex. 1001, 11:3–6 (emphases added). This is the only mention of “main
`memory” in the ’918 patent. That the Flash memory serves as “main
`memory” in “certain embodiments” implies that there may be other
`embodiments in which this is not the case. Accordingly, we agree with
`Petitioner that the term “memory module” is not limited to “main memory
`modules . . . designed to connect to the primary memory controller.” See
`Reply 1.
`
`We agree with Patent Owner that the “memory module” includes
`structure to connect with a “host system” including its memory controller.
`See, e.g., Ex. 1001, code (57), 12:52–59. The claims do not mention a
`“memory controller” but they do mention that the “memory module” has an
`“interface” to connect with a “host system.” Ex. 1001, 38:19–24 (claim 1),
`39:54–59 (claim 16), 40:51–56 (claim 23). That the “me
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
