FUIIi BUffered DIMM (FBMDIMM)
`Design Considerations
`
`Howard David
`Memory Architect
`
`Michael McTague
`Staff Engineer
`
`Intel Corp.
`
`Feb 18, 2004
`
` -Intel
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`
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`'Agenda
`
`I
`
`_
`
`lw—
`
`• FB-DIMM Architecture
`• FB-DIMM Channel Electrical Characteristics
`• FB-DIMM Physical Design
`• FB-DIMM System Design Considerations
`
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`riiithi Platform Memory Technology RoaTdmap"
`
`DDR3
`
`DDR2
`
`DDR
`
`I] I] PE I'I'lL*lcI
`
`FB-DIMM
`
`DDR2 667/800
`
`DDR3
`
`aDDR333L400
`DDR266
`
`RDRAM*
`
`PCI 066
`
`ftC80t
`
`SDRAM
`
`L20051
`
`-
`
`• DDR2 400/533 support in all main IA segments in 2004
`with DDR flexibility
`• FB -DIMM new server interconnect in 2005
`• Low Power SDRAM moving to low power DDR
`• RDRAM still used in specific applications
`
`
`
`in
`
`*Oth er names and brands may be claimed as the property of others
`
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`FB-DIMM Architecture
`FB-DIMM Block Diagram
`
`DRAM interface is entirely behind the buffer
`- DDR2 DRAM scales from 533 to 800 MT/s, with up to
`8 DlMMs (288 devices) per channel
`
`Commodity
`DRAMs
`
`Upto8
`DlMMs
`
`Differential Pairs
`
`DRAM!
`:bRAM1
`
`Buffer
`
`E Buffer
`
`Memory
`Controller
`
`14
`
`DRAM!
`
`DRAM!
`
`DRAM!
`6RAM1
`
`Buffer
`
`-
`
`DRAM!
`
`DRAM!
`
`SMBus
`I
`
`
`CLK
`Source
`
`in
`
`DRAM
`
`DRAM
`
`DRAM
`
`DRAM
`
`. .
`
`Buffer
`
`DRAM
`
`DRAM
`
`DRAM
`
`DRAM
`
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`FB-DIMM Architecture
`FB-DIMM Module Block Diagram
`
`Read Data
`(Primary Northbound)
`
`Pass-through
`& Merging
`Logic
`
`Read Data
`(Secondary Northbound)
`
`AMB is the new
`buffer
`technology for
`server memory
`
`Serializer
`
`K
`
`Data Bus/'
`N
`Interface\
`
`DRAM Data
`
`I
`
`-\
`
`9to36
`DRAM
`
`De-serializer
`& Decode
`Logic
`
`DRAM C/A Copy A
`
`DRAM C/A Copy B
`
` I
`
`Reference Clock
`
`Clocking
`
`DRAM Clocks
`
`Write Data and Command
`(Primary Southbound)
`
`Pass-
`through
`Logic
`
`Write Data and Command
`(Secondary Southbound)
`
`in
`
`'Advanced
`Memory Buffer
`(AMB)
`
`SMBus
`
`SPD
`EEPROM ,.In teI
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`FB-DIMM Channel Electrical Characteristics
`Signaling Characteristics
`
`• Differential point-to-point, 50 Q termination
`• DC coupled, current mode driver
`• Derived clocking (mesochronous clocking)
`• Transmitter de-emphasis to reduce ISI
`• 3.2 Gbls, 4.0 Gbls, and 4.8 Gb/s data rates
`
`•1•
`
`Tx
`
`Rx
`
`Sync
`
`PLL
`
`int&
`
`Reference
`CLK
`
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`FB-DIMM Channel Electrical Characteristics
`Differential Signaling
`
`Parameter
`
`VDlFFp-p
`
`VCM-AC
`
`VCM-DC
`
`Description
`
`Differential Peak to
`Peak Voltage
`
`AC Common Mode
`Voltage
`
`DC Common Mode
`Voltage
`
`Equation
`2*max[VD+ - VD-]
`
`(VD+ + VD-)/2
`
`AVG[(VD+ + VD-)/2]
`
`D-
`
`D+
`
`V D +
`
`VD -
`
`V C M -AC
`
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`FB-DIMM Channel Electrical Characteristics
`Tx Voltage Spec
`
`(Medium drive strength example)
`
`0
`
`Parameter
`VTX-DIFF , -Mm
`D+, b-
`VTX-DIFF P-P-Min,
`-3.5 Db
`
`VTX-DIFF P-P-Min,
`-6.0 Db D+
`VTX-DIFF P-P-Min,
`-9.0 Db
`
`VTX-SE
`
`Description
`
`Min
`
`Max
`
`Differential Swing,
`De-emphasisi off
`
`Differential swing,
`De-emphasis on
`
`Differential swing,
`De-emphasion
`
`Differential swing,
`De-emphasis on
`
`Single Ended Swing
`nit
`
`800 my
`1
`505 my
`
`357 my
`a
`239 my
`
`566 my
`
`450 my
`
`301 my
`
`700 my
`
`int&
`
`a
`
`1
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`-
`
`—
`
`YFB-DIMM Channel Electrical Characteristics IN
`Tx Timing Spec
`
`I I
`
`Silt
`Si S
`I I S
`
`i ill
`
` S ;I5
`ut
`I 5
`ul.
`t t
`IF
`IS
`it
`
`U min spec
`
`Tx
`Total
`
`S 'a
`S
`I
`S
`I
`Data ea rl y 8
`
`11.
`H
`
`Median
`J itte r
`
`Median to max
`Jitter
`
`Data late
`
`VTx ditfmin p-p
`
`r
`
`4
`St
`It
`I
`I St
`I
`I
`
`S
`I
`I
`S
`I,
`
`A
`5'.
`
`I a'
`I I
`It
`I,
`
`I'
`I'
`II
`
`I
`I
`
`*
`5
`
`S
`I
`
`-
`
`Median
`Jitter
`
`UI rn in TX m mn 2 TX m edian torn axjitter 0
`
`Transfer
`Rate
`(Gbls)
`
`3.2
`
`4.0
`
`4.8
`
`UI
`Nom
`
`(Ps)
`
`312.0
`
`250.0
`
`208.0
`
`TTx-Total-
`mm
`
`TTX-Eye-Median-Max-Jitter
`(PS)
`
`(PS)
`
`248.5
`
`191.0
`
`157.0
`
`32.0
`
`29.5
`
`25.68
`
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`-
`
`-
`
`YFB-DIMM Channel Electrical Characteristics
`RxSpec
`
`Daacrxint
`
`D*,aacrptt
`
`TR-Tdal-Mn
`
`0.4
`
`0,2
`
`0
`
`.0.2
`
`.0,4
`
`u'r •Th&.<
`— -rr-
`srr
`UAW
`
`4t
`
`Data
`Rate
`(Gbls)
`
`3.2
`
`4.0
`
`4.8
`
`UI, Nom
`(ps)
`
`TRX-Total-
`Mm (ps)
`
`TRX-EYE-
`Median-Max
`Jitter (ps)
`
`312.0
`
`250.0
`
`208.0
`
`115
`
`90
`
`75
`
`98.67
`
`80.0
`
`66.68
`
`int&
`
`-Measured
`-Simulated
`
`V DIFFppMIN (my)
`
`170
`
`170
`
`170
`
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`-
`
`-
`
`YFB-DIMM Channel Electrical Characteristics IN
`Clock Spec
`• HCSL (High-Speed Current Steering Logic) clock
`
`• 0.7vswing
`
`• 1/4th of the DDR2 DRAM frequency (133, 166, and 200 MHz)
`
`• Spread Spectrum Clock (SSC) with up to —0.5% down spread
`
`• Reference clock jitter specified to allow standard clock buffers.
`
`Zo d = 100
`
`<0.2"
`
`ZOd — lOO
`
`Zod = 100
`
`<0.2"
`
`330
`
`<TBD"
`
`-2.5"
`
`500
`
`500
`
`FB-DIMM
`Connector
`
`0.5"
`
`DBxxx
`Clock
`Driver
`
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`FB-DIMM Channel Electrical Characteristics
`Interconnect Modeling
`
`• Three (3) Topologies supported
`• Accurately models connection from Tx pin to Rx pin
`• Non-Interleaved routing with no bit to bit length matching required
`• Differential signaling design rules
`
`Tx Package
`
`Southbound Interconnect Network
`(Memory Writes)
`
`Rx Package
`
`U
`
`• Package Breakout
`• Lossy Transmission Lines
`• Connectors
`• Vias
`• Sockets and test points
`
`00
`
`00
`
`Not Equivalent due to 01MM Routing and connector location
`
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`F13-DIMM Channel Electrical Characteristics
`FB-DIMM Topologies
`
`DIMMs on Motherboard
`
`Memory
`Controller
`
`Base Board
`A
`\4 4
`
`FB-DIMM
`
`( AMB
`
`FB-.DlMM Connector
`
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`FB-DIMM Channel Electrical Characteristics
`FB-DIMM Topologies
`
`DIMMs on a Riser Card
`
`Memory
`Riser Board
`
`FB-DIMM Connector
`
`Memory
`Controller
`
`Base Board
`
`FB-DIMM
`
`AMB
`
`4/
`
`PCI Express* or
`pin and socket
`connector
`
`int&
`
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`FB-DIMM Channel Electrical Characteristics
`FB-DIMM Topologies
`
`DIMM to DIMM
`
`FB-DIMM
`
`FB-DIMM
`
`I
`
`Base Board
`
`\
`
`AMB
`
`1ti
`
`It
`
`AMB
`
`____
`
`•/1
`
`
`
`FB- DIMM connectors
`
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`FB-DIMM Channel Electrical Characteristics
`Interconnect Components
`• Package Models
`— Return Loss (<-10 Db)
`• PCB Model
`— Impedance, delay, and loss characteristics of traces
`— 3 pair, non-interleaved, cross talk model
`— VIA Models
`• Connector(s)
`— 3D Models validated using Measurements
`
`MC Vendor Model
`
`W Element
`
`W Element
`
`AM B Vendor Model
`
`Package
`Network
`
`Parkag
`N wow or
`
`0050 Ohm
`
`85 ohm
`Strip Line
`
`a
`FBD DDR2
`Connector
`Model
`
`85 ohm
`M icros trip
`Breakout
`
`85 ohm Strip Line
`
`e Vias
`
`inteL
`
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`FB-DIMM Channel Electrical Characteristics
`FB-DIMM Connector
`• Standard DDR2 Connector wl FB-DIMM connector spec
`• Characterized up to 8 GHz
`• WD Spice Model based on FOXCONN* Connector Data
`
`-
`
`-
`
`ufllk o.—btfl
`
`10
`
`L3IP21A offs*te !dj LOIS COG! LUt} flQvOI.i
`
`Th
`/
`
`4"
`
`is t as
`rmqsOw
`
`Ow
`
`• Less than I Db insertion loss.
`
`• Less than 3.2% Far end Cross talk
`
`• Less than 10 Db insertion loss
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`FB-DIMM Channel Electrical Characteristics
`Channel Design Rules
`• Channel impedance: 85 ohms, normal distribution
`• Microstrip trace geometry
`- w=6m, s= 4x h , tolerance = +/- 20%, etc.
`• Strip line trace geometry
`- w= 5 mil, s = 3x h, tolerance = +1-15%, etc
`• Asymmetric strip line geometry
`- w = 5 mil, s = 4x h , tolerance = +1-15%, etc, etc
`• Loss tangent 0.017 to 0.025, a - 3.4 (FR4 materials)
`
`ef
`
`II
`
`I-*i
`
`I-C
`
`d 1 Cr2
`H
`
`h2
`
`int&
`
`Cr2
`
`hi
`
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`FB-DIMM Channel Electrical Characteristics
`Channel Validation
`1. Tx Stand alone Test
`
`... oollooll...
`
`2. Interconnect meets Rx
`Eye Spec
`
`Tx Package
`
`Tx Eye
`Specification
`
`2 x 50 ohms
`
`Worse Case
`181 Pattern
`
`Interconnect Network
`
`Rx Eye
`Specification
`
`2x50 ohms
`
`3. Rx Meets BER with
`Minimum Eye
`
`Tx Package
`
`Rx Package
`
`Worse Case
`181 Pattern
`
`Interconnect Network
`
`FB-DIMM channel requires new
`memory design techniques
`
`in
`
`Pattern Check
`or "On-die"
`Measurement
`
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`FB-DIMM Physical Design
`Mechanical Prototype
`
`-- t-'tt I •? 1:
`
`17,
`
`¶11
`
`WUUUUU**LUMLUUIUWWIII!L'
`
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`F13-DIMM Physical Design
`Physically Compatible Approach
`
`• FB-DIMM fits into existing system infrastructure
`
`Registered DIMM
`
`FB-DIMM
`
`Max Dimension
`
`133.5 x 305 mm
`
`1315 x 30.5 mm
`
`Gold fingers
`
`240
`
`240
`
`Key position 4 mm right of center 8 mm right of center
`
`#otDRAM
`
`9,18 or 36
`
`9. 18 or 36
`
`DRAM Outline
`
`12.3x21.9nini
`
`12.3x21.9mm
`
`Silicon Support
`Components
`
`1.2 or 4 registers
`1 PLL clock buffer
`1 SPD [[PROM
`
`I Advanced Memory
`Buffer (AMB)
`I SPD [[PROM
`
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`

`FB-DIMM Physical Design
`DIMM Mechanical Outline
`
`inc
`
`çb 3 fl (w
`)P.acL
`
`18X ( )
`
`169 6
`
`AMB on front
`
`Retention notches
`reduced to 2.5 mm
`
`Nominal
`4 jpight
`
`4X 2.
`
`8 DRAM on front,
`10 DRAM on back
`
`2X 21
`
`2 6.4
`
`SEE VILIt C
`
`SEE IbII&lL E.
`
`in
`
`Key moved
`
`ILg
`COIIFW1LNT AFID TRACI
`KtCou1 ZoulS SEC D0410 A 5
`
`U DET AIL C
`SCaL 8.ODU
`
`New end
`notches
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`

`F13-DIMM Physical Design
`Advanced Memory Buffer (AMB)
`• New 0.8 mm ball pitch package
`—24.5mm x 19.5 mm x 2.15 mm
`- (29 columns x 23 rows) — 12 corner balls = 655 balls
`
`-------
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`Channel
`,."'Intel
`[Dave'] op ea'
`Forum
`
`23
`
`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`FB-DIMM Physical Design
`FB-DIMM Bus Topologies
`• Bus topologies scale to higher frequencies than the
`registered DlMMs
`- DRAM farthest from AMB gets latest clock, C/A and data
`
`Data bus
`
`C/A bus
`
`Registered DIMM
`Stub Topology up to
`657,1 one DIMM per
`channel at 800 &
`higher
`One unterminated
`tree at 400/533,
`2 at 667 & higher
`
`Clock bus
`
`P-to-P 10 1; 2 or 4
`DRAM
`
`F113-DIMM
`
`One or two DRAM at
`the end of a
`
`15-75 mm trace
`
`Two terminated daisy
`chains
`
`Two or tour
`terminated daisy
`chains
`
`int&
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`evei op ar
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`IPR2022-00996
`
`

`

`YFB:DIMM Physical Design
`Thermal Solution for x8 based DlMMs
`
`• x8 DlMMs will have an AM B-only heat spreader
`- Attached using a spring clip, inserted into two holes
`• Stacked BGA and dual die x4 DlMMs under investigation
`
`in
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`evei op ar
`Forum
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`IPR2022-00996
`
`

`

`FB-DIMM Physical Design
`Raw Cards under Design
`
`The JEDEC DIMM and Socket Task Group is
`standardizing these DlMMs: (R/C=Raw Card)
`—RIC A
`SR x8
`9 DRAM
`—RIC B
`DR x8
`18 DRAM
`—RIC C
`SR x4
`18 DRAM
`—RIC D
`DR x4
`36 DRAM (Stacked)
`
`• All DlMMs will fit standard MO & are designed to
`meet signal integrity, timing and power delivery
`
`• FB-DIMM channels will be routed to same rules
`r DRAM fritrface is -self-contained on
`industry standard DIMMs
`
`ifltJ
`
` Forum
`
`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`FB-DIMM System Design Considerations
`System Design Overview
`
`• FB-DIMM uses standard baseboard technology
`—With 6 layers, can route 4 FB-DIMM channels
`—Compared to 2 "stub bus" DDR2 channels
`
`• Will support standard pitch of 0.4"
`- Evaluating wider pitch for stacked BGA x4 DlMMs
`
`• Three voltage regulators for DRAM and buffer
`—1.8V for DDR2 DRAM
`- O.9V to terminate DRAM C/A
`—1.5v for AMB
`
`int&
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`,.In teI
`evei op ar
`Forum
`
`27
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`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`YFB:DlMM System Design Considerations
`Cooling
`
`• Need to meet component requirements:
`- Normal refresh: DRAM Tcase ≤ 85°C
`(tREFl7.8u5)
`- 2X refresh: DRAM Tcase 95°C
`(tREFl3.9us)
`- AMB Tcase ≤ 105°C
`
`• Recommend ducted air flow at 1.5-3.0 mIs inlet air speed
`- A function of inlet air temperature and application
`
`• 1st DIMM on channel is highest AMB power - typ. 3.4W
`
`• Last 01MM on Channel is lowest AMB power - typ. 2.4W
`- Secondary channel disabled
`
`• Memory Controller will throttle activity to meet Tcase
`- Algorithm enhanced by AMB thermal sensor
`
`int&
`
` .InteI
`evei op ar
`Forum
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`28
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`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`VFB-DIMM System Design Considerations
`8 DIMM Layout
`• Non-interleaved DIMM
`layout
`Better for thermals
`
`-
`
`• 0.4" DIMM-to-DIMM
`
`• Length matching not
`required
`
`• Shortest lead-in 1.2"
`- Southbound channel 0
`
`• Longest lead-in 7.3"
`- Northbound channel 3
`
`int&
`
`Intel will present detailed design
`guidelines at Fall'04 OF
`
`,.In teI
`evei op ar
`Forum
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`Samsung v Netlist
`IPR2022-00996
`
`

`

`1
`
`I
`
`rsumma
`Summary
`• AMB is the new buffer technology for server
`memory
`• FB-DIMM channel requires new memory design
`techniques
`• DRAM interface is self-contained on industry
`standard DlMMs
`• Intel will present detailed design guidelines at
`Fall'04 OF
`
`IFB-DIMM is the next server memory technology
`,.InteI
`iio'rYT
`ForuWJ
`
`inteL
`
`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Please fill bUtthO Session
`Evaluation Form.
`
`Thank You'.
`
`int&
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`,.In teI
`evei op ar
`Forum
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`IPR2022-00996
`
`

`

`int&
`
`N,
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`Netlist Ex 2101
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`IPR2022-00996
`
`

`

`r"Acronyms
`
`1
`
`•AMB
`'IS'
`•Tx
`•Rx
`• P-to-P
`•BER
`•PCB
`•MCH
`'MO
`•RIC
`• JEDEC
`'C/A
`
`int&
`
`Advanced Memory Buffer
`Inter-Symbol Interference
`Transmitter
`Receiver
`Point-to-point
`Bit Error Rate
`Printed Circuit Board
`Memory Controller Hub
`Mechanical Outline
`Raw Card
`JEDEC Solid State Technology Association
`Command/Address
`
`,.In teI
`evei op ar
`Forum
`
`33
`
`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Bifdsof-a 1Feathbr Lunch Discuss ions
`
`Where: Level 3 Foyer (Not in the main lunch area)
`Arrive early - seating is limited
`• When:
`
`Wednesday 12PM - 1:30PM
`802 .11*
`
`802 .16*! WiM ax*
`
`Server Manageability
`Client Manageability
`
`DMTF* Server Manageability
`Working Group
`IPMI (Intelligent Platform
`Management Interface)
`Thursday 12PM - 1:30PM
`Enthusiast PC
`Trusted Computing Group for More
`Secure Computing
`Extended Battery Life
`
`InteL
`
`Extensible Firmware Interface
`(EFI)
`Latin America Mobile/Data
`Services
`Advanced TCA*
`Advanced Switching based on
`PCI Express* Architecture
`Connecting consumers in the
`digital home
`
`Ethernet in the Datacenter
`Advanced Switching based on
`PC] Express* Architecture
`
`34
`
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`evei op eaa
`Forum
`
`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Round Tàblesfor Innovation
`Where: Level 2— Alcoves across from Rooms 2018-2024
`Immediately following Solution Keynotes
`
`What: This is your chance to focus on relevant issues, compare notes with
`colleagues, and gain insight from professionals who face similar challenges.
`When: Tuesday 17th from 4:15 to 6:00pm
`Topics:
`• Emerging worker models for the highly connected employee
`• Improving PC usability
`• IT Benchmarking Programs
`• Technology and Work/Life Balance
`• Internal IT Consulting Model
`• Managing wireless networks
`• Prod uctivity/collaboration/eWorkforce
`• Capturing IT Business Value and ROI
`• Mobilized Software: Addressing Technology and Business Challenges Consistently
`• Creating Mobility Business Value in the Enterprise
`• Reducing Costs and Increasing Revenue with Secure WLAN Solutions
`• Achieving Competitive Advantages with Real-time Mobile Business Solutions
`• Collaborating with Mobility
`• Mobile Point of Care Solutions for Healthcare
`• RFID technologies transforming the Retail environment
`Ifliel.
`
`Forum
`
` .In
`
`35
`
`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`

`

`IflteL
`
`N,
`
`Netlist Ex 2101
`Samsung v Netlist
`IPR2022-00996
`
`