UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`
`Patent Owner,
`
`_____________________________
`
`Case No. IPR2022-00615
`
`Patent No. 7,619,912
`
`_____________________________
`
` REMOTE VIDEOTAPED DEPOSITION BY VIRTUAL ZOOM OF
`
`ANDREW WOLFE, PH.D.
`
`WEDNESDAY, JANUARY 4, 2023
`
`Reported by:
`
`Ashala Tylor, CSR #2436, CLR, CRR, RPR
`
`JOB NO. 5621734
`
`PAGES 1 - 233
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`Netlist Ex 2056
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`IPR2022-00996
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` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`
`Patent Owner,
`
`_____________________________
`
`Case No. IPR2022-00615
`
`Patent No. 7,619,912
`
`_____________________________
`
` REMOTE VIDEOTAPED DEPOSITION BY VIRTUAL ZOOM OF
`
`ANDREW WOLFE, PH.D.
`
`WEDNESDAY, JANUARY 4, 2023
`
`Reported by:
`
`Ashala Tylor, CSR #2436, CLR, CRR, RPR
`
`JOB NO. 5621734
`
`PAGES 1 - 233
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` UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` SAMSUNG ELECTRONICS CO., LTD.,
`
` Petitioner,
`
` v.
`
` NETLIST, INC.,
`
` Patent Owner,
`
` _____________________________
`
` Case No. IPR2022-00615
`
` Patent No. 7,619,912
`
` _____________________________
`
` Videotaped deposition of ANDREW WOLFE, PH.D.,
`
`taken via virtual Zoom, commencing at 9:04 a.m. and
`
`ending at 6:38 p.m., on Wednesday, January 4, 2023,
`
`before Ashala Tylor, CSR No. 2436, RPR, CRR, CLR.
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`APPEARANCES OF COUNSEL:
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`FOR THE PETITIONER, SAMSUNG ELECTRONICS CO., LTD.:
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` BAKER BOTTS LLP
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` BY: TED CHANDLER, ESQ.
`
` 101 California Street
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` Suite 3600
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` San Francisco, California 94111
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` ted.chandler@bakerbotts.com
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` - and -
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` BAKER BOTTS LLP
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` BY: FERENC PAZMANDI, ESQ.
`
` 1001 Page Mill Road
`
` Suite 200
`
` Palo Alto, California 94304
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` ferenc.pazmandi@bakerbotts.com
`
`///
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`A P P E A R A N C E S ( c o n t i n u e d )
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`F O R T H E P A T E N T O W N E R , N E T L I S T , I N C . :
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` I R E L L & M A N E L L A L L P
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` B Y : H . A N N I T A Z H O N G , E S Q .
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` M I C H A E L T E Z Y A N , E S Q .
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` 1 8 0 0 A v e n u e o f t h e S t a r s
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` S u i t e 9 0 0
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` L o s A n g e l e s , C a l i f o r n i a 9 0 0 6 7
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` ( 3 1 0 ) 2 0 3 - 7 9 3 6
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` h z h o n g @ i r e l l . c o m
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` m t e z y a n @ i r e l l . c o m
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` I N D E X
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`WITNESS EXAMINATION BY PAGE
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`ANDREW WOLFE, PH.D.
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` Ms. Zhong 8, 107, 222
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` Mr. Chandler 215
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` E X H I B I T S
`
`NO. DESCRIPTION PAGE
`
`Exhibit 1001 USP 7,619,912 (Bhakta, et al.,) 150
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`Exhibit 1003 Expert Declaration of Dr. Andrew 37
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` Wolfe
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`Exhibit 1005 Provisional Application for 107
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` Patent Cover Sheet, 60/588,244
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`Exhibit 1006 Provisional Application for 127
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` Patent Cover Sheet, 60/550,668
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`Exhibit 1007 Provisional Application for
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` Patent Cover Sheet, 60/575,595
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`Exhibit 1029 JEDEC Standard, DDR2 SDRAM 8
`
` Specification, JESD79-2
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`Exhibit 1030 JEDEC Standard, Double Data 8
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` Rate (DDR) SDRAM Specification,
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` JESD79
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`E X H I B I T S (continued)
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`NO. DESCRIPTION PAGE
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`Exhibit 1032 PC2100 and PC1600 DDR SDRAM 9
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` Registered DIMM Design
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` Specification, Revision 1.3,
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` January 2002
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`Exhibit 1033 Memory Systems - Cache, DRAM, 192
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` Disk
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`Exhibit 1034 Synchronous DRAM Architectures, 75
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` Organizations, and Alternative
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` Technologies by Prof. Bruce L.
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` Jacob, 12-10-02
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`Exhibit 1035 USP 7,363,422 (Perego, et al.) 24
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`Exhibit 1036 US Application Publication 171
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` No. 2006/0117152
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` (Amidi, et al.,)
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`Exhibit 1037 US Patent Application 155
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` Publication No. 2006/0277355
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`Exhibit 2100 MR16R1624(8/G)EG0 Change History 14
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` Data Sheet
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`Exhibit 2101 Provisional Application for 131
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` Patent Cover Sheet
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`Exhibit 2102 Screen Capture, Sheet 15 of 18 169
`
`///
`
`///
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`E X H I B I T S (continued)
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`Previously Marked Exhibits:
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`NO. DESCRIPTION PAGE
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`Exhibit 1009 USP 7,286,436 119
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` QUESTIONS INSTRUCTED NOT TO ANSWER
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` Page 222, Line 7
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` Page 222, Line 17
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` Page 222, Line 24
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` Wednesday, January 4, 2023
`
` 9:04 a.m.
`
` --o0o--
`
` ANDREW WOLFE, PH.D.
`
` being first duly sworn or affirmed to testify
`
` to the truth, the whole truth, and nothing but
`
` the truth, was examined and testified as follows:
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` EXAMINATION
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`BY MS. ZHONG: 09:04
`
` Q. Dr. Wolfe, can you pull up Exhibit 1032, 09:04
`
`Exhibit 1029, Exhibit 1030. You have them on your 09:05
`
`local computer and -- 09:05
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` THE REPORTER: I'm sorry, Ms. Zhong, I'm 09:05
`
`having a difficult time hearing you. 09:05
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`BY MS. ZHONG: 09:05
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` Q. Okay. Dr. Wolfe, can you pull up 09:05
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`Exhibits 1032, 1030 and 1029. 09:05
`
` (Exhibit 1029 was marked for 09:05
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` identification and attached 09:05
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` hereto.) 09:05
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` (Exhibit 1030 was marked for 09:05
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` identification and attached 09:05
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` hereto.) 09:05
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` (Exhibit 1032 was marked for 09:05
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` identification and attached 09:05
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` hereto.) 09:05
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` THE WITNESS: All three of them you want 09:05
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`me to pull up? 09:05
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`BY MS. ZHONG: 09:05
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` Q. Yes. You have them on your local 09:05
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`computer, correct? 09:05
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` A. I do. 09:05
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` Q. Okay. Let me know when you have them. 09:05
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` A. I have them. 09:05
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` Q. What is Exhibit 1032? 09:05
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` A. It is the PC2100 and PC1600, DDR SDRAM 09:05
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`Registered DIMM, D-I-M-M, Design Specification, 09:06
`
`Revision 1.3 from January 2002. And we often refer 09:06
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`to it as a version of JEDEC Standard 21-C. 09:06
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` Q. How does JEDEC Standard 21-C differ from 09:06
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`Exhibit 1030? 09:06
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` A. They are different documents describing 09:06
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`different things. 09:06
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` Q. What does Exhibit 1030 describe? 09:06
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` A. That is the JESD79 standard or 09:06
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`specification from June 2000. And it describes 09:06
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`various aspects of double-data-rate DRAM chips 09:06
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`primarily. 09:07
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` Q. Okay. So Exhibit 1030 is directed to the 09:07
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`SDRAM's memory device itself, correct? 09:07
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` A. Primarily, yes. 09:07
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` Q. Okay. And Exhibit 1032 describes the 09:07
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`memory module level, correct? 09:07
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` A. For one particular type of memory module, 09:07
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`that is correct. 09:07
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` Q. Okay. So Exhibit 1032 describes in 09:07
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`particular the registered DIMM memory module, 09:07
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`correct? 09:07
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` A. A particular type or a particular set of 09:07
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`types of registered DIMM memory modules. There's 09:07
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`other information in there as well, but that's its 09:07
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`primary purpose. 09:07
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` Q. Okay. And the operation of DDR SDRAM 09:08
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`device itself you refer to Exhibit 1030; is that 09:08
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`right? 09:08
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` A. Exhibit 1030 includes a multitude of 09:08
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`specific characteristic specifications for a 09:08
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`packaged double-data-rate SDRAM chip at that time. 09:08
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` Q. Okay. Why don't we go to Exhibit 1032, 09:08
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`page 16. 09:08
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` A. Okay. 09:08
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` Q. On page 16, lower left corner, do you see 09:08
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`a bunch of signals that's going into an element 09:08
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`called a register? Do you see that diagram there? 09:08
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` A. I do see that diagram. 09:08
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` Q. Okay. And what is a register shown on 09:09
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`page 16 of Exhibit 1032? 09:09
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` A. Well, what a register is always depends on 09:09
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`context. But in this particular context, that would 09:09
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`be a component on this module that can temporarily 09:09
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`store signal values. 09:09
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` So it would store the input values based 09:09
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`on certain values of the PCK, which stands for 09:09
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`clock, and PCK bar signals, and make those available 09:09
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`at the outputs on the right. 09:09
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` Q. Okay. So the signals on the left of the 09:09
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`register are input signals that -- (indiscernible.) 09:09
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` THE REPORTER: I'm sorry, Counsel. I'm 09:10
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`having a difficult time hearing you. One more time, 09:10
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`please. 09:10
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`BY MS. ZHONG: 09:10
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` Q. So the signals to the left of the element 09:10
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`of register are input signals received by the DIMM 09:10
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`from the computer system; is that correct? 09:10
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` A. In this diagram, the signals that are on 09:10
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`the left of the box marked "Register" would come 09:10
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`from -- they are input signals to the DIMM, and in 09:10
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`most cases they would come from a computer system. 09:10
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` Q. Okay. And the signals that's to the right 09:10
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`of the box labeled "Register," those are output 09:10
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`signals; is that correct? 09:10
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` A. From the perspective of this particular 09:10
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`register they are output signals. They would be 09:11
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`input signals to some other device. 09:11
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` Q. Okay. And so the signals to the right of 09:11
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`the register are output signals from the perspective 09:11
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`of the register and -- but they are input signals to 09:11
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`the SDRAM devices; is that correct? 09:11
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` A. They -- each of those would be an input 09:11
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`signal to one or more SDRAM devices. 09:11
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` Q. So the answer to my question is "yes"; is 09:11
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`that correct? 09:11
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` A. I don't know whether or not we're saying 09:11
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`the same thing. 09:11
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` The register will output each of the 09:11
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`signals shown to the right of the register. Those 09:11
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`are then provided -- but some are provided to some 09:11
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`SDRAM devices. Some are provided to others. Some 09:11
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`are provided to all of them. 09:11
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` Q. Okay. And there are different types of 09:11
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`DIMMs; is that correct?
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` A. In the world, that is true, there are 09:12
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`different type of DIMMs in the world. 09:12
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` Q. Okay. Are you familiar with a type of 09:12
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`DIMM called RIMM, which I believe is specific to the 09:12
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`Rambus-designed memory modules? 09:12
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` A. I don't recall it by that name, but there 09:12
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`were a number of Rambus memory modules in the 09:12
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`2000-2005 time frame typically. 09:12
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` Q. Okay. Do you recall what kind of input 09:12
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`signals do those RIMMs receive? 09:12
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` A. Not in detail. The RIMM -- the Rambus 09:12
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`DRAM memory modules used a packetized communication 09:13
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`scheme that used a narrower communication channel 09:13
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`than the most common other DIMMs at the time. 09:13
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` Q. Okay. So, for example, the Rambus memory 09:13
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`module -- let me rephrase that. 09:13
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` So the Rambus DRAM memory module do not 09:13
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`receive, for example, chip select signal, band 09:13
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`address signal, RAS bar, CAS bar, WE bar, and 09:13
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`address this as shown on page 16 of Exhibit 1032; is 09:13
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`that correct? 09:14
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` MR. CHANDLER: Objection. Form. 09:14
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` THE WITNESS: Again, I would need to look 09:14
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`at that specification to recall all the details. 09:14
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`It's been 20-plus years since I've read it. But my 09:14
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`recollection is that the same information was 09:14
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`conveyed but not in the exact same physical form. 09:14
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`BY MS. ZHONG: 09:14
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` Q. Okay. Let me see -- let me introduce a 09:14
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`document and see if this will jog your memory. 09:14
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` (Exhibit 2100 was marked for 09:15
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` identification and attached 09:15
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` hereto.) 09:15
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`BY MS. ZHONG: 09:15
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` Q. So, Dr. Wolfe, can you please refresh your 09:15
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`Exhibit Share link? 09:15
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` A. Yes. 09:15
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` Q. And do you see a newly marked 09:15
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`Exhibit 2001 -- 2100, EX2100? 09:15
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` A. EX2100. 09:15
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` Q. Yes. Can you please open it or download 09:15
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`it. 09:15
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` A. Okay. 09:15
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` Q. Exhibit 21 -- okay. Do you have it? 09:15
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` A. I do. 09:15
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` Q. So Exhibit 2100 is a Samsung data sheet 09:15
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`for RIMM, R-I-M-M, module based on 256 megabits or
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`288 megabits, 32 bank, 16K/32ms Rambus DRAMs.
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` Can you go to pages 2, 3, 4, and take a 09:16
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`look. 09:16
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` MR. CHANDLER: And, Annita, let me just 09:16
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`lodge an objection to the exhibit. It's -- appears 09:16
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`to be outside the scope of his declaration. Also 09:16
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`doesn't appear to be -- it doesn't appear to be 09:16
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`evidence that I can -- appears to be hearsay. 09:16
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`BY MS. ZHONG: 09:16
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` Q. Dr. Wolfe, can you please take a look at 09:16
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`pages 2 through 4. 09:16
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` A. I see them. 09:16
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` Q. Okay. The signals listed on pages 2 09:16
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`through 4, the input signals to the DIMM, for this 09:16
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`particular DIMM. 09:16
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` A. I'm sorry, I didn't understand the 09:17
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`question. 09:17
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` Q. So on page 2 through 4 there are a number 09:17
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`of pins listed on those pages, correct? 09:17
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` A. They are called pads in this case. But 09:17
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`there are a number of connections to a module that 09:17
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`are described on these pages. 09:17
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` Q. Okay. So the pads that's listed on those 09:17
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`pages are the -- how do you say? -- the input and 09:17
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`output pads for the -- for the memory module; is 09:17
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`that correct? 09:17
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` A. Some of them probably are. To get into 09:17
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`the details, I think, requires reviewing other 09:17
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`documents. 09:17
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` Q. Okay. Can you tell me which pin would be 09:17
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`check select signal coming in from? 09:18
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` A. Not from a cursory review of this document 09:18
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`I can't, no. There are other documents, the ones 09:18
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`intended to review together with this, that describe 09:18
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`how these signals are used in more detail. 09:18
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` Q. Okay. Do you see any reference to chip 09:18
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`select signal here in this document? 09:18
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` A. There may or may not be. Again, I 09:18
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`don't -- I don't know the definition of the 09:18
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`functionality of every pin from this document alone. 09:18
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` There are other documents that were 09:18
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`supplied at the time by Rambus that would describe 09:18
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`how each pin was used. And for this particular kind 09:18
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`of a DIMM, my recollection was that the DIMMs -- 09:18
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`that pins or pads had multiple functions. 09:18
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` Q. Okay. Are the signals -- you mentioned 09:19
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`that for Rambus memory module the address and the 09:19
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`control signals are packetized; is that correct? 09:19
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` THE REPORTER: I'm sorry, are what? I'm 09:19
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`sorry, Counsel, the last part of your question? 09:19
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`BY MS. ZHONG: 09:19
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` Q. You mentioned that the Rambus memory 09:19
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`module -- let me withdraw and reask. 09:19
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` So in the Rambus memory module, the 09:19
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`control and address information is packetized; is 09:19
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`that correct? 09:19
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` MR. CHANDLER: Objection. Form. 09:19
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` THE WITNESS: That was my recollection as 09:19
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`to certain Rambus memory modules that I was familiar 09:19
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`with in the early 2000s. I don't know, from what 09:19
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`I've seen here right now, whether or not this 09:20
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`particular module is consistent with the ones that I 09:20
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`previously studied. 09:20
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`BY MS. ZHONG: 09:20
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` Q. And how does a packetized control and 09:20
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`address information differ from the signaling 09:20
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`protocol that we see on page 16 of Exhibit 1032? 09:20
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` A. There are similarities and there are 09:20
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`differences, and it would depend on the specifics of 09:20
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`the specific situation. 09:20
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` But I think that the biggest difference is 09:20
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`that in the Rambus protocols that I was familiar 09:20
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`with at the time, there was -- there were more pins 09:20
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`that had multiple functions. 09:20
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` Q. So is there a discrete chip select signal 09:21
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`as in Exhibit 1032? 09:21
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` A. Does what have a discrete chip select 09:21
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`signal? 09:21
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` Q. Let me put it this way. When the control 09:21
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`and address information is set by the computer 09:21
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`system -- let me reask. 09:21
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` What do you mean by the control and 09:21
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`address information is packetized? 09:21
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` A. I'm not sure what you're referring to. 09:21
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` Q. Well, you said in the Rambus memory module 09:21
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`the control and address information is packetized, 09:21
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`correct? 09:22
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` A. I don't recall if that's exactly what I 09:22
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`said. But in the Rambus memory modules that I was 09:22
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`familiar with at one point in time, which again are 09:22
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`only a subset of the Rambus products, the control 09:22
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`and address -- as best as I can recall, I don't have 09:22
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`that protocol in front of me -- the control and 09:22
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`address data would be broken up into chunks, I 09:22
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`believe, 8 bits at a time, and sent as a sequence 09:22
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`over a limited number of wires and then 09:22
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`reconstituted on the module itself into individual 09:22
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`signals. 09:22
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` Q. Okay. So in the Rambus memory module that 09:22
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`you are familiar with from the early 2000s, the 09:22
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`control and address information is set in bits and 09:22
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`reconstituted by a larger component on the memory 09:23
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`module; is that correct? 09:23
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` MR. CHANDLER: Object to form. 09:23
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` THE WITNESS: Now, first understanding 09:23
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`clearly that this is -- that the module in 09:23
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`Exhibit 2100 is not one that I'm familiar with. 09:23
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` But my recollection is that, as I stated 09:23
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`before, that in the Rambus protocol for the devices 09:23
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`that I was familiar with, control and address 09:23
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`information would be sent along a relatively narrow 09:23
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`channel as a sequence of packets and then 09:23
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`reconstituted into individual signals by the logic 09:23
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`functions on the -- within the Rambus chips. 09:24
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`BY MS. ZHONG: 09:24
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` Q. Okay. 09:24
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` A. But again, I haven't seen those documents 09:24
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`in a long time, so I really can't tell you any of 09:24
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`the details about it without reviewing them again. 09:24
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` Q. When you say "reconstituted into 09:24
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`individual signals by the logic function within the 09:24
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`Rambus chips," what do you mean by "reconstituted"? 09:24
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` A. Again, it's been a long time since I 09:24
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`reviewed this protocol. But my best recollection is 09:24
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`that the individual selection signals to select 09:24
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`columns, rows, banks, and die would be reconstituted 09:25
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`within some logic somewhere on the memory module. 09:25
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` Q. So the form in which the logic function 09:25
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`receives the information from the memory system -- 09:25
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`let me withdraw it and reask. 09:25
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` So the input -- inputs that the logic 09:25
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`function receives from the computer system differs 09:25
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`from the output of that logic function; is that 09:25
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`correct? 09:25
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` MR. CHANDLER: Object to form. 09:25
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` THE WITNESS: I don't understand your 09:25
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`question. 09:25
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`BY MS. ZHONG: 09:25
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` Q. Which part don't you understand? 09:25
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` A. I don't understand what the question is. 09:25
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` Q. So the logic function on the Rambus DIMMs 09:26
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`that you are familiar with receives packetized 09:26
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`control and address information; is that correct? 09:26
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` A. In a very general sense. Again, I 09:26
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`haven't -- I haven't reviewed that protocol in 09:26
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`decades. 09:26
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` Q. Okay. And that logic function then 09:26
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`reconstitute those that receive the packetized 09:26
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`information and generates signals for output to the 09:26
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`DRAMs; is that correct? 09:26
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` MR. CHANDLER: Objection. Form. 09:26
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` THE WITNESS: Yeah, it depends how you're 09:26
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`defining some of those terms. I'm not sure what -- 09:26
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`what -- I mean I answered the question using 09:26
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`language I was comfortable with, but I don't know 09:26
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`how -- what -- how you're defining some of the words 09:26
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`in your question. 09:26
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`BY MS. ZHONG: 09:27
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` Q. Which words don't you understand? 09:27
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` A. Can you go through your question again? 09:27
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`In particular, I don't understand what you mean when 09:27
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`you say the signals go to the DRAM. 09:27
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` Q. And the logic function on the Rambus 09:27
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`memory module you're familiar with then 09:27
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`reconstitutes the control and address information 09:27
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`that it receives and it generates output signals; is 09:27
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`that correct? 09:27
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` A. It depends what you mean by output 09:27
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`signals. But in the very broadest sense where there 09:27
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`is at least some logic gate that outputs that 09:27
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`signal, that would be true based on my recollection 09:27
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`without reviewing the protocol. 09:27
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` Q. Okay. And the signals that are output by 09:27
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`the logic function, where do they go? 09:27
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` A. I don't remember. Again, I haven't seen 09:28
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`this design in decades. I'd have to see the actual 09:28
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`design to give you any more details. 09:28
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` Q. Do they go to the memory devices on the 09:28
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`module? 09:28
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` A. Like I said, I don't -- I don't recall. 09:28
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` Q. And is the -- and is the information 09:28
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`that's output by the logic function still 09:28
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`packetized? 09:28
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` MR. CHANDLER: Objection. Form. 09:28
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` THE WITNESS: Where and when? 09:28
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`BY MS. ZHONG: 09:28
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` Q. Pardon? 09:28
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` A. Where and when? 09:28
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` Q. You mention that the logic function would 09:28
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`take the packetized control and address information 09:29
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`it receives and reconstitute to generate the output 09:29
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`signal. So is that output signal still packetized? 09:29
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` MR. CHANDLER: Objection. Form. 09:29
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` THE WITNESS: Again, you know, at some 09:29
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`point the details become important and we have to 09:29
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`look at an actual circuit and look at an exact spot 09:29
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`in the circuit. 09:29
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` But eventually those -- that information 09:29
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`about control and addresses is not in the same 09:29
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`packetized form that it is transmitted over the 09:29
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`Rambus channel. But -- but, you know, it still -- 09:29
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`it's sequential. But at some point we would
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