240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`Features
`
`Preliminary‡
`
`DDR2 SDRAM FBDIMM
`MT18HTF12872FD – 1GB
`MT18HTF25672FD – 2GB
`
`For the latest data sheet, refer to Micron’s Web site: www.micron.com
`
`Figure 1:
`
`240-Pin FBDIMM (MO-256 R/C B)
`
`PCB height: 30.35mm (1.19in)
`
`Options
`(cid:129) Package
`– 240-pin FBDIMM (lead-free)
`(cid:129) Frequency/CL1
`– 3.75ns @ CL = 5 (DDR2-667)
`– 3.75ns @ CL = 4 (DDR2-533)
`(cid:129) PCB height
`– 30.35mm (1.19in)
`
`Notes: 1. CL = CAS (READ) latency.
`
`Marking
`
`Y
`
`-667
`-53E
`
`Features
`• 240-pin DDR2 fully buffered, dual in-line memory
`module (FBDIMM) with ECC to detect and report
`channel errors to the host memory controller
`(cid:129) Fast data transfer rates: PC2-4200 and PC2-5300
`using 533 MT/s and 667 MT/s DDR2 SDRAM
`components
`(cid:129) 3.2 Gb/s and 4.0 Gb/s link transfer rates
`(cid:129) High-speed, differential, point-to-point link
`between host memory controller and the AMB using
`serial, dual-simplex bit lanes
`– 10-pair southbound (data path to FBDIMM)
`– 14-pair northbound (data path from FBDIMM)
`(cid:129) Fault tolerant; can work around a bad bit lane in
`each direction
`(cid:129) High-density scaling with up to 8 dual-rank modules
`(288 DDR2 SDRAM devices) per channel
`(cid:129) SMBus interface to AMB for configuration register
`access
`(cid:129) In-band and out-of-band command access
`(cid:129) Deterministic protocol
`– Enables memory controller to optimize DRAM
`accesses for maximum performance
`– Delivers precise control and repeatable memory
`behavior
`(cid:129) Automatic DDR2 SDRAM bus and channel
`calibration
`(cid:129) Transmitter de-emphasis to reduce ISI
`(cid:129) MBIST and IBIST test functions
`(cid:129) Transparent mode for DDR2 SDRAM test support
`(cid:129) VDD = VDDQ = +1.8V for DDR2 SDRAM
`(cid:129) VREF = 0 .9V SDRAM C/A termination
`(cid:129) VCC = 1.5V for advanced memory buffer (AMB)
`(cid:129) VDDSPD = +1.7V to +3.6V for SPD EEPROM
`(cid:129) Serial presence-detect (SPD) with EEPROM
`(cid:129) Gold edge contacts
`(cid:129) Dual rank
`(cid:129) Supports 95°C operation with 2X refresh (tREFI =
`7.8µs at or below 85°C; tREFI = 3.9µs above 85°C)
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`1
`©2005 Micron Technology, Inc. All rights reserved.
`HTF18C128_256x72FD_1.fm - Rev. B 4/06 EN
`‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
`Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
`
`Netlist Ex 2048
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`
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`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`Features
`
`Preliminary
`
`Table 1:
`
`FBDIMM / DDR2 SDRAM Addressing
`
`Parameter
`Refresh count
`Device bank addressing
`Device page size per bank
`Device configuration
`Row addressing
`Column addressing
`Module rank addressing
`
`1GB
`8K
`4 (BA0, BA1)
`1KB
`512Mb (64 Meg x 8)
`16K (A0–A13)
`2K (A0–A9)
`2 (S0#, S1#)
`
`2GB
`8K
`8 (BA0, BA1, BA2)
`1KB
`1Gb (128 Meg x 8)
`16K (A0–A13)
`2K (A0–A9)
`2 (S0#, S1#)
`
`Table 2:
`
`Performance Parameters
`
`Speed Grade
`-667
`-53E
`
`Module Bandwidth
`PC2-5300
`PC2-4200
`
`Peak Channel
`Throughput
`8.0 GB/s
`6.4 GB/s
`
`Link Transfer Rate
`4.0 GT/s
`3.2 GT/s
`
`Latency
`(CL-tRCD-tRP)
`5-5-5
`4-4-4
`
`Table 3:
`
`Part Numbers and Label Markings
`
`Part Number1
`MT18HTF12872FDY-53E__
`MT18HTF12872FDY-667__
`MT18HTF25672FDY-53E__
`MT18HTF25672FDY-667__
`Notes:
`
`FBDIMM
`Label Key Attributes
`Configuration
`Module Density
`1GB 2Rx8 PC2-4200F-444-10-B_
`128 Meg x 72
`1GB
`1GB 2Rx8 PC2-5300F-555-10-B_
`128 Meg x 72
`1GB
`2GB 2Rx8 PC2-4200F-444-10-B_
`256 Meg x 72
`2GB
`2GB
`256 Meg x 72
`2GB 2Rx8 PC2-5300F-555-10-B_
`1. All part numbers end with a two-place code (not shown), designating component and PCB
`revisions. Consult factory for current revision codes. Example: MT18HTF12872FDY-53EC2.
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FD_1.fm - Rev. B 4/06 EN
`
`2
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`Table of Contents
`
`Preliminary
`
`Table of Contents
`Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
`Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
`List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
`List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
`FBDIMM Specification Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
`General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
`Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
`Advanced Memory Buffer (AMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
`AMB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
`High-Speed, Differential, Point-to-Point Link Interfaces (1.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
`DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
`SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
`Channel Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
`Peak Theoretical Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
`Hot-Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
`Hot-Remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
`Hot-Replace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
`FBDIMM Functional Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
`Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
`Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
`IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
`Assumptions for All Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
`Differential Transmitter and Receiver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
`AMB Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
`Serial Presence-Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`SPD Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`SPD Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`SPD Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`SPD Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FDTOC.fm - Rev. B 4/06 EN
`
`3
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`List of Figures
`
`Preliminary
`
`List of Figures
`Figure 1:
`240-Pin FBDIMM (MO-256 R/C B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
`Figure 2:
`FBDIMM System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
`Figure 3:
`AMB Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
`Figure 4:
`AMB Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
`Figure 5:
`FBDIMM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
`Figure 6:
`FBDIMM Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
`Figure 7:
`AMB Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
`Figure 9:
`Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
`Figure 10:
`Acknowledge Response from Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
`Figure 11:
`SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
`Figure 12:
`240-pin DDR2 FBDIMM Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FDLOF.fm - Rev. B 4/06 EN
`
`4
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`List of Tables
`
`Preliminary
`
`List of Tables
`Table 1:
`FBDIMM / DDR2 SDRAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
`Table 2:
`Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
`Table 3:
`Part Numbers and Label Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
`Table 4:
`240-pin FBDIMM Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
`Table 5:
`Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
`Table 6:
`Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
`Table 7:
`Input DC Voltage and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
`Table 8:
`Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
`DDR2 IDD Specifications and Conditions – 1GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
`Table 9:
`DDR2 IDD Specifications and Conditions – 2GB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
`Table 10:
`Table 11:
`Reference Clock Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
`VTT Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
`Table 12:
`Table 13:
`Differential Transmitter Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
`Table 14:
`Differential Receiver Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
`Table 15:
`EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
`Table 16:
`EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
`Table 17:
`Serial Presence-Detect EEPROM DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
`Table 18:
`Serial Presence-Detect EEPROM AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
`Table 19:
`MT18HTF12872FD Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
`Table 20:
`MT18HTF25672FD Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FDLOT.fm - Rev. B 4/06 EN
`
`5
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`Introduction
`
`Preliminary
`
`Introduction
`
`FBDIMM Specification Details
`
`The JEDEC FBDIMM specification consists of the following sections and can be found at
`the JEDEC Web site member’s area.
`
`
`Each of these sections contains detailed information about the various aspects of
`FBDIMM construction, interfaces, and theory of operation. The
`JEDEC specification is
`simply too long and complex to condense into a single data sheet; minimal references
`are made throughout this document to give a brief overview. For design guidance and
`final specification information, designers must refer to the JEDEC FBDIMM specifica-
`tion.
`1. FBDIMM Design Specification
`Defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300,
`72-bit wide, fully buffered double data rate synchronous DRAM dual in-line memory
`modules (DDR2 SDRAM FBDIMMs). These DDR2 SDRAM FBDIMMs are intended for
`use as main memory when installed in systems such as servers and workstations.
`PC2-4200/PC2-5300 refers to the DIMM naming convention in which PC2-4200/PC2-
`5300 indicates a 240-pin DDR2 DIMM running at 266/333 MHz DDR2 SDRAM clock
`speed and offering 4.2/5.3 GB/s bandwidth.
`
`Reference design examples are included which provide an initial basis for FBDIMM
`designs. Modifications to these reference designs may be required to meet all system
`timing, signal integrity, and thermal requirements for PC2-4200/PC2-5300/ support.
`All FBDIMM implementations must use simulations and lab verification to ensure
`proper timing requirements and signal integrity in the design.
`
`2. FBDIMM Architecture and Protocol Specification
`Describes FBDIMM channel topology, physical signaling, clocking, and data flow.
`
`3. FBDIMM AMB Specification
`Core specification for a FBDIMM memory system. This document, along with the
`other core specifications, must be treated as a whole. Information critical to an AMB
`design appears in the other specifications, with specific cross-references provided.
`
`4. FBDIMM Link Signaling Specification
`Defines the high-speed, differential, point-to-point signaling link for FBDIMM, oper-
`ating at AMB VCC = 1.5V, provided at the FBDIMM connector. This specification also
`applies to FBDIMM host chips which may operate with a different supply voltage. The
`link consists of a transmitter, a receiver, and the interconnect between them. The
`transmitter sends serialized bits into a lane and the receiver accepts the electrical sig-
`nals of the serialized bits and transforms them into a serialized bit-stream. The first-
`generation FBDIMM link is specified for 3.2–4.0 Gb/s and defined for three distinct
`bit rates: 3.2 Gb/s and 4.0 Gb/s.
`
`The link utilizes a derived-clock approach and transmitter de-emphasis to compen-
`sate for channel loss characteristics. The link definition has the flexibility to accom-
`modate future silicon enhancement circuits, such as forwarded clocking or advanced
`equalization techniques, to meet future signaling targets.
`
`5. FBDIMM DFx Specification
`Defines design for test, design for manufacturing, and design for validation (DFx)
`requirements and implementation guidelines for FBDIMM technology.
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FD_2.fm - Rev. B 4/06 EN
`
`6
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`General Description
`
`Preliminary
`
`6. FBDIMM SPD Specification
`This section describes the serial presence-detect (SPD) values for FBDIMMs, refer-
`enced in the SPD “Specific Features” standard document. The SPD fields indicated in
`this specification will occur in the order presented in section 1.1 of the JEDEC docu-
`ment. (Note that the descriptions of bytes 0 and 1 differ from those in previous SPD
`standards.) Further description of byte 2 is found in Appendix A of the JEDEC
`FBDIMM SPD standard. All unused entries will be coded as 0x00. All unused bits in
`defined bytes will be coded as 0, except where noted.
`
`General Description
`The Micron FBDIMM adheres to the currently proposed industry specifications for
`FBDIMMs. This data sheet represents a minimal subset of the FBDIMM and AMB speci-
`fication details and will be revised further as the specification matures and is approved
`and released. This document is to be used only as an introduction to the industry speci-
`fication, which will serve as the final reference for any an all design parameters and
`criteria.
`
`Micron’s FBDIMM is a high-bandwidth, large-capacity-channel solution that has a
`narrow host interface. FBDIMMs use DDR2 SDRAM devices isolated from the channel
`behind a buffer on the FBDIMM. Memory-device capacity remains high and total
`memory capacity scales with DDR2 SDRAM bit density.
`
`As shown in Figure 2 on page 8, the FBDIMM channel provides a communication path
`from a host controller to an array of DDR2 SDRAM devices, with the DDR2 SDRAM
`devices buffered behind an AMB device. The physical isolation of the DDR2 SDRAM
`devices from the channel enables the flexibility to enhance the communication path to
`significantly increase reliability and availability of the memory subsystem.
`
`Micron’s FBDIMM features a novel architecture, including the AMB that isolates the
`DDR2 SDRAM devices from the channel. This single-chip AMB component, located in
`the center of each FBDIMM, acts as a repeater and buffer for all signals and commands
`exchanged between the host controller and DDR2 SDRAM devices, including data input
`and output. The AMB communicates with the host controller and adjacent FBDIMMs
`on a system board using an industry-standard, high-speed, differential, point-to-point
`interface at 1.5V.
`
`The AMB also allows buffering of memory traffic to support large memory capacities. All
`memory control for the DDR2 SDRAM devices resides in the host, including memory
`request initiation, timing, refresh, scrubbing, sparing, configuration access, and power
`management. The AMB interface is responsible for handling channel and memory
`requests to and from the local FBDIMM and for forwarding requests to other FBDIMMs
`on the memory channel.
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FD_2.fm - Rev. B 4/06 EN
`
`7
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`General Description
`
`Preliminary
`
`Figure 2:
`
` FBDIMM System Block Diagram
`
`DDR2 connector with unique key
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`DDR2
`Component
`
`AMB
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`DDR2
`Component
`
`AMB
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`DDR2
`Component
`
`AMB
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`Commodity
`DDR2 SDRAM
`devices
`
`Up to 8 modules
`
`(cid:129) (cid:129) (cid:129)
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`DDR2
`Component
`
`AMB
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`DDR2
`Component
`
`Common clock source
`
`SMbus access
`to buffer registers
`
`10
`
`14
`
`SMBus
`
`Memory
`Controller
`
`CK
`Source
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FD_2.fm - Rev. B 4/06 EN
`
`8
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`Functional Description
`
`Preliminary
`
`Functional Description
`
`Advanced Memory Buffer (AMB)
`
`The AMB reference design complies with the JEDEC standard, “FBDIMM Architecture
`and Protocol Specification.” It is expected that there will be AMB multiple vendors,
`which will offer at least the minimum functionality set forth in the industry specifica-
`tion. To achieve optimal operation and compatibility with DDR2 SDRAM device and
`host/controller offerings, each vendor’s AMB will have a unique set of personality bytes
`contained in the SPD for setting up and fine tuning that device.
`
`The FBDIMM specification defines a number of options to support the requirements of
`different applications. The capabilities of the AMB are communicated to the host during
`the initialization process in the TS2 training pattern and in bits readable in the features
`register in the AMB.
`
`The AMB is responsible for handling FBDIMM channel and memory requests to and
`from the local FBDIMM and for forwarding requests to other FBDIMMs on the channel.
`A complete and detailed description of the AMB is contained in the proposed FBDIMM
`AMB Specification. The AMB is a memory interface that connects an array of DDR2
`SDRAM devices to the FBDIMM channel. The AMB is a slave device on the channel
`responding to channel commands and forwarding channel commands to other AMB
`devices.
`
`All memory control for the DDR2 SDRAM resides in the host, including memory request
`initiation, timing, refresh, scrubbing, sparing, configuration access, and power manage-
`ment.
`
`The AMB is expected to perform the following functions:
`
`(cid:129) Support channel initialization procedures as defined in the initialization chapter of
`the FBDIMM Architecture and Protocol Specification to align the clocks and the
`frame boundaries and verify channel connectivity
`(cid:129) Support the forwarding of southbound and northbound frames, servicing requests
`directed to a specific FBDIMM’s AMB, as defined in the protocol chapter of the speci-
`fication, and merging the return data into the northbound frames
`(cid:129) Initialize northbound frames if the FBDIMM’s AMB is the last, southern-most frame
`on the channel
`(cid:129) Detect errors on the channel and report them to the host memory controller
`(cid:129) Support the FBDIMM configuration register set as defined in the FBDIMM AMB spec-
`ification register chapter of the specification
`(cid:129) Act as a DRAM memory buffer for all read, write, and configuration accesses
`addressed to a specific FBDIMM’s AMB
`(cid:129) Provide a read and write buffer FIFO
`(cid:129) Support an SMBus protocol interface for access to the AMB configuration registers
`(cid:129) Provide features to support MEMBIST and IBIST test functions
`(cid:129) Provide a register interface for the thermal sensor and status indicator
`(cid:129) Function as a repeater to extend the maximum length of FBDIMM Links
`(cid:129) Reconfigure FBDIMM inputs from differential high-speed link receivers to two single-
`ended, low-speed receivers (~200 MHz). These inputs directly control DDR2
`command/address and input data that replicates to all DDR2 SDRAM devices.
`(cid:129) Bypass high speed parallel/serial circuitry and provide test results back to the tester,
`using low-speed FBDIMM outputs.
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FD_2.fm - Rev. B 4/06 EN
`
`9
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

`AMB Interface
`
` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`Functional Description
`
`Preliminary
`
`Figure 3 illustrates the AMB and all of its interfaces. They consist of two FBDIMM links,
`one DDR2 channel, and an SMBus interface. Each FBDIMM link connects the AMB to a
`host memory controller or an adjacent FBDIMM. The DDR2 channel supports direct
`connection to the DDR2 SDRAMs on an FBDIMM.
`
`The FBDIMM channel uses a daisy-chain topology to provide expansion from a single
`FBDIMM per channel to up to eight FBDIMMs per channel. The host sends data on the
`southbound link to the first FBDIMM, where it is received and redriven to the second
`FBDIMM. On the southbound data path, each FBDIMM receives the data and redrives
`the data to the next FBDIMM, until the last FBDIMM receives the data. The last
`FBDIMM in the chain initiates the transmission of northbound data in the direction of
`the host. On the northbound data path, each FBDIMM receives the data and redrives the
`data to the next FBDIMM until the host is reached.
`
`Figure 3:
`
` AMB Interface Block Diagram
`
`Primary or
`Host Direction
`
`Northbound
`FBD out link
`
`Southbound
`FBD in link
`
`Memory Interface
`
`DDR2
`Channel
`
`AMB
`
`Secondary direction or
`to (optional) next FBDIMM
`
`Northbound
`FBD out link
`
`Southbound
`FBD in link
`
`SMB
`
`High-Speed, Differential, Point-to-Point Link Interfaces (1.5V)
`The AMB supports one FBDIMM channel consisting of two bidirectional link interfaces
`using high-speed differential point-to-point electrical signaling. The southbound input
`link is 10 lanes wide. It carries commands and write data from the host memory
`controller, or the adjacent FBDIMM in the host direction, to the next FBDIMM in the
`chain.
`
`The northbound input link is 14 lanes wide. It carries read return data or status informa-
`tion from one FBDIMM to the next in the host direction and multiplexes in any inter-
`nally generated READ return data or status information.
`
`Data and commands sent to the DDR2 SDRAM devices travel southbound on 10 primary
`differential signal line pairs. Data and status information received from the DDR2
`SDRAM devices travel northbound on 14 primary differential pairs. Data and commands
`sent to the upstream adjacent FBDIMM are repeated and travel further southbound on
`10 secondary differential pairs. Data and status information received from the upstream
`adjacent FBDIMM travel further northbound on 14 secondary differential pairs.
`
`PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b
`HTF18C128_256x72FD_2.fm - Rev. B 4/06 EN
`
`10
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2005 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2048
`Samsung v Netlist
`IPR2022-00996
`
`

`

`DDR2 Channel
`
` 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72)
`Functional Description
`
`Preliminary
`
`The AMB DDR2 channel supports direct connection to DDR2 SDRAM devices. The
`DDR2 channel supports two ranks of eight banks with 16 row/column-request, 64 data,
`and eight check-bit signals. There are two copies of address and command signals to
`support FBDIMM routing and electrical requirements. Four transfer bursts are driven on
`the data and check-bit lines at 800 MHz.
`
`Propagation delays can differ between read data/check-bit strobe lanes on a given
`channel. Each strobe can be calibrated by hardware-state machines using WRITE/READ
`trial and error. Hardware aligns the read data and check-bits to a single core clock. The
`AMB provides four copies of the command clock phase references (CK[3:0]) and write
`data/check-bit strobes (DQS) for each DDR2 SDRAM device nibble.
`
`SMBus Slave Interface
`AMB support for an SMBus interface allows system access to configuration registers
`independent of the FBDIMM link. The AMB will never be a master on the SMBus, only a
`slave. Serial SMBus data transfer is supported at 100 KHz. SMBus access to the AMB may
`be a requirement to boot and to set link strength, frequency, and other parameters
`needed to ensure robust configurations. It is also required for diagnostic support when
`the high-speed link is down. The SMBus address straps located on the FBDIMM
`connector are used to set the unique ID.
`
`Channel Latency
`
`FBDIMM channel latency is measured from the time a read request is driven on the
`FBDIMM channel pins to the time when the first 16 bytes (second chunk) of read
`completion data is sampled by the memory controller.
`
`When not using variable READ latency, the latency for a specific FBDIMM on a channel
`is always equal to the latency for any other FBDIMM on that channel. However, the
`latency for each FBDIMM in a specific configuration with some number of FBDIMMs
`installed may not be equal to the latency for each FBDIMM in a configuration with some
`different number of FBDIMMs installed. As more FBDIMMs are added to the channel,
`additional latency is required to read from each FBDIMM on the channel.
`
`Because the channel is based on point-to-point interconnection of buffer components
`between FBDIMMs, memory requests are required to travel through N - 1 buffers before
`reaching the Nth buffer. The result is that a four-FBDIMM channel configuration will
`have greater idle READ latency than a one-FBDIMM channel configuration.
`
`The variable READ latency capability can be used to reduce latency for FBDIMMs closer
`to the host. The idle latencies listed in this section are representative of what might be
`achieved in typical AMB designs. Actual implementations with latencies less than the
`values listed w