`Features
`
`DDR2 SDRAM SODIMM
`MT16HTF12864HZ – 1GB
`MT16HTF25664HZ – 2GB
`MT16HTF51264HZ – 4GB
`
`Features
`• 200-pin, small-outline dual in-line memory module
`(SODIMM)
`• Fast data transfer rates: PC2-3200, PC2-4200,
`PC2-5300, or PC2-6400
`• 1GB (128 Meg x 64), 2GB (256 Meg x 64) or 4GB (512
`Meg x 64)
`• VDD = VDDQ = 1.8V
`• VDDSPD = 1.7–3.6V
`• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
`• Differential data strobe (DQS, DQS#) option
`• 4n-bit prefetch architecture
`• Multiple internal device banks for concurrent
`operation
`• Programmable CAS latency (CL)
`• Posted CAS additive latency (AL)
`• WRITE latency = READ latency - 1 tCK
`• Programmable burst lengths (BL): 4 or 8
`• Adjustable data-output drive strength
`• 64ms, 8192-cycle refresh
`• On-die termination (ODT)
`• Halogen-free
`• Serial presence detect (SPD) with EEPROM
`• Gold edge contacts
`• Dual rank
`
`Table 1: Key Timing Parameters
`
`Figure 1: 200-Pin SODIMM (MO-224 R/C E)
`
`Module Height: 30mm (1.181 in.)
`
`Options
`• Operating temperature
`– Commercial (0°C ≤ TA ≤ +70°C)
`– Industrial (–40°C ≤ TA ≤ +85°C)1
`• Package
`– 200-pin DIMM (halogen-free)
`• Frequency/CL2
`– 1.87ns @ CL = 7 (DDR2-1066)
`– 2.5ns @ CL = 5 (DDR2-800)
`– 2.5ns @ CL = 6 (DDR2-800)
`– 3ns @ CL = 5 (DDR2-667)
`
`Marking
`
`None
`I
`
`Z
`
`-1GA
`-80E
`-800
`-667
`
`Notes:
`
`1. Contact Micron for industrial temperature
`module offerings.
`2. CL = CAS (READ) latency.
`3. Not recommended for new designs.
`
`Speed
`Grade
`-1GA
`-80E
`-800
`-667
`-53E
`-40E
`
`Industry
`Nomenclature
`PC2-8500
`PC2-6400
`PC2-6400
`PC2-5300
`PC2-4200
`PC2-3200
`
`CL = 7
`1066
`
`Data Rate (MT/s)
`CL = 6
`CL = 5
`CL = 4
`800
`667
`533
`800
`800
`533
`800
`667
`533
`–
`667
`553
`–
`–
`553
`–
`–
`400
`
`CL = 3
`400
`400
`400
`400
`400
`400
`
`tRCD
`(ns)
`13.125
`12.5
`15
`15
`15
`15
`
`tRP
`(ns)
`13.125
`12.5
`15
`15
`15
`15
`
`tRC
`(ns)
`58.125
`57.5
`60
`60
`55
`55
`
`1
`PDF: 09005aef8339ef97
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`Products and specifications discussed herein are subject to change by Micron without notice.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Features
`
`Table 2: Addressing
`
`Parameter
`Refresh count
`Row address
`Device bank address
`Device configuration
`Column address
`Module rank address
`
`1GB
`8K
`16K A[13:0]
`4 BA[1:0]
`512Mb (64 Meg x 8)
`1K A[9:0]
`2 S#[1:0]
`
`2GB
`8K
`16K A[13:0]
`8 BA[2:0]
`1Gb (128 Meg x 8)
`1K A[9:0]
`2 S#[1:0]
`
`4GB
`8K
`32K A[14:0]
`8 BA[2:0]
`2Gb (256 Meg x 8)
`1K A[9:0]
`2 S#[1:0]
`
`Table 3: Part Numbers and Timing Parameters – 1GB Modules
`
`Base device: MT47H64M8,1 512Mb DDR2 SDRAM
`Module
`Density
`1GB
`1GB
`1GB
`
`Part Number2
`MT16HTF12864H(I)Z-80E__
`MT16HTF12864H(I)Z-800__
`MT16HTF12864H(I)Z-667__
`
`Configuration
`128 Meg x 64
`128 Meg x 64
`128 Meg x 64
`
`Module
`Bandwidth
`6.4 GB/s
`6.4 GB/s
`5.3 GB/s
`
`Memory Clock/
`Data Rate
`2.5ns/800 MT/s
`2.5ns/800 MT/s
`3.0ns/667 MT/s
`
`Clock Cycles
`(CL-tRCD-tRP)
`5-5-5
`6-6-6
`5-5-5
`
`Table 4: Part Numbers and Timing Parameters – 2GB Modules
`
`Base device: MT47H128M8,1 1Gb DDR2 SDRAM
`Module
`Density
`2GB
`2GB
`2GB
`2GB
`
`Part Number2
`MT16HTF25664H(I)Z-1GA__
`MT16HTF25664H(I)Z-80E__
`MT16HTF25664H(I)Z-800__
`MT16HTF25664H(I)Z-667__
`
`Configuration
`256 Meg x 64
`256 Meg x 64
`256 Meg x 64
`256 Meg x 64
`
`Module
`Bandwidth
`8.5 GB/s
`6.4 GB/s
`6.4 GB/s
`5.3 GB/s
`
`Memory Clock/
`Data Rate
`1.87ns/1066 MT/s
`2.5ns/800 MT/s
`2.5ns/800 MT/s
`3.0ns/667 MT/s
`
`Clock Cycles
`(CL-tRCD-tRP)
`7-7-7
`5-5-5
`6-6-6
`5-5-5
`
`Table 5: Part Numbers and Timing Parameters – 2GB Modules
`
`Base device: MT47H256M8,1 2Gb DDR2 SDRAM
`Module
`Density
`4GB
`4GB
`4GB
`4GB
`
`Part Number2
`MT16HTF51264H(I)Z-1GA__
`MT16HTF51264H(I)Z-80E__
`MT16HTF51264H(I)Z-800__
`MT16HTF51264H(I)Z-667__
`
`Configuration
`512 Meg x 64
`512 Meg x 64
`512Meg x 64
`512 Meg x 64
`
`Module
`Bandwidth
`8.5 GB/s
`6.4 GB/s
`6.4 GB/s
`5.3 GB/s
`
`Memory Clock/
`Data Rate
`1.87ns/1066 MT/s
`2.5ns/800 MT/s
`2.5ns/800 MT/s
`3.0ns/667 MT/s
`
`Clock Cycles
`(CL-tRCD-tRP)
`7-7-7
`5-5-5
`6-6-6
`5-5-5
`
`Notes:
`
`1. The data sheet for the base device can be found on Micron’s Web site.
`2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
`Consult factory for current revision codes. Example: MT16HTF25664HZ-80EM1.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`2
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Pin Assignments
`
`Pin Assignments
`
`Table 6: Pin Assignments
`
`200-Pin DDR2 SODIMM Front
`Pin Symbol Pin Symbol Pin Symbol Pin Symbol
`1
`51
`DQS2
`101
`A1
`151
`DQ42
`VREF
`3
`VSS
`53
`VSS
`103
`VDD
`153
`DQ43
`5
`DQ0
`55
`DQ18
`105
`A10
`155
`VSS
`7
`DQ1
`57
`DQ19
`107
`BA0
`157
`DQ48
`9
`VSS
`59
`VSS
`109
`WE#
`159
`DQ49
`11
`DQS0#
`61
`DQ24
`111
`VDD
`161
`VSS
`13
`DQS0
`63
`DQ25
`113
`CAS#
`163
`NC
`15
`VSS
`65
`VSS
`115
`S1#
`165
`VSS
`17
`DQ2
`67
`DM3
`117
`VDD
`167
`DQS6#
`19
`DQ3
`69
`NC
`119
`ODT1
`169
`DQS6
`21
`VSS
`71
`VSS
`121
`VSS
`171
`VSS
`23
`DQ8
`73
`DQ26
`123
`DQ32
`173
`DQ50
`25
`DQ9
`75
`DQ27
`125
`DQ33
`175
`DQ51
`27
`VSS
`77
`VSS
`127
`VSS
`177
`VSS
`29
`DQS1#
`79
`CKE0
`129
`DQS4#
`179
`DQ56
`31
`DQS1
`81
`VDD
`131
`DQS4
`181
`DQ57
`33
`VSS
`83
`NC
`133
`VSS
`183
`VSS
`NC/BA21
`35
`DQ10
`85
`135
`DQ34
`185
`DM7
`37
`DQ11
`VDD
`VDD
`137
`DQ35
`187
`VSS
`39
`VSS
`89
`A12
`139
`VSS
`189
`DQ58
`41
`VSS
`91
`A9
`141
`DQ40
`191
`DQ59
`43
`DQ16
`93
`A8
`143
`DQ41
`193
`VSS
`45
`DQ17
`95
`VDD
`145
`VSS
`195
`SDA
`47
`VSS
`97
`A5
`147
`DM5
`197
`SCL
`49
`DQS2#
`99
`A3
`149
`VSS
`199
`VDDSPD
`
`200-Pin DDR2 SODIMM Back
`Pin Symbol Pin Symbol Pin Symbol Pin Symbol
`2
`52
`DM2
`102
`A0
`152
`DQ46
`VSS
`4
`DQ4
`54
`VSS
`104
`VDD
`154
`DQ47
`6
`DQ5
`56
`DQ22
`106
`BA1
`156
`VSS
`8
`VSS
`58
`DQ23
`108
`RAS#
`158
`DQ52
`10
`DM0
`60
`VSS
`110
`S0#
`160
`DQ53
`12
`VSS
`62
`DQ28
`112
`VDD
`162
`VSS
`14
`DQ6
`64
`DQ29
`114
`ODT0
`164
`CK1
`16
`DQ7
`66
`VSS
`116
`A13
`166
`CK1#
`18
`VSS
`68
`DQS3#
`118
`VDD
`168
`VSS
`20
`DQ12
`70
`DQS3
`120
`NC
`170
`DM6
`22
`DQ13
`72
`VSS
`122
`VSS
`172
`VSS
`24
`VSS
`74
`DQ30
`124
`DQ36
`174
`DQ54
`26
`DM1
`76
`DQ31
`126
`DQ37
`176
`DQ55
`28
`VSS
`78
`VSS
`128
`VSS
`178
`VSS
`30
`CK0
`80
`CKE1
`130
`DM4
`180
`DQ60
`32
`CK0#
`82
`VDD
`132
`VSS
`182
`DQ61
`34
`VSS
`84
`NC
`134
`DQ38
`184
`VSS
`NC/A142
`36
`DQ14
`86
`136
`DQ39
`186
`DQS7#
`38
`DQ15
`88
`VDD
`138
`VSS
`188
`DQS7
`40
`VSS
`90
`A11
`140
`DQ44
`190
`VSS
`42
`VSS
`92
`A7
`142
`DQ45
`192
`DQ62
`44
`DQ20
`94
`A6
`144
`VSS
`194
`DQ63
`46
`DQ21
`96
`VDD
`146
`DQS5#
`196
`VSS
`48
`VSS
`98
`A4
`148
`DQS5
`198
`SA0
`50
`NC
`100
`A2
`150
`VSS
`200
`SA1
`
`Notes:
`
`1. Pin 85 is NC for 1GB and BA2 for 2GB, 4GB.
`2. Pin 86 is NC for 1GB, 2GB and A14 for 4GB.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`3
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Pin Descriptions
`
`Pin Descriptions
`
`The pin description table below is a comprehensive list of all possible pins for all DDR2
`modules. All pins listed may not be supported on this module. See Pin Assignments for
`information specific to this module.
`
`Table 7: Pin Descriptions
`
`Symbol
`Ax
`
`Type
`Input
`
`BAx
`
`Input
`
`CKx,
`CK#x
`CKEx
`
`DMx
`
`Input
`
`Input
`
`Input
`
`ODTx
`
`Input
`
`Par_In
`RAS#, CAS#, WE#
`
`RESET#
`
`S#x
`
`SAx
`
`SCL
`
`CBx
`DQx
`DQSx,
`DQS#x
`
`Input
`Input
`
`Input
`
`Input
`
`Input
`
`Input
`
`I/O
`I/O
`I/O
`
`Description
`Address inputs: Provide the row address for ACTIVE commands, and the column ad-
`dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
`out of the memory array in the respective bank. A10 sampled during a PRECHARGE
`command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
`selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
`during a LOAD MODE command. See the Pin Assignments Table for density-specific
`addressing information.
`Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
`PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
`MR2, and MR3) is loaded during the LOAD MODE command.
`Clock: Differential clock inputs. All control, command, and address input signals are
`sampled on the crossing of the positive edge of CK and the negative edge of CK#.
`Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
`try and clocks on the DDR2 SDRAM.
`Data mask (x8 devices only): DM is an input mask signal for write data. Input data
`is masked when DM is sampled HIGH, along with that input data, during a write ac-
`cess. Although DM pins are input-only, DM loading is designed to match that of the
`DQ and DQS pins.
`On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
`nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
`ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
`will be ignored if disabled via the LOAD MODE command.
`Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
`Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
`entered.
`Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
`signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
`Chip select: Enables (registered LOW) and disables (registered HIGH) the command
`decoder.
`Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
`bus.
`Serial clock for SPD EEPROM: Used to synchronize communication to and from the
`SPD EEPROM on the I2C bus.
`Check bits. Used for system error detection and correction.
`Data input/output: Bidirectional data bus.
`Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
`troller. Output with read data; input with write data for source synchronous opera-
`tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
`MODE command.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`4
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Pin Descriptions
`
`Table 7: Pin Descriptions (Continued)
`
`Symbol
`SDA
`
`RDQSx,
`RDQS#x
`
`Type
`I/O
`
`Output
`
`Err_Out#
`
`VDD/VDDQ
`
`Output
`(open drain)
`Supply
`
`VDDSPD
`VREF
`VSS
`NC
`NF
`
`NU
`RFU
`
`Supply
`Supply
`Supply
`–
`–
`
`–
`–
`
`Description
`Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
`the I2C bus.
`Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
`MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
`is output with read data only and is ignored during write data. When RDQS is disa-
`bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
`and differential data strobe mode is enabled.
`Parity error output: Parity error found on the command and address bus.
`
`Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
`ule VDD.
`SPD EEPROM power supply: 1.7–3.6V.
`Reference voltage: VDD/2.
`Ground.
`No connect: These pins are not connected on the module.
`No function: These pins are connected within the module, but provide no functional-
`ity.
`Not used: These pins are not used in specific module configurations/operations.
`Reserved for future use.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`5
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Functional Block Diagram – 1GB, 2GB
`
`Functional Block Diagram – 1GB, 2GB
`
`Figure 2: Functional Block Diagram – 1GB, 2GB
`
`
`
`S1#
`S0#
`
`DQS0#
`DQS0
`DM0
`
`DQS4#
`DQS4
`DM4
`
`DM CS# DQ DQS#
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U1
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U14
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U4
`
`U11
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DQS1#
`DQS1
`DM1
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQS2#
`DQS2
`DM2
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQS3#
`DQS3
`DM3
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`BA[2/1:0]
`A[13:0]
`RAS#
`CAS#
`WE#
`CKE0
`CKE1
`ODT0
`ODT1
`
`DQS5#
`DQS5
`DM5
`
`DM CS# DQ DQS#
`
`U6
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U18
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U8
`
`U16
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DQS6#
`DQS6
`DM6
`
`DM CS# DQ DQS#
`
`U2
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U13
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U5
`
`U10
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DM CS# DQ DQS#
`
`U7
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U17
`
`DQS7#
`DQS7
`DM7
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`SDA
`
`U9
`
`U15
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`Rank 0 = U1, U2, U4–U9
`Rank 1 = U10, U11, U13–U18
`
`BA[2/1:0]: DDR2 SDRAM
`A[13:0]: DDR2 SDRAM
`RAS#: DDR2 SDRAM
`CAS#: DDR2 SDRAM
`WE#: DDR2 SDRAM
`CKE0: Rank 0
`CKE1: Rank 1
`ODT0: Rank 0
`ODT1: Rank 1
`
`U3
`SPD/EEPROM
`A0
`A1 A2
`WP
`
`SCL
`
`VSS
`
`SA0 SA1
`
`VSS
`SPD/EEPROM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM, EEPROM
`
`CK0
`CK0#
`
`CK1
`CK1#
`
`VDDSPD
`VDD
`VREF
`VSS
`
`U1, U2, U6, U7
`U13, U14, U17, U18
`
`U4, U5, U8, U9
`U10, U11, U15, U16
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`6
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Functional Block Diagram – 4GB
`
`Functional Block Diagram – 4GB
`
`Figure 3: Functional Block Diagram – 4GB
`
`
`
`S1#
`S0#
`
`DQS0#
`DQS0
`DM0
`
`DQS4#
`DQS4
`DM4
`
`DM CS# DQ DQS#
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U1
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U14
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U5
`
`U12
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DQS1#
`DQS1
`DM1
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQS2#
`DQS2
`DM2
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQS3#
`DQS3
`DM3
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`BA[2:0]
`A[14:0]
`RAS#
`CAS#
`WE#
`CKE0
`CKE1
`ODT0
`ODT1
`
`DQS5#
`DQS5
`DM5
`
`DM CS# DQ DQS#
`
`U7
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U18
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U9
`
`U16
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DQS6#
`DQS6
`DM6
`
`DM CS# DQ DQS#
`
`U2
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U13
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U6
`
`U11
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DQS7#
`DQS7
`DM7
`
`DM CS# DQ DQS#
`
`U8
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`DM CS# DQ DQS#
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U17
`
`DM CS# DQ DQS#
`
`DM CS# DQ DQS#
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`U10
`
`U15
`
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`DQ
`
`BA[2:0]: DDR2 SDRAM
`A[14:0]: DDR2 SDRAM
`RAS#: DDR2 SDRAM
`CAS#: DDR2 SDRAM
`WE#: DDR2 SDRAM
`CKE0: Rank 0
`CKE1: Rank 1
`ODT0: Rank 0
`ODT1: Rank 1
`
`U4
`SPD/EEPROM
`A1 A2
`A0
`WP
`
`SCL
`
`SDA
`
`Rank 0 = U1, U2, U5–U10
`Rank 1 = U11–U18
`
`VSS
`
`SA0 SA1
`
`VSS
`SPD/EEPROM
`DDR2 SDRAM
`DDR2 SDRAM
`DDR2 SDRAM, EEPROM
`
`CK0
`CK0#
`
`CK1
`CK1#
`
`VDDSPD
`VDD
`VREF
`VSS
`
`U1, U2, U7, U8
`U13, U14, U17, U18
`
`U5, U6, U9, U10
`U11, U12, U15, U16
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`7
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`General Description
`
`General Description
`DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
`ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
`modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
`essentially a 4n-prefetch architecture with an interface designed to transfer two data
`words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
`module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
`internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data
`transfers at the I/O pins.
`
`DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
`and CK# to capture commands, addresses, and control signals. Differential clocks and
`data strobes ensure exceptional noise immunity for these signals and provide precise
`crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is
`transmitted externally, along with data, for use in data capture at the receiver. DQS is a
`strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
`troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
`with data for WRITEs.
`
`DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
`CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
`mands (address and control signals) are registered at every positive edge of CK. Input
`data is registered on both edges of DQS, and output data is referenced to both edges of
`DQS, as well as to both edges of CK.
`
`Serial Presence-Detect EEPROM Operation
`DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
`256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
`ule type and various SDRAM organizations and timing parameters. The remaining 128
`bytes of storage are available for use by the customer. System READ/WRITE operations
`between the master (system logic) and the slave EEPROM device occur via a standard
`I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
`(WP) is connected to VSS, permanently disabling hardware write protection.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`8
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`Electrical Specifications
`
`Electrical Specifications
`Stresses greater than those listed may cause permanent damage to the module. This is a
`stress rating only, and functional operation of the module at these or any other condi-
`tions outside those indicated in the device data sheet are not implied. Exposure to abso-
`lute maximum rating conditions for extended periods may adversely affect reliability.
`
`Table 8: Absolute Maximum Ratings
`
`Symbol
`VDD
`VIN, VOUT
`II
`
`Parameter
`VDD supply voltage relative to VSS
`Voltage on any pin relative to VSS
`Input leakage current; Any input 0V ≤ VIN ≤
`VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other
`pins not under test = 0V)
`
`IOZ
`
`IVREF
`TA
`
`1
`TC
`
`Output leakage current; 0V ≤ VOUT; DQ and
`ODT are disabled
`VREF leakage current; VREF = valid VREF level
`Module ambient operating temperature
`
`DDR2 SDRAM component operating tem-
`perature2
`
`Address inputs, RAS#, CAS#,
`WE#, BA
`S#, CKE, ODT, CK, CK#
`DM
`DQ, DQS, DQS#
`
`Commercial
`Industrial
`Commercial
`Industrial
`
`Min
`–1.0
`–0.5
`–80
`
`–40
`–10
`–10
`
`–32
`0
`–40
`0
`–40
`
`Max
`2.3
`2.3
`80
`
`Units
`V
`V
`µA
`
`40
`10
`10
`
`32
`70
`85
`85
`95
`
`µA
`
`µA
`°C
`°C
`°C
`°C
`
`Notes:
`
`1. The refresh rate is required to double when TC exceeds 85°C.
`2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
`able on Micron’s Web site.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`9
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`DRAM Operating Conditions
`
`DRAM Operating Conditions
`Recommended AC operating conditions are given in the DDR2 component data sheets.
`Component specifications are available on Micron's Web site. Module speed grades cor-
`relate with component speed grades.
`
`Table 9: Module and Component Speed Grades
`
`DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
`Module Speed Grade
`Component Speed Grade
`-1GA
`-187E
`-80E
`-25E
`-800
`-25
`-667
`-3
`-53E
`-37E
`-40E
`-5E
`
`Design Considerations
`Simulations
`
`Micron memory modules are designed to optimize signal integrity through carefully de-
`signed terminations, controlled board impedances, routing topologies, trace length
`matching, and decoupling. However, good signal integrity starts at the system level. Mi-
`cron encourages designers to simulate the signal characteristics of the system's memo-
`ry bus to ensure adequate signal integrity of the entire memory system.
`
`Power
`
`Operating voltages are specified at the DRAM, not at the edge connector of the module.
`Designers must account for any system voltage drops at anticipated power levels to en-
`sure the required supply voltage is maintained.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`10
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`IDD Specifications
`
`IDD Specifications
`
`Table 10: DDR2 IDD Specifications and Conditions – 1GB (Die Revision G)
`
`Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) com-
`ponent data sheet
`
`Parameter
`Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS =
`tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
`switching; Data bus inputs are switching
`Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL
`(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE
`is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
`pattern is same as IDD4W
`Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW;
`Other control and address bus inputs are stable; Data bus inputs are floating
`Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH,
`S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating
`Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is
`HIGH; Other control and address bus inputs are switching; Data bus inputs are switching
`Active power-down current: All device banks open; tCK
`Fast PDN exit MR[12] = 0
`= tCK (IDD); CKE is LOW; Other control and address bus in-
`Slow PDN exit MR[12] = 1
`puts are stable; Data bus inputs are floating
`Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
`tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
`dress bus inputs are switching; Data bus inputs are switching
`Operating burst write current: All device banks open; Continuous burst writes; BL =
`4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
`HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus
`inputs are switching
`Operating burst read current: All device banks open; Continuous burst read, IOUT =
`0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
`CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Da-
`ta bus inputs are switching
`Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval;
`CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs
`are switching; Data bus inputs are switching
`Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus in-
`puts are floating; Data bus inputs are floating
`Operating bank interleave read current: All device banks interleaving reads; IOUT =
`0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
`tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
`Address bus inputs are stable during deselects; Data bus inputs are switching
`
`Symbol
`1
`IDD0
`
`-80E/
`-800
`576
`
`-667 Units
`536
`mA
`
`1
`
`IDD1
`
`656
`
`616
`
`mA
`
`IDD2P
`
`2
`
`2
`IDD2Q
`
`2
`IDD2N
`
`IDD3P
`
`2
`
`112
`
`112
`
`mA
`
`384
`
`352
`
`mA
`
`448
`
`400
`
`mA
`
`288
`144
`
`240
`144
`
`mA
`
`2
`IDD3N
`
`528
`
`480
`
`mA
`
`IDD4W
`
`1
`
`1056
`
`976
`
`mA
`
`1
`IDD4R
`
`1016
`
`936
`
`mA
`
`2
`
`IDD5
`
`816
`
`776
`
`mA
`
`2
`
`IDD6
`
`1
`
`IDD7
`
`112
`
`112
`
`mA
`
`1256
`
`1176 mA
`
`Notes:
`
`1. Value calculated as one module rank in this operating condition; all other module ranks
`in IDD2P (CKE LOW) mode.
`2. Value calculated reflects all module ranks in this operating condition.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`11
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`IDD Specifications
`
`Table 11: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H)
`
`Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
`ponent data sheet
`
`Parameter
`Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD),
`tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
`bus inputs are switching; Data bus inputs are switching
`Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL =
`CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
`(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
`switching; Data pattern is same as IDD4W
`Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
`LOW; Other control and address bus inputs are stable; Data bus inputs are float-
`ing
`Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is
`HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
`are floating
`Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH,
`S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
`are switching
`Active power-down current: All device banks open;
`tCK = tCK (IDD); CKE is LOW; Other control and address
`bus inputs are stable; Data bus inputs are floating
`Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
`MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Oth-
`er control and address bus inputs are switching; Data bus inputs are switching
`Operating burst write current: All device banks open; Continuous burst writes;
`BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
`CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
`ing; Data bus inputs are switching
`Operating burst read current: All device banks open; Continuous burst read,
`IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
`tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
`puts are switching; Data bus inputs are switching
`Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) in-
`terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
`dress bus inputs are switching; Data bus inputs are switching
`Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
`bus inputs are floating; Data bus inputs are floating
`Operating bank interleave read current: All device banks interleaving reads;
`IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC
`= tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between
`valid commands; Address bus inputs are stable during deselects; Data bus inputs
`are switching
`
`Fast PDN exit MR[12] = 0
`Slow PDN exit MR[12] = 1
`
`Symbol
`1
`IDD0
`
`-1GA
`656
`
`-80E/
`-800 -667 Units
`576
`536 mA
`
`1
`
`IDD1
`
`736
`
`656
`
`616 mA
`
`IDD2P
`
`2
`
`112
`
`112
`
`112 mA
`
`2
`IDD2Q
`
`448
`
`384
`
`384 mA
`
`2
`IDD2N
`
`544
`
`448
`
`384 mA
`
`IDD3P
`
`2
`
`368
`160
`
`320
`160
`
`240 mA
`160
`
`2
`IDD3N
`
`640
`
`528
`
`480 mA
`
`IDD4W
`
`1
`
`1216
`
`1056
`
`976 mA
`
`1
`IDD4R
`
`1176
`
`1016
`
`936 mA
`
`2
`
`IDD5
`
`1296
`
`1216 1176 mA
`
`2
`
`IDD6
`
`1
`
`IDD7
`
`112
`
`112
`
`112 mA
`
`1816
`
`1736 1536 mA
`
`Notes:
`
`1. Value calculated as one module rank in this operating condition; all other module ranks
`in IDD2P (CKE LOW) mode.
`
`PDF: 09005aef8339ef97
`htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
`
`12
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 2008 Micron Technology, Inc. All rights reserved.
`
`Netlist Ex 2045
`Samsung v Netlist
`IPR2022-00996
`
`
`
`1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
`IDD Specifications
`
`2. Value calculated reflects all module ranks in this operating condition.
`
`Table 12: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M)
`
`Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
`ponent data sheet
`
`Parameter
`Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD),
`tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
`bus inputs are switching; Data bus inputs are switching
`Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL =
`CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
`(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
`switching; Data pattern is same as IDD4W
`Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
`LOW; Other control and address bus inputs are stable; Data bus inputs are float-
`ing
`Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is
`HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-
`puts are floating
`Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH,
`S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
`are switching
`Active power-down current: All device banks open;
`tCK = tCK (IDD); CKE is LOW; Other control and address
`bus inputs are stable; Data bus inputs are floating
`Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
`MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Oth-
`er control and address bus inputs are switching; Data bus inputs are switching
`Operating burst write current: All device banks open; Continuous burst writes;
`BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
`CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
`ing; Data bus inputs are switching
`Operating burst read current: All device banks open; Continuous burst read,
`IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
`tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
`puts are switching; Data bus inputs are switching
`Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) in-
`terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
`dress bus inputs are switching; Data bus inputs are switching
`Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
`bus inputs are floating; Data bus inputs are floating
`
`Fast PDN exit MR[12] = 0
`Slow PDN exit MR[12] = 1
`
`Symbol
`1
`IDD0
`
`-1GA
`680
`
`-80E/
`-800 -667 Units
`600
`560 mA
`
`1
`
`IDD1
`
`760
`
`680
`
`640 mA
`
`IDD2P
`
`2
`
`160
`
`160
`
`160 mA
`
`2
`IDD2Q
`
`448
`
`384
`
`384 mA
`
`2
`IDD2N
`
`544
`
`448
`
`384 mA
`
`IDD3P
`
`2
`
`512
`