Memory Module Specifications
`
`KVR667D2D4F5/2G
`2GB 256M x 72-Bit PC2-5300
`CL5 ECC 240-Pin FBDIMM
`
`Description:
`This document describes ValueRAM's 2GB (256M x 72-bit) PC2-5300 CL5 SDRAM (Synchronous DRAM) "fully
`buffered" ECC "dual rank" memory module. This module is based on thirty-six 128M x 4-bit 667MHz DDR2 FBGA
`components. The module also includes an AMB device (Advanced Memory Buffer). The electrical and mechanical
`specifications are as follows:
`
`Feature:
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`·
`
`FBDIMM Module: 240-pin
`
`JEDEC Standard: R/C H
`
`Memory Organization: 2 rank of x4 devices
`
`DDR2 DRAM Interface: SSTL_18
`
`DDR2 Speed Grade: 667 Mbps
`
`CAS Latency: 5-5-5
`
`Module Bandwidth: 5.3 GB/s
`
`FBDIMM Channel Peak Throughput: 8.0 GB/s
`
`DRAM: VDD = VDDQ = 1.8V
`
`AMB: VCC = VCCFBD = 1.5V
`
`EEPROM: VDDSPD = 3.3V (typical)
`
`Heat Spreader: AMB-only heat sink
`
`PCB Height: 30.35mm, double-side
`
`RoHS Compliant
`
`VALUERAM0483-001.A00
`
`04/14/06
`
`Page 1
`
`Netlist Ex 2042
`Samsung v Netlist
`IPR2022-00996
`
`

`

`DDR2 240-pin FBDIMM Pinout:
`
`Pin
`#
`
`Front
`Side
`
`VDD
`
`VDD
`
`1
`
`2
`
`3
`
`Pin
`#
`
`121
`
`122
`
`123
`
`Back
`Side
`
`VDD
`
`VDD
`
`Pin
`#
`
`31
`
`32
`
`33
`
`Front
`Side
`
`PN3
`
`PN3
`
`Pin
`#
`
`151
`
`152
`
`153
`
`Back
`Side
`
`SN3
`
`SN3
`
`VSS
`
`Pin
`#
`
`61
`
`62
`
`63
`
`Front
`Side
`
`PN9
`
`VSS
`
`PN10
`
`Pin
`#
`
`181
`
`182
`
`183
`
`Back
`Side
`
`SN9
`
`VSS
`
`SN10
`
`Pin
`#
`
`91
`
`92
`
`93
`
`Front
`Side
`
`PS9
`
`VSS
`
`PS5
`
`Pin
`#
`
`211
`
`212
`
`213
`
`Back
`Side
`
`SS9
`
`VSS
`
`SS5
`
`T E C H N O L O G Y
`
`VDD
`
`VSS
`
`VDD
`
`VDD
`
`124
`
`125
`
`126
`
`4
`
`5
`
`6
`
`VDD
`
`VSS
`
`VDD
`
`VDD
`
`34
`
`35
`
`36
`
`VSS
`
`PN4
`
`PN4
`
`VSS
`
`PN5
`
`154
`
`155
`
`156
`
`157
`
`SN4
`
`SN4
`
`VSS
`
`SN5
`
`64
`
`65
`
`66
`
`67
`
`PN10
`
`VSS
`
`PN11
`
`PN11
`
`184
`
`185
`
`186
`
`187
`
`SN10
`
`VSS
`
`SN11
`
`SN11
`
`94
`
`95
`
`96
`
`97
`
`PS5
`
`VSS
`
`PS6
`
`PS6
`
`214
`
`215
`
`216
`
`217
`
`SS5
`
`VSS
`
`SS6
`
`SS6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`VDD
`
`VSS
`
`VCC
`
`VCC
`
`127
`
`128
`
`129
`
`130
`
`131
`
`VDD
`
`VSS
`
`VCC
`
`VCC
`
`37
`
`38
`
`39
`
`40
`
`41
`
`PN5
`
`VSS
`
`PN13
`
`PN13
`
`158
`
`159
`
`160
`
`161
`
`SN5
`
`VSS
`
`SN13
`
`SN13
`
`68
`
`69
`
`70
`
`VSS
`
`188
`
`VSS
`
`KEY
`
`189
`
`190
`
`VSS
`
`PS0
`
`VSS
`
`SS0
`
`98
`
`99
`
`100
`
`101
`
`VSS
`
`PS7
`
`PS7
`
`218
`
`219
`
`220
`
`221
`
`VSS
`
`SS7
`
`SS7
`
`VSS
`
`VCC
`
`VCC
`
`VSS
`
`132
`
`133
`
`134
`
`12
`
`13
`
`14
`
`VSS
`
`VCC
`
`VCC
`
`VSS
`
`42
`
`43
`
`44
`
`45
`
`VSS
`
`VSS
`
`RFU*
`
`RFU*
`
`162
`
`163
`
`164
`
`165
`
`VSS
`
`VSS
`
`RFU*
`
`RFU*
`
`71
`
`72
`
`73
`
`74
`
`PS0
`
`VSS
`
`PS1
`
`PS1
`
`191
`
`192
`
`193
`
`194
`
`SS0
`
`VSS
`
`SS1
`
`SS1
`
`102
`
`103
`
`104
`
`105
`
`VSS
`
`PS8
`
`PS8
`
`VSS
`
`222
`
`223
`
`224
`
`225
`
`VSS
`
`SS8
`
`SS8
`
`VSS
`
`15
`
`16
`
`VTT
`
`VID1
`
`135
`
`136
`
`VTT
`
`VID0
`
`17 RESET 137 DNU/M_Test
`
`18
`
`19
`
`VSS
`RFU**
`
`138
`
`139
`
`VSS
`RFU**
`
`46
`
`47
`
`48
`
`49
`
`VSS
`
`VSS
`
`PN12
`
`PN12
`
`166
`
`167
`
`168
`
`169
`
`VSS
`
`VSS
`
`SN12
`
`SN12
`
`75
`
`76
`
`77
`
`78
`
`VSS
`
`PS2
`
`PS2
`
`195
`
`196
`
`197
`
`198
`
`VSS
`
`SS2
`
`SS2
`
`106
`
`107
`
`108
`
`109
`
`RFU**
`
`RFU**
`
`VSS
`
`VDD
`
`226
`
`227
`
`228
`
`229
`
`RFU**
`
`RFU**
`
`VSS
`
`SCK
`
`SCK
`
`20
`
`21
`
`22
`
`RFU**
`
`VSS
`
`PN0
`
`PN0
`
`140
`
`141
`
`142
`
`143
`
`RFU**
`
`VSS
`
`SN0
`
`SN0
`
`50
`
`51
`
`52
`
`53
`
`VSS
`
`PN6
`
`PN6
`
`170
`
`171
`
`172
`
`173
`
`VSS
`
`SN6
`
`SN6
`
`79
`
`80
`
`81
`
`82
`
`VSS
`
`PS3
`
`PS3
`
`VSS
`
`PS4
`
`199
`
`200
`
`201
`
`202
`
`VSS
`
`SS3
`
`SS3
`
`VSS
`
`SS4
`
`VDD
`
`VSS
`
`VDD
`
`VDD
`
`110
`
`111
`
`112
`
`113
`
`VSS
`
`VDD
`
`VDD
`
`230
`
`231
`
`232
`
`233
`
`23
`
`24
`
`25
`
`26
`
`VSS
`
`PN1
`
`PN1
`
`144
`
`145
`
`146
`
`VSS
`
`SN1
`
`SN1
`
`54
`
`55
`
`56
`
`VSS
`
`PN7
`
`PN7
`
`VSS
`
`PN8
`
`174
`
`175
`
`176
`
`177
`
`VSS
`
`SN7
`
`SN7
`
`VSS
`
`SN8
`
`83
`
`84
`
`85
`
`86
`
`PS4
`
`VSS
`
`VSS
`
`RFU*
`
`203
`
`204
`
`205
`
`206
`
`SS4
`
`VSS
`
`VSS
`
`RFU*
`
`114
`
`115
`
`116
`
`117
`
`VDD
`
`VSS
`
`VDD
`
`VDD
`
`234
`
`235
`
`236
`
`237
`
`VDD
`
`VSS
`
`VDD
`
`VDD
`
`27
`
`28
`
`29
`
`30
`
`VSS
`
`PN2
`
`PN2
`
`VSS
`
`147
`
`148
`
`149
`
`150
`
`VSS
`
`SN2
`
`SN2
`
`VSS
`
`57
`
`58
`
`59
`
`60
`
`PN8
`
`VSS
`
`PN9
`
`178
`
`179
`
`180
`
`SN8
`
`VSS
`
`SN9
`
`87
`
`88
`
`89
`
`90
`
`RFU*
`
`VSS
`
`VSS
`
`PS9
`
`207
`
`208
`
`209
`
`210
`
`RFU*
`
`VSS
`
`VSS
`
`SS9
`
`VTT
`
`SA2
`
`SDA
`
`SCL
`
`VTT
`
`VDDSPD
`
`SA0
`
`SA1
`
`238
`
`239
`
`240
`
`118
`
`119
`
`120
`
`RFU = Reserved Future Use.
`* These pin positions are reserved for forwarded clocks to be used in future module implementations
`** These pin positions are reserved for future architecture flexibility
`1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN13,
`PS9/PS9, SS9/SS9
`
`VALUERAM0483-001.A00
`
`Page 2
`
`Netlist Ex 2042
`Samsung v Netlist
`IPR2022-00996
`
`

`

`DIMM Connector Pin Description:
`
`Pin Name
`
`Pin Description
`
`SCK
`
`SCK
`
`PN[13:0]
`
`PN[13:0]
`
`PS[9:0]
`
`PS[9:0]
`
`SN[13:0]
`
`SN[13:0]
`
`SS[9:0]
`
`SS[9:0]
`
`SCL
`
`SDA
`
`System Clock Input, positive line1
`
`System Clock Input, negative line1
`Primary Northbound Data, positive lines
`
`Primary Northbound Data, negative lines
`
`Primary Southbound Data, positive lines
`
`Primary Southbound Data, negative lines
`
`Secondary Northbound Data, positive lines
`
`Secondary Northbound Data, negative lines
`
`Secondary Southbound Data, positive lines
`
`Secondary Southbound Data, negative lines
`
`Serial Presence Detect (SPD) Clock Input
`
`SPD Data Input / Output
`
`SA[2:0]
`
`SPD Address Inputs, also used to select the DIMM number in the AMB
`
`VID[1:0]
`
`RESET
`
`RFU
`
`VCC
`VDD
`VTT
`VDDSPD
`VSS
`
`DNU/M_Test
`
`Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
`VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is V CC value: OPEN = 1.5 V, GND = 1.2 V
`AMB reset signal
`
`Reserved for Future Use2
`
`AMB Core Power and AMB Channel Interface Power (1.5 Volt)
`
`DRAM Power and AMB DRAM I/O Power (1.8 Volt)
`
`DRAM Address/Command/Clock Termination Power (V DD/2)
`
`SPD Power
`
`Ground
`
`The DNU/M_Test pin provides an exter nal connection on R/Cs A-D for testing
`the margin of Vref which is produced by a voltage divider on the module. It
`is not intended to be used in normal system operation and must not be
`connected (DNU) in a system. This test pin may have other features on future card designs
`and if it does, will be included in this specification at that time.
`1
`
`Total
`
`1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency
`2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
`
`T E C H N O L O G Y
`
`Count
`
`1
`
`1
`
`14
`
`14
`
`10
`
`10
`
`14
`
`14
`
`10
`
`10
`
`1
`
`1
`
`3
`
`2
`
`1
`
`16
`
`8
`
`24
`
`4
`
`1
`
`80
`
`1
`
`240
`
`VALUERAM0483-001.A00
`
`Page 3
`
`Netlist Ex 2042
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Functional Block Diagram:
`
`T E C H N O L O G Y
`
`VSS
`S1
`S0
`
`DQS0
`DQS0
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQS1
`DQS1
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQS2
`DQS2
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`CS DQS
`
`DQS
`
`D0
`
`CS DQS
`
`DQS
`
`D1
`
`CS DQS
`
`DQS
`
`D18
`
`CS DQS
`
`DQS
`
`D19
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQS
`
`DM
`
`CS DQS
`
`DQS
`
`DQS9
`DQS9
`
`DQ4
`DQ5
`DQ6
`DQ7
`DQS10
`DQS10
`
`DQ12
`DQ13
`DQ14
`DQ15
`DQS11
`DQS11
`
`CS DQS
`
`DQS
`
`D9
`
`CS DQS
`
`DQS
`
`D10
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`CS DQS
`
`DQS
`
`D27
`
`CS DQS
`
`DQS
`
`D28
`
`DQS
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQS3
`DQS3
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQS4
`DQS4
`
`CS DQS
`
`D2
`
`CS DQS
`
`DQS
`
`D3
`
`CS DQS
`
`DQS
`
`D4
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D20
`
`CS DQS
`
`DQS
`
`D21
`
`CS DQS
`
`DQS
`
`D22
`
`CS DQS
`
`DQS
`
`D11
`
`CS DQS
`
`DQS
`
`D12
`
`CS DQS
`
`DQS
`
`D13
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`CS DQS
`
`D29
`
`CS DQS
`
`DQS
`
`D30
`
`CS DQS
`
`DQS
`
`D31
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQ20
`DQ21
`DQ22
`DQ23
`DQS12
`DQS12
`
`DQ28
`DQ29
`DQ30
`DQ31
`DQS13
`DQS13
`
`DQ36
`DQ37
`DQ38
`DQ39
`DQS14
`DQS14
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQS5
`DQS5
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQS6
`DQS6
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQS7
`DQS7
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`CS DQS
`
`DQS
`
`D5
`
`CS DQS
`
`DQS
`
`D6
`
`CS DQS
`
`DQS
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`CS DQS
`
`DQS
`
`D23
`
`CS DQS
`
`DQS
`
`D24
`
`CS DQS
`
`DQS
`
`DQ44
`DQ45
`DQ46
`DQ47
`DQS15
`DQS15
`
`DQ52
`DQ53
`DQ54
`DQ55
`DQS16
`DQS16
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`CS DQS
`
`DQS
`
`D14
`
`CS DQS
`
`DQS
`
`D15
`
`CS DQS
`
`DQS
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`CS DQS
`
`DQS
`
`D32
`
`CS DQS
`
`DQS
`
`D33
`
`CS DQS
`
`DQS
`
`D7
`
`CS DQS
`
`DQS
`
`D8
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D25
`
`CS DQS
`
`DQS
`
`D26
`
`DQ60
`DQ61
`DQ62
`DQ63
`DQS17
`DQS17
`
`CB4
`CB5
`CB6
`CB7
`
`All address/command/control/clock
`
`SN0-SN13
`SN0-SN13
`SS0-SS9
`SS0-SS9
`S0 -> CS (D0-D17)
`CKE0 -> CKE (D0-D17)
`S1 -> CS (D18-D35)
`CKE1 -> CKE (D18-D35)
`ODT -> ODT0 (all SDRAMs)
`BA0-BA2 (all SDRAMs)
`A0-A15 (all SDRAMs)
`RAS (all SDRAMs)
`CAS (all SDRAMs)
`WE (all SDRAMs)
`CK/CK (all SDRAMs)
`
`Serial PD
`
`SCL
`
`WP
`
`A0
`
`A1 A2
`
`SDA
`
`SA0 SA1 SA2
`
`VREF
`VSS
`Notes:
`1. DQ-to-I/O wiring may be changed within a nibble
`2. There are two physical copies of each address/command/control
`3. There are four physical copies of each clock
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`VTT
`
`D16
`
`CS DQS
`
`DQS
`
`D17
`
`VTT
`VCC
`VDDSPD
`
`VDD
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D34
`
`CS DQS
`
`DQS
`
`D35
`
`Terminators
`AMB
`
`SPD, AMB
`
`D0-D35, AMB
`
`D0-D35
`
`D0-D35, SPD,
`AMB
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DM
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`AMB
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQS8
`DQS8
`
`CB0
`CB1
`CB2
`CB3
`
`PN0-PN13
`PN0-PN13
`PS0-PS9
`PS0-PS9
`
`DQ0-DQ63
`CB0-CB7
`DQS0-DQS17
`DQS0-DQS17
`SCL
`SDA
`SA1-SA2
`SA0
`
`RESET
`SCK/SCK
`
`VALUERAM0483-001.A00
`
`Page 4
`
`Netlist Ex 2042
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Architecture:
`Advanced Memory Buffer Pin Description:
`
`Pin Name
`
`Pin Description
`
`FB-DIMM Channel Signals
`System Clock Input, positive line
`
`System Clock Input, negative line
`
`Primary Northbound Data, positive lines
`
`Primary Northbound Data, negative lines
`
`Primary Southbound Data, positive lines
`
`Primary Southbound Data, negative lines
`
`Secondary Northbound Data, positive lines
`
`Secondary Northbound Data, negative lines
`
`Secondary Southbound Data, positive lines
`
`Secondary Southbound Data, negative lines
`
`To an external precision calibration resistor connected to Vcc
`DDR2 Interface Signals
`Data Strobes, positive lines
`
`Data Strobes, negative lines
`
`SCK
`
`SCK
`
`PN[13:0]
`
`PN[13:0]
`
`PS[9:0]
`
`PS[9:0]
`
`SN[13:0]
`
`SN[13:0]
`
`SS[9:0]
`
`SS[9:0]
`
`FBDRES
`
`DQS[8:0]
`
`DQS[8:0]
`
`DQS[17:9]/DM[8:0] Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes.
`
`DQS[17:9]
`
`Data Strobes (x4 DRAM only), negative lines
`
`DQ[63:0]
`
`CB[7:0]
`
`Data
`
`Checkbits
`
`A[15:0]A, A[15:0]B
`
`Addresses. A10 is part of the pre-charge command
`
`BA[2:0]A, BA[2:0]B Bank Addresses
`
`RASA, RASB
`
`Part of command, with CAS, WE, and CS[1:0].
`
`CASA, CASB
`
`Part of command, with RAS, WE, and CS[1:0].
`
`WEA, WEB
`
`Part of command, with RAS, CAS, and CS[1:0].
`
`ODTA, ODTB
`
`On-die Termination Enable
`
`CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank)
`
`CS[1:0]A, CS[1:0]B Chip Select (one per rank)
`
`CLK[3:0]
`
`CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out-
`put disabled when not in use.
`
`CLK[3:0]
`
`Negative lines for CLK[3:0]
`
`DDRC_C14
`
`DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18.
`
`DDRC_B18
`
`DDR Compensation: Resistor connected to common return pin DDRC_C14
`
`DDRC_C18
`
`DDRC_B12
`
`DDRC_C12
`
`DDR Compensation: Resistor connected to common return pin DDRC_C14
`DDR Compensation: Resistor connected to VSS
`DDR Compensation: Resistor connected to VDD
`
`T E C H N O L O G Y
`
`Count
`99
`
`1
`
`1
`
`14
`
`14
`
`10
`
`10
`
`14
`
`14
`
`10
`
`10
`
`1
`175
`
`9
`
`9
`
`9
`
`9
`
`64
`
`8
`
`32
`
`6
`
`2
`
`2
`
`2
`
`2
`
`4
`
`4
`
`4
`
`4
`
`1
`
`1
`
`1
`
`1
`
`1
`
`VALUERAM0483-001.A00
`
`Page 5
`
`Netlist Ex 2042
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Advanced Memory Buffer Pin Description:
`
`SPD Bus Interface Signals
`Serial Presence Detect (SPD) Clock Input
`
`SPD Data Input / Output
`
`SPD Address Inputs, also used to select the DIMM number in the AMB
`Miscellaneous Signals
`PLL Clock Observability Output
`
`Analog VCC for the PLL. Tied with low pass filter to VCC.
`
`Analog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM.
`
`SCL
`
`SDA
`
`SA[2:0]
`
`PLLTSTO
`
`VCCAPLL
`
`VSSAPLL
`
`TEST_pin#
`
`Leave floating on the DIMM
`
`TESTLO_pin#
`
`BFUNC
`
`RESET
`
`NC
`
`RFU
`
`VCC
`VCCFBD
`VDD
`VDDSPD
`VSS
`
`Tie to ground on the DIMM2
`Tie to ground to set functionality as “buffer on DIMM.”
`
`AMB reset signal
`
`No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power
`islands.
`
`Reserved for Future Use
`Power/Ground Signals
`AMB Core Power (1.5 Volt)
`
`AMB Channel I/O Power (1.5 Volt)
`
`AMB DRAM I/O Power (1.8 Volt)
`
`SPD Power (3.3 Volt)
`
`Ground
` Total
`
`T E C H N O L O G Y
`
`5
`
`1
`
`1
`
`3
`163
`
`1
`
`1
`
`1
`
`6
`
`5
`
`1
`
`1
`
`129
`
`18
`213
`
`24
`
`8
`
`24
`
`1
`
`156
`655
`
`1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.
`2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero
`ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production
`DIMMs with a direct connection to ground.
`
`VALUERAM0483-001.A00
`
`Page 6
`
`Netlist Ex 2042
`Samsung v Netlist
`IPR2022-00996
`
`

`

`Package Dimensions:
`
`T E C H N O L O G Y
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`T E C H N O L O G Y
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`AMB
`Advance Memory Buffer
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`FBGA DDR2
`
`SDRAM
`
`(Units = millimeters)
`
`0.346 (8.8)
`MAX with heat sink
`
`Units: inches (millimeters)
`
`45°x 0.0071(0.18)
`
`0.047 (1.19)
`
`0.042 (1.06)
`
`0.042 (1.06)
`
`Detail A
`
`0.054 (1.37)
`0.046 (1.17)
`
`VALUERAM0483-001.A00
`
`Page 7
`
`Netlist Ex 2042
`Samsung v Netlist
`IPR2022-00996
`
`